From patchwork Fri Oct 13 01:05:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 825191 X-Patchwork-Delegate: prafulla@marvell.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ewfeBrn6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yCqK61qHTz9sNc for ; Fri, 13 Oct 2017 12:05:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B0E7BC21C29; Fri, 13 Oct 2017 01:05:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CBE44C21F04; Fri, 13 Oct 2017 01:05:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9FDD6C21F04; Fri, 13 Oct 2017 01:05:34 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 0A7A8C21C29 for ; Fri, 13 Oct 2017 01:05:34 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id e64so7445275pfk.9 for ; Thu, 12 Oct 2017 18:05:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=SRjgfO+KLAE0GR27qsmZaSKETSF8V96lDstorL6XXgY=; b=ewfeBrn6ln/FDfyMjOVzqe4v7g9fbBTsICB5ArYBLZmQxg1PLPCQz4QUH/Ad2DPLB/ ligRZ29rm1bMePfTo98aYKuKX8uAIL+lFKsCr0IQI64wZBZXil5eKEtsrQK90CjBEh0u M+REqdE71eBEX6x/mC2Rj5y2TN+zUkNCVgolZfviuIOPHZOq0lTany4LVmhxWCIV8Ohe 0nHOTFMIlwaB5jrM0Pxh3oIqcks4MiEPzpbwi9w4S6qQOds+ABM0mWOz3ZrevIcNGg2I AdgxFrwyEKZrUXPvAD876YwncZWyNMQzhc5kv4lKJXo1eWwKAbE4GQYVyeUINJBs8IQo 8suQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SRjgfO+KLAE0GR27qsmZaSKETSF8V96lDstorL6XXgY=; b=Wr6obOAv+uDCsv1XrQ+xLGEJx8DLN9ChLQEaGajIYHc/XTXeUE8QDR6ouWoTnHDebr l8Oh4tVhC6aMLHkqcKSjovdtNoszmJE3aiDqKXVMhX3pMp1gk6sdrGb5EavtDu+HH6De fTIxsWpRhjA1Seg1rrewrp8/oIfT3yQJkfpxjPOw0Dpsn/2lQ+d8YyE6Iu07UUG7fTZu Wq/2Wi3l9TGluMd6oj6aUraukSXODY7950cVe5YPDLYvW/N+30/7hMxCawvXDa4PWhbP sYsCmEO/lOWPejKFxO1azHN/+YkNYnXYvWY7iY2yp9vt3gsspFnSCPnerUwbtmdoEilN jS5w== X-Gm-Message-State: AMCzsaWbR+t09PAvjRFk6J1D5mDzc3m2K1hDOhLBjlWGbsGJgcV/QD0N x7DxKglYv5mRyfbdeAkMQMGP6mFB X-Google-Smtp-Source: AOwi7QDyn9xxmCB7U8r/sOpdPpPjnINk4ZEvOhsApM0LmnlAbVBgH26zd3iBKeuQZLMrU4QeWSoz4A== X-Received: by 10.101.65.75 with SMTP id x11mr1595439pgp.388.1507856732122; Thu, 12 Oct 2017 18:05:32 -0700 (PDT) Received: from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:22:3a2c:4aff:fe70:2b02]) by smtp.gmail.com with ESMTPSA id k24sm34391644pfj.151.2017.10.12.18.05.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 18:05:31 -0700 (PDT) From: Chris Packham To: u-boot@lists.denx.de Date: Fri, 13 Oct 2017 14:05:21 +1300 Message-Id: <20171013010521.12017-1-judge.packham@gmail.com> X-Mailer: git-send-email 2.14.2 Cc: Jagan Teki , Kalyan Kinthada , Stefan Roese , Chris Packham Subject: [U-Boot] [PATCH] spi: kirkwood_spi: implement workaround for FE-9144572 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Erratum NO. FE-9144572: The device SPI interface supports frequencies of up to 50 MHz. However, due to this erratum, when the device core clock is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and CPOL=CPHA=1 there might occur data corruption on reads from the SPI device. Implement the workaround by setting the TMISO_SAMPLE value to 0x2 in the timing1 register. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/include/asm/arch-mvebu/spi.h | 6 ++++ drivers/spi/kirkwood_spi.c | 62 +++++++++++++++++++++++++++++++++-- 2 files changed, 65 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index 3545aed17347..1de510ea6da9 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -57,6 +57,12 @@ struct kwspi_registers { #define KWSPI_TXLSBF (1 << 13) #define KWSPI_RXLSBF (1 << 14) +/* Timing Parameters 1 Register */ +#define KW_SPI_TMISO_SAMPLE_OFFSET 6 +#define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET) +#define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET) +#define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET) + #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ #define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 0c6bd295cde9..7992556d49eb 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -243,6 +243,16 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, /* Here now the DM part */ +enum mvebu_spi_type { + ORION_SPI, + ARMADA_SPI, +}; + +struct mvebu_spi_dev { + enum mvebu_spi_type typ; + bool is_errata_50mhz_ac; +}; + struct mvebu_spi_platdata { struct kwspi_registers *spireg; }; @@ -269,10 +279,30 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) return 0; } +static void +mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + u32 data = readl(®->timing1); + + data &= ~KW_SPI_TMISO_SAMPLE_MASK; + + if (CONFIG_SYS_TCLK == 250000000 && + mode & SPI_CPOL && + mode & SPI_CPHA) + data |= KW_SPI_TMISO_SAMPLE_2; + else + data |= KW_SPI_TMISO_SAMPLE_1; + + writel(data, ®->timing1); +} + static int mvebu_spi_set_mode(struct udevice *bus, uint mode) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); struct kwspi_registers *reg = plat->spireg; + const struct mvebu_spi_dev *drvdata; u32 data = readl(®->cfg); data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF); @@ -286,6 +316,10 @@ static int mvebu_spi_set_mode(struct udevice *bus, uint mode) writel(data, ®->cfg); + drvdata = (struct mvebu_spi_dev *)dev_get_driver_data(bus); + if (drvdata->is_errata_50mhz_ac) + mvebu_spi_50mhz_ac_timing_erratum(bus, mode); + return 0; } @@ -343,10 +377,32 @@ static const struct dm_spi_ops mvebu_spi_ops = { */ }; +static const struct mvebu_spi_dev armada_xp_spi_dev_data = { + .typ = ARMADA_SPI, +}; + +static const struct mvebu_spi_dev armada_375_spi_dev_data = { + .typ = ARMADA_SPI, +}; + +static const struct mvebu_spi_dev armada_380_spi_dev_data = { + .typ = ARMADA_SPI, + .is_errata_50mhz_ac = true, +}; + static const struct udevice_id mvebu_spi_ids[] = { - { .compatible = "marvell,armada-375-spi" }, - { .compatible = "marvell,armada-380-spi" }, - { .compatible = "marvell,armada-xp-spi" }, + { + .compatible = "marvell,armada-375-spi", + .data = (ulong)&armada_375_spi_dev_data + }, + { + .compatible = "marvell,armada-380-spi", + .data = (ulong)&armada_380_spi_dev_data + }, + { + .compatible = "marvell,armada-xp-spi", + .data = (ulong)&armada_xp_spi_dev_data + }, { } };