From patchwork Mon Dec 3 05:27:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006660 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="CPFNvMwU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YSz2Zxlz9s3Z for ; Mon, 3 Dec 2018 16:29:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 05DEAC2201E; Mon, 3 Dec 2018 05:28:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C1FC3C22691; Mon, 3 Dec 2018 05:28:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C162CC22685; Mon, 3 Dec 2018 05:28:07 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id B6F3BC22086 for ; Mon, 3 Dec 2018 05:28:02 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id e5so5852276plb.5 for ; Sun, 02 Dec 2018 21:28:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=18QrhhAgnziZ/rQVrwBMVjCL5MAiBseC9VBMZ9qU45c=; b=CPFNvMwU02njG/P9o+z0ETzG9lxTjk2b40N3SOLc7za1tnDYjmDeu17uC5XqzkL5q8 DIqaufvOEcgCHs/B2+/iH20drzSzXrsVKkfMie7hp5x9w5vWY8n1hU1rR9YvQIJZ0Bep DdOUq5zGDK5WwUQlp+3FordtJl1DLkELnIOwKJRf9fuIHq5q88LvXJ43mIzZnH0nhG8U cNYOc9b9YhFe6fcRbHRv3grp8ox6QXLCGxsntPdYy2Sj4b2vY5R3ZNjULSYmHB/8uytN FA3iOx5UuHT5WE6u9w8eSvBOaUBKWQVeyMoM/8/FMJxjXluFjY531vzXU4dsDmFag4Pn UXgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=18QrhhAgnziZ/rQVrwBMVjCL5MAiBseC9VBMZ9qU45c=; b=mo9ub73Z0gOGDRmbeuE+xTKB+MNxEzdUeq1KaiDXncX3bt6a6NZa/ynLS9NXdT5WBg t+OJ9HXFO95stbc5rawTznuPBza6ANIksoB/ez5Kzrzg3yP0gwALe+6S9JKm89KF5A39 RicCPaxXwEzAcBk6n0GsdaaS4IE8w9te5QE67/VUYx4WydIzX1eah1YM2RdOW7A0yDuE UIgrvJAO0Yw1FhfbFwCL13iGYe/ANaG9q+p2sAnyQpKL9t6XmZQHPfRzAMkJ8G2CJ7W5 gKqRcC6hSNvpxlGPMO3aj7Vi+3zpbFLtsff6qHZmj0WR/MkK4/3guxUUfnOgqUP3UgIa kqWg== X-Gm-Message-State: AA+aEWawcC9IZN7zNNcQr2iJCMehHZjSd9DcThDEg7bfAFIyH6oUX7HP eZcZ7rzRuPoZ6+X0n1baUyorQg== X-Google-Smtp-Source: AFSGD/VKkvKRA7/2LrwvLTxKqFwV0f41hJvornuCEqPP6x3tLA+5azZl0tIYh3g9LiF6VovWPwuG6w== X-Received: by 2002:a17:902:2ac3:: with SMTP id j61mr14616687plb.185.1543814881196; Sun, 02 Dec 2018 21:28:01 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.27.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:00 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:40 +0530 Message-Id: <20181203052743.29036-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 1/4] riscv: Add kconfig option to run U-Boot in S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s CSRs instead of m CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Kconfig | 5 +++++ arch/riscv/cpu/start.S | 23 +++++++++++++++-------- arch/riscv/include/asm/encoding.h | 6 ++++++ arch/riscv/lib/interrupts.c | 31 ++++++++++++++++++++++--------- 4 files changed, 48 insertions(+), 17 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3e0af55e71..732a357a99 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -55,6 +55,11 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y +config RISCV_SMODE + bool "Run in S-Mode" + help + Enable this option to build U-Boot for RISC-V S-Mode + config 32BIT bool diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 15e1b8199a..3f055bdb7e 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -41,10 +41,10 @@ _start: li t0, CONFIG_SYS_SDRAM_BASE SREG a2, 0(t0) la t0, trap_entry - csrw mtvec, t0 + csrw MODE_PREFIX(tvec), t0 /* mask all interrupts */ - csrw mie, zero + csrw MODE_PREFIX(ie), zero /* Enable cache */ jal icache_enable @@ -166,7 +166,7 @@ fix_rela_dyn: */ la t0, trap_entry add t0, t0, t6 - csrw mtvec, t0 + csrw MODE_PREFIX(tvec), t0 clear_bss: la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ @@ -238,17 +238,24 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) - csrr a0, mcause - csrr a1, mepc + csrr a0, MODE_PREFIX(cause) + csrr a1, MODE_PREFIX(epc) mv a2, sp jal handle_trap - csrw mepc, a0 + csrw MODE_PREFIX(epc), a0 +#ifdef CONFIG_RISCV_SMODE +/* + * Remain in S-mode after sret + */ + li t0, SSTATUS_SPP +#else /* * Remain in M-mode after mret */ li t0, MSTATUS_MPP - csrs mstatus, t0 +#endif + csrs MODE_PREFIX(status), t0 LREG x1, 1*REGBYTES(sp) LREG x2, 2*REGBYTES(sp) LREG x3, 3*REGBYTES(sp) @@ -281,4 +288,4 @@ trap_entry: LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES - mret + MODE_PREFIX(ret) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 9ea50ce640..97cf906aa6 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -7,6 +7,12 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H +#ifdef CONFIG_RISCV_SMODE +#define MODE_PREFIX(__suffix) s##__suffix +#else +#define MODE_PREFIX(__suffix) m##__suffix +#endif + #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 903a1c4cd5..3aff006977 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -34,17 +34,30 @@ int disable_interrupts(void) return 0; } -ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) +ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) { - ulong is_int; + ulong is_irq, irq; - is_int = (mcause & MCAUSE_INT); - if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) - external_interrupt(0); /* handle_m_ext_interrupt */ - else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) - timer_interrupt(0); /* handle_m_timer_interrupt */ - else - _exit_trap(mcause, epc, regs); + is_irq = (cause & MCAUSE_INT); + irq = (cause & ~MCAUSE_INT); + + if (is_irq) { + switch (irq) { + case IRQ_M_EXT: + case IRQ_S_EXT: + external_interrupt(0); /* handle external interrupt */ + break; + case IRQ_M_TIMER: + case IRQ_S_TIMER: + timer_interrupt(0); /* handle timer interrupt */ + break; + default: + _exit_trap(cause, epc, regs); + break; + }; + } else { + _exit_trap(cause, epc, regs); + } return epc; } From patchwork Mon Dec 3 05:27:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006662 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="WaeAXGp4"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YTl43bNz9s3Z for ; Mon, 3 Dec 2018 16:29:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 343BDC22074; Mon, 3 Dec 2018 05:28:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 84AC8C21FEF; Mon, 3 Dec 2018 05:28:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5A606C220BC; Mon, 3 Dec 2018 05:28:11 +0000 (UTC) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by lists.denx.de (Postfix) with ESMTPS id 66C5DC21FF7 for ; Mon, 3 Dec 2018 05:28:07 +0000 (UTC) Received: by mail-pf1-f195.google.com with SMTP id w73so5756372pfk.10 for ; Sun, 02 Dec 2018 21:28:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cKbxcUi8EFtXRX6ZKTRteFrEA1MNrvc3hL5H4tJKH1Y=; b=WaeAXGp4Mp/M6nTbYAH90ENOEe97rJKo8XGHQpljd69LPkFQCSSmi3Eh7A2fhhoxg9 hWM2ElZH5nkIji59GDJSqTVi0frmET+orVvajXUspKSMe0spdPuct6T0WnvUUoD2P5UD NX3VU5s2Fo1qQkjT1WxZGxPlc2O7kXRwZTZyXWIH4UJfHAlYEPc03yloxcIn8vu/wOsS Fqip6G2Ee/Akgera25imz8y3jYoty0Eq1e54FFnn7sZODeCr+sfG1xUdWX5yFfIPMdd3 aYEBlH4XPEHGmEpjibNH62lzY6ept+Ir6qMn+WwGfbmysY7LqHrHh/XuV/xPTTXr9O0N 4pUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cKbxcUi8EFtXRX6ZKTRteFrEA1MNrvc3hL5H4tJKH1Y=; b=jfIwruwcELMNcAwhDUH5OQzgBB2VQP1asu/PNpDhSjiTpFWUjehfS9zcNZ47pFy/T7 0WRHedQniaiNBDU4TXCxH58yeWTkCKQhPUH2r4q9p16umRMEcf2l6WC/1GNhXTndCVvH XZqXgtSQhdAdduOSy+Mno4Bls6WgbQ7FRaT5t0+RMHxgWXaZzRn0R2Ik86qlKmcTR/rS atTkmC04KBFYHk0Wmu0MxGNHLTJmE+zkOwVV+N1rpMarIfhXepJdIflFh+68vDY4WCby rDE5ANWz6d0EHEer+aK+m5spYLttNP3UUkydQlTWv4x4TXUsgseVbpvSZx7MjOb8lUCo 0i+w== X-Gm-Message-State: AA+aEWY/9gxOY+FVhK8pDnE3/iCyAU12dhGia9QhVnHhh7buqdPQWSQb cJ6pt4QwoOtwhemqz9WUdE0vmA== X-Google-Smtp-Source: AFSGD/VtW8RVsfsq5iPFNah6tZ6TI9PI7zpjPz3TZTf5vIcmZVpaezXYq9SMwrt/9QC0apMOsMpKbg== X-Received: by 2002:a62:5ec5:: with SMTP id s188mr14248907pfb.145.1543814885824; Sun, 02 Dec 2018 21:28:05 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.28.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:05 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:41 +0530 Message-Id: <20181203052743.29036-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 2/4] riscv: qemu: Use different SYS_TEXT_BASE for S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot use 0x80000000 as SYS_TEXT_BASE when running in S-mode. Instead for S-mode, we use 0x80200000 as SYS_TEXT_BASE. Even Linux RISC-V kernel ignores/reserves memory range 0x80000000 to 0x80200000 because it runs in S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 33ca253432..56bb5337d4 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE - default 0x80000000 + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y From patchwork Mon Dec 3 05:27:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006661 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="sf1sMT4l"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YT01CJCz9sBh for ; Mon, 3 Dec 2018 16:29:08 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D3990C226D6; Mon, 3 Dec 2018 05:28:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 88312C22680; Mon, 3 Dec 2018 05:28:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4BFBC22074; Mon, 3 Dec 2018 05:28:16 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id C8942C220BC for ; Mon, 3 Dec 2018 05:28:11 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id 17so5197450pgg.1 for ; Sun, 02 Dec 2018 21:28:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kE5TOK27CoYULOVJYCIFjTFsjogrFvdIAWPXy8fp0sA=; b=sf1sMT4lnIZntlUpsMvw9mhcqWP+yYpxU79ftEvmk8JPvdx9J+h2sIRXaQFPLXgKnl XNKYQ754T2yMR64i2iv1abKgkzcFpsOi1A/VMbq72M/jdTuYyFbfTZwoBHabMbY57yh2 zY0OqC1AV1g+R3scJ5xY7mw7jNAbsb+XVvtmu8/8RxjWG4V7dddcHKyReXNqDAWXJISe EFnvnzZ4L1DgPLEEeZXW/Q8/kiqoFlRJRTLk6zgCvqZh31iY7USpsbWjfIUzX1xRqNaE kFsKzbBXTXqgr06wXG3ve+EiZ0QCJjkGbWzcJNfUeGl1zRBueooF9D6geqlYGOkLT4+x wqpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kE5TOK27CoYULOVJYCIFjTFsjogrFvdIAWPXy8fp0sA=; b=klh6Qojoot552JXzdUGMFZ6rtWPHe+vMpXro2L3aQm5m//04OJ3aXE3XjVxz+WKeaJ uPvqo078N7BLgdynaFslGAXJHzPi22IXTiI0YWvTJvU0+1ZtBsU83ZaNHzSxUs48ph7T St6Jl4KHwMXWGZrD0G4OQZhHptoy3oDN6FifGq5t9NHTgpCr8JelAjCnPns/+OgMpsPZ V3J0iH/xxBdD00/hG/3xItiaiXmGzlM0htD5nL0vMMjxhCcb7rdmyBCK+fAZMIZHpYrT KXCuN8kpkG6EbS8UtoIKdmAGyuU9dNf0lGjGuMudvo4OZC39T88RjfXTVP4XIABdQZqz KK3w== X-Gm-Message-State: AA+aEWZhUBLdEWNYUwYgPTE6+rjhNebR/K38UyuXJ6q6tlO/rl9Pv+ju V2nRuQVkWZFcHd805MJYgL31Bw== X-Google-Smtp-Source: AFSGD/XhqeLjqyDCVWAxEhq9hbSDpDWkOnna28llxSAoMZJ5TXF7uXa3RKOvkX6hC8QKCrPqCSA8Kw== X-Received: by 2002:a62:3c1:: with SMTP id 184mr2508732pfd.56.1543814890245; Sun, 02 Dec 2018 21:28:10 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.28.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:09 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:42 +0530 Message-Id: <20181203052743.29036-4-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 3/4] riscv: Add S-mode defconfigs for QEMU virt machine X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds S-mode defconfigs for QEMU virt machine so that we can run u-boot in S-mode on QEMU using M-mode runtime firmware (BBL or equivalent). Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- board/emulation/qemu-riscv/MAINTAINERS | 2 ++ configs/qemu-riscv32_smode_defconfig | 10 ++++++++++ configs/qemu-riscv64_smode_defconfig | 11 +++++++++++ 3 files changed, 23 insertions(+) create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index 3c6eb4f844..c701c83d77 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -4,4 +4,6 @@ S: Maintained F: board/emulation/qemu-riscv/ F: include/configs/qemu-riscv.h F: configs/qemu-riscv32_defconfig +F: configs/qemu-riscv32_smode_defconfig F: configs/qemu-riscv64_defconfig +F: configs/qemu-riscv64_smode_defconfig diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig new file mode 100644 index 0000000000..0a84ec1874 --- /dev/null +++ b/configs/qemu-riscv32_smode_defconfig @@ -0,0 +1,10 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig new file mode 100644 index 0000000000..b012443370 --- /dev/null +++ b/configs/qemu-riscv64_smode_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y From patchwork Mon Dec 3 05:27:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006663 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="IcsrnNZe"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YVW3Hpwz9sBh for ; Mon, 3 Dec 2018 16:30:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2CD34C226DB; Mon, 3 Dec 2018 05:29:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A9879C220BC; Mon, 3 Dec 2018 05:28:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 44D74C22086; Mon, 3 Dec 2018 05:28:20 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 3A422C22680 for ; Mon, 3 Dec 2018 05:28:16 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id a14so5837076plm.12 for ; Sun, 02 Dec 2018 21:28:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=odk1I7L00udgfJ156E3htvHMQ0x8XkgAxbQD4I+VAPE=; b=IcsrnNZeXgxjnacb7Z5GpQq7a0TtdOmkRMShlAWbCa3qTp7ra7d8bXqLWWk5MH0LYD ZwtYeWzyAxJGTzfd3yux3YjWYZbyMQgPoyR2Mcapv5pWOM620xF5RZXWKscxIRov3xWb 2UbxVKK9JPzVQhM3ctTgouWFaDdCwjvYYdNHKPms8mstZeDYvq2KPGIARani0gQGmylQ QbiBjvL2dj62hPZgStsOTKCDMEpbpVeRKguhcAwG7CUHtJyAMxZ0WNxbzaiD9tQsyeM4 vRFwcLhsy9Png9ZvvfGo0fA8a6qiHllIZ7tqOggX5oX57xerlV+P2IYk6Y2wpzz9eiHS 3kbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=odk1I7L00udgfJ156E3htvHMQ0x8XkgAxbQD4I+VAPE=; b=Qi+aRtUjLEg3B5dqqT2bfraTedPuQvwiymyGg9az3t56SxB7xzQDqJ3ZS/v0gUu+r0 WPjkHxefLG68pllnVNXJOdQJ2XxCvMpfifrOJi6f9lETDUMyvwlPkgz0967qw9TcF8uX 3s7q9eZlqZWDNc5xgO4YjDiISDmA844brXO+Hx2/7Z+/JJU0dpy/iKOmAZCTTK04iV4Z qn54a4i4xsJz905zrJygrHMi9PcS1DuuNPENjp/MnK/fS456nK+JuVMjFQj90xLnVGwH ppXJDp72O0gFYvW5iVGjonZAW8+AG3v5qiDZX5460jI0VIeM3w5d6u9NWK18u1e7ZtdX BOfA== X-Gm-Message-State: AA+aEWZ9Cp7z4BDW+W+eR9ZnzJzCYchcjFW15ixXb6kjJ0ZjiihQE+iU TjxJUswgFQwYekROTAGKy6ck8A== X-Google-Smtp-Source: AFSGD/WNcyQi0RZifPg1sP0BdTG5Ld2VenS5Toa7WygRWJi3msAxMY1zocknY6pBXD09ZxQ0YYColQ== X-Received: by 2002:a17:902:7c82:: with SMTP id y2mr14402441pll.33.1543814894616; Sun, 02 Dec 2018 21:28:14 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.28.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:14 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:43 +0530 Message-Id: <20181203052743.29036-5-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 4/4] RISC-V: Add S-mode timer implementation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When running in S-mode, we can use rdtime and rdtimeh instructions for reading timer ticks (just like Linux). The frequency of timer ticks is passed by prior booting stages in "timebase-frequency" DT property of the "/cpus" DT node. This patch provides a generic timer implementation for U-Boot running in S-mode. For U-Boot running in M-mode, specific timer drivers will have to be provided. Signed-off-by: Anup Patel --- arch/Kconfig | 1 - arch/riscv/Kconfig | 22 +++++++++++---- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/time.c | 60 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/lib/time.c diff --git a/arch/Kconfig b/arch/Kconfig index 9fdd2f7e66..a4fcb3522d 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -72,7 +72,6 @@ config RISCV imply BLK imply CLK imply MTD - imply TIMER imply CMD_DM config SANDBOX diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 732a357a99..20a060454b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,23 @@ config ARCH_RV64I endchoice +choice + prompt "Run Mode" + default RISCV_MMODE + +config RISCV_MMODE + bool "Machine" + select TIMER + help + Choose this option to build U-Boot for RISC-V M-Mode. + +config RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -55,11 +72,6 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y -config RISCV_SMODE - bool "Run in S-Mode" - help - Enable this option to build U-Boot for RISC-V S-Mode - config 32BIT bool diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b58db89752..98aa6d40e7 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -12,6 +12,7 @@ obj-y += cache.o obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o +obj-$(CONFIG_RISCV_SMODE) += time.o # For building EFI apps CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) diff --git a/arch/riscv/lib/time.c b/arch/riscv/lib/time.c new file mode 100644 index 0000000000..077e568ca6 --- /dev/null +++ b/arch/riscv/lib/time.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Anup Patel + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int tbclk; + +static void setup_tbclk(void) +{ + int cpus; + + if (!gd->fdt_blob || tbclk) + return; + + cpus = fdt_path_offset(gd->fdt_blob, "/cpus"); + if (cpus < 0) { + debug("%s: Missing /cpus node\n", __func__); + return; + } + + tbclk = fdtdec_get_int(gd->fdt_blob, cpus, + "timebase-frequency", 1000000); +} + +ulong notrace get_tbclk(void) +{ + setup_tbclk(); + + return tbclk; +} + +#ifdef CONFIG_64BIT +uint64_t notrace get_ticks(void) +{ + unsigned long n; + + __asm__ __volatile__ ( + "rdtime %0" + : "=r" (n)); + return n; +} +#else +uint64_t notrace get_ticks(void) +{ + uint32_t lo, hi, tmp; + __asm__ __volatile__ ( + "1:\n" + "rdtimeh %0\n" + "rdtime %1\n" + "rdtimeh %2\n" + "bne %0, %2, 1b" + : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); + return ((uint64_t)hi << 32) | lo; +} +#endif