From patchwork Thu Oct 12 20:52:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 825085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XkLqSbvk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCjk63gg4z9sBW for ; Fri, 13 Oct 2017 07:53:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755297AbdJLUwf (ORCPT ); Thu, 12 Oct 2017 16:52:35 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:56214 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755201AbdJLUwd (ORCPT ); Thu, 12 Oct 2017 16:52:33 -0400 Received: by mail-pf0-f182.google.com with SMTP id 17so6580023pfn.12 for ; Thu, 12 Oct 2017 13:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=omwDLTjhkoV879JbPb4WJXB4tSDpCkA/wkgiWn4TBd0=; b=XkLqSbvk0OrhVNWFcS0g+3K+fS1taCN0OAw9SceIbSEq4dN0fnZJRSf+mvLEaBxKTd BJL1jh6O1B7Ks3CKXfvO4tdiA4XFnJn1sV6Bf4BVe1SHpRC/N/N2+PY+GsqPsv+WHm9s k+Q19ITSsGjSWEUQ8wVcb6ZOLO3bPwdLXpENM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=omwDLTjhkoV879JbPb4WJXB4tSDpCkA/wkgiWn4TBd0=; b=L7/haOmip5xc/SqOlDD8U4FdETT2mUfA/cXhZdZJS2/nzFK9yUNRLe0Gs33x4qUS5k GMjjkGEh5efCow/R/xXr6cRZIsL6cmqCU/Lo5sN4I2zxSQiNy1AG3oMIMFuDVGp+gAnY ZzdFcQTmwFbfsSTFhIMe/9BGfnUDTCgDmNb+JmuoxMxIKV+jYzfSQlz3JUKHLLN0cCzA 3VySvMAoXbk/DrEopaiur+8b15UTTjdwJX59bO6ycZM1vfpkppsrmD2xI/40rty9PKxK iIQuskIUra7wOjKhTjXy1LdvnYJdV601o23YdrhmO2IJZgsVjea+v8lRueARiQRaknhL hJKA== X-Gm-Message-State: AMCzsaXOt111U30Z/Mp6uWDd9wV0d/jYeSIs9LM6YZ66P2ENz1g7ekjF 6BfW7tK9T1QgLbqpSsnDAtCeZw== X-Google-Smtp-Source: AOwi7QDHAqVlGfHfUuqBV45paYfhG2njEy6se9X6NZCLpYZaWtTpUKGlXB6T62+L4YKiqlY2AoUrZA== X-Received: by 10.84.142.101 with SMTP id 92mr1187667plw.254.1507841552582; Thu, 12 Oct 2017 13:52:32 -0700 (PDT) Received: from ban.mtv.corp.google.com ([172.22.113.17]) by smtp.gmail.com with ESMTPSA id h1sm25048704pgp.37.2017.10.12.13.52.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 13:52:32 -0700 (PDT) From: Brian Norris To: Bjorn Helgaas Cc: Rajat Jain , Rob Herring , Mark Rutland , Frank Rowand , Shawn Lin , Heiko Stuebner , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Brian Norris Subject: [PATCH 1/3] Documentation/devicetree: Add pcie-reset-suspend property Date: Thu, 12 Oct 2017 13:52:18 -0700 Message-Id: <20171012205220.130048-2-briannorris@chromium.org> X-Mailer: git-send-email 2.15.0.rc0.271.g36b669edcc-goog In-Reply-To: <20171012205220.130048-1-briannorris@chromium.org> References: <20171012205220.130048-1-briannorris@chromium.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The patch is self-descriptive. I've found that we may need platform-specific behavior for the PERST# signal in system suspend, depending on the type of PCIe endpoints are attached. Signed-off-by: Brian Norris --- Documentation/devicetree/bindings/pci/pci.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index c77981c5dd18..91339b6d0652 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -24,3 +24,14 @@ driver implementation may support the following properties: unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. +- pcie-reset-suspend: + If present this property defines whether the PCIe Reset signal (referred to + as PERST#) should be asserted when the system enters low-power suspend modes + (e.g., S3). Depending on the form factor, the associated PCIe + electromechanical specification may specify a particular behavior (e.g., + "PERST# is asserted in advance of the power being switched off in a + power-managed state like S3") or it may be less clear. The net result is + that some endpoints perform better (e.g., lower power consumption) with + PERST# asserted, and others prefer PERST# deasserted. The value must be '0' + or '1', where '0' means do not assert PERST# and '1' means assert PERST#. + When absent, behavior may be platform-specific. From patchwork Thu Oct 12 20:52:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 825087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="W92V2Bno"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCjkC1H09z9sBW for ; Fri, 13 Oct 2017 07:53:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755274AbdJLUxg (ORCPT ); Thu, 12 Oct 2017 16:53:36 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:47143 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755214AbdJLUwe (ORCPT ); Thu, 12 Oct 2017 16:52:34 -0400 Received: by mail-pf0-f181.google.com with SMTP id z11so6603996pfk.4 for ; Thu, 12 Oct 2017 13:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dnH5A9agN+AqHbnjhAY8RChCdBxo0Fr8J2aLGGv5zBU=; b=W92V2BnouHD7lgjA6ZVAfwMuhe9hyWL95tsd5GyJV3/wom2tXc+yZf03S46jbz7GeW MnG1iJhuHbMDh+CUl7OYVyoZcBhaUpkdfdXO5t57wN9LGDfS/UJBqzH+wkxQZWcVG5h2 IEONh+BBqXZNBXss8d6Sie2zuw+kxyDQim1P4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dnH5A9agN+AqHbnjhAY8RChCdBxo0Fr8J2aLGGv5zBU=; b=tWMoGH3jhAYB8ZtoxTCYi3LEzYa6v2miUyMLzylwFuKKHcM3aHjopfIB0+zlD8vkr+ sfyry1zqScWNWy1INJrLYCjzDxE9Qx67pAOfxOMLDeeW6Sbck4Rvp/2thwGhbk28VL6k j2WoCANli3IiUV0DpTiHOoqJXmU4QOQ3rgw4HTdLmuk1OfebjYpxhGrU9YyrsHQTlvfu xlRvnlxoMY9L7DHPLNAvlwqyDiT8NN8D/3p4/pMfbYWH/8dmgls8rOTSRsO/BYicfLnT 2LF12pWgPF6vqMiDBwYyeJTQdd9f3norxaBwbUVD777AOrqlYBXDfJ43CyjprV3FSdtb rCuA== X-Gm-Message-State: AMCzsaUS0S4JD5nhMT+Ki//2scImoEF1I8Y9YzkB7DMlcNIcsV0uP5GE deQJwVB6niowmLing5EcW8lgbA== X-Google-Smtp-Source: AOwi7QBlyTauwjzQ/g322s6jzdis7/MH92T885b/e1mC3PKBwYJgpircxpWYeiD2vRW/64gNiF3uog== X-Received: by 10.84.129.65 with SMTP id 59mr1181421plb.442.1507841553498; Thu, 12 Oct 2017 13:52:33 -0700 (PDT) Received: from ban.mtv.corp.google.com ([172.22.113.17]) by smtp.gmail.com with ESMTPSA id h1sm25048704pgp.37.2017.10.12.13.52.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 13:52:33 -0700 (PDT) From: Brian Norris To: Bjorn Helgaas Cc: Rajat Jain , Rob Herring , Mark Rutland , Frank Rowand , Shawn Lin , Heiko Stuebner , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Brian Norris Subject: [PATCH 2/3] of/pci: Add of_pci_get_pcie_reset_suspend() to parse pcie-reset-suspend Date: Thu, 12 Oct 2017 13:52:19 -0700 Message-Id: <20171012205220.130048-3-briannorris@chromium.org> X-Mailer: git-send-email 2.15.0.rc0.271.g36b669edcc-goog In-Reply-To: <20171012205220.130048-1-briannorris@chromium.org> References: <20171012205220.130048-1-briannorris@chromium.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This helper can be used by drivers to determine the expected PERST# behavior when in low-power system suspend (e.g., S3). I've found the expected behavior to vary across a few different endpoint implementations. Signed-off-by: Brian Norris --- drivers/of/of_pci.c | 25 +++++++++++++++++++++++++ include/linux/of_pci.h | 7 +++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c index e9ec931f5b9a..ab2586f86094 100644 --- a/drivers/of/of_pci.c +++ b/drivers/of/of_pci.c @@ -137,6 +137,31 @@ int of_pci_get_max_link_speed(struct device_node *node) } EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); +/** + * This function returns true if the PCIe controller should assert PCIe Reset + * (PERST#) when entering system suspend (e.g., S3). + * + * @node: device tree node with the reset property + * + * Returns 1 (meaning "assert reset") or 0 ("don't assert reset"), if the DT + * defined a valid behavior. Otherwise, returns a negative error code. + */ +int of_pci_get_pcie_reset_suspend(struct device_node *node) +{ + int ret; + u32 val; + + ret = of_property_read_u32(node, "pcie-reset-suspend", &val); + if (ret) + return ret; + + if (val > 1) + return -EINVAL; + + return val; +} +EXPORT_SYMBOL_GPL(of_pci_get_pcie_reset_suspend); + /** * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only * is present and valid diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 518c8d20647a..df453893080b 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -17,6 +17,7 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); int of_pci_get_max_link_speed(struct device_node *node); +int of_pci_get_pcie_reset_suspend(struct device_node *node); void of_pci_check_probe_only(void); int of_pci_map_rid(struct device_node *np, u32 rid, const char *map_name, const char *map_mask_name, @@ -69,6 +70,12 @@ of_pci_get_max_link_speed(struct device_node *node) return -EINVAL; } +static inline int +of_pci_get_pcie_reset_suspend(struct device_node *node) +{ + return -EINVAL; +} + static inline void of_pci_check_probe_only(void) { } #endif From patchwork Thu Oct 12 20:52:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 825088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="FSqgTwRI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCjkP67N8z9sBW for ; Fri, 13 Oct 2017 07:53:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752631AbdJLUxg (ORCPT ); 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Thu, 12 Oct 2017 13:52:34 -0700 (PDT) Received: from ban.mtv.corp.google.com ([172.22.113.17]) by smtp.gmail.com with ESMTPSA id h1sm25048704pgp.37.2017.10.12.13.52.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 13:52:33 -0700 (PDT) From: Brian Norris To: Bjorn Helgaas Cc: Rajat Jain , Rob Herring , Mark Rutland , Frank Rowand , Shawn Lin , Heiko Stuebner , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Brian Norris Subject: [PATCH 3/3] PCI: rockchip: Support configuring PERST# state via DT Date: Thu, 12 Oct 2017 13:52:20 -0700 Message-Id: <20171012205220.130048-4-briannorris@chromium.org> X-Mailer: git-send-email 2.15.0.rc0.271.g36b669edcc-goog In-Reply-To: <20171012205220.130048-1-briannorris@chromium.org> References: <20171012205220.130048-1-briannorris@chromium.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org I've found that different endpoints and board configurations have required different behavior from the PCIe Reset (PERST#) signal when in low-power system suspend (e.g., S3). Use the new of_pci helper to request this state and assert (active low) PERST# before suspending. Note that we reinitialize the link (including reconfiguring PERST#) at resume time. This requires that the board and system firmware supports driving this signal low when the system is suspended, since PERST# may be pulled up by the endpoint, and some GPIO banks are not active in S3. Signed-off-by: Brian Norris --- drivers/pci/host/pcie-rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 9051c6c8fea4..1ab58c1abb34 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -233,6 +233,7 @@ struct rockchip_pcie { struct regulator *vpcie1v8; /* 1.8V power supply */ struct regulator *vpcie0v9; /* 0.9V power supply */ struct gpio_desc *ep_gpio; + bool suspend_reset; u32 lanes; u8 lanes_map; u8 root_bus_nr; @@ -1155,6 +1156,9 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) dev_info(dev, "no vpcie0v9 regulator found\n"); } + /* Default not-asserted, to retain backward compatibility. */ + rockchip->suspend_reset = of_pci_get_pcie_reset_suspend(node) > 0; + return 0; } @@ -1463,6 +1467,9 @@ static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) return ret; } + if (rockchip->suspend_reset) + gpiod_set_value(rockchip->ep_gpio, 0); + rockchip_pcie_deinit_phys(rockchip); rockchip_pcie_disable_clocks(rockchip);