From patchwork Sun Nov 25 16:18:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 1002815 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="g7+PtZso"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432wGh0bwkz9s0n for ; Mon, 26 Nov 2018 03:19:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726562AbeKZDKb (ORCPT ); Sun, 25 Nov 2018 22:10:31 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:36728 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726226AbeKZDKa (ORCPT ); Sun, 25 Nov 2018 22:10:30 -0500 Received: by mail-pl1-f196.google.com with SMTP id g9so208648plo.3; Sun, 25 Nov 2018 08:19:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=dNaTAnr10zrYPVdsj0Xu4lcwWPKS7hR7CHzNPhUwwUg=; b=g7+PtZsoKpLBBoCYnVRnl/v5J7PlNw13Xu9ps86JqOKwgf/tWyZwmjG6f31J8Y02bc Z1rMv1r5b0DJTk9y9vo9hxCvxZfytTqbEfCtHyNQYKLybHBt48MAHw8TRfV7RYIgvOsq 3ay9eQzRY4Mlkf44ByHz2mEy3RVSIeHYO+tnh9CRUEOGm54i3JlpZsHieZualjvVOeHs QYD/6HZuOrdGlOUS+SrKt8Ap4zxG0hi28SIKPlP6wWo1MhfIHZSwl6EEe9V+7aUbiEst Uj9QqrhKfQ2ZiEBUjG0hL8nn2QUDx8DCd1gzMOoDaJpOCppzcYNmfE7sf6iF0C0Z0AJf PcMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=dNaTAnr10zrYPVdsj0Xu4lcwWPKS7hR7CHzNPhUwwUg=; b=uV1khKhl72PqQWWimlLtj2RV28wJnno2YNLUOlmIq5MqIWzgpGrgrkRv709M22RvJQ LLRur+9rXhv9H8zp6NUU/yhfeybg5+dZjX4facruWXVGcla3QfAltJ5blbSAhCc7vSu7 9tPUDgo+QeGJMB6kg39EUSJZcIcLaN6fyg/dE9tdh34dH/0XB5AAsfNafvLK8jHxRC+u Io+2myn24njwj9cRPd/BMPbpGu/vQnUE+oM+PEjiakUKnJRthCkWOkiBQM9NGIZo8e+X EbdAfzu/GNJX0PAaI2tWqn4ESwIKUMYlklhfjqZl9Fm45BWZ6gn1i7Xjc/x+9RDPHwd9 wZTg== X-Gm-Message-State: AA+aEWZnHEgWSWic7hVcOli8gUwUY5+hYgiIGDetL1MqKdHRxRnoLu/W iO4lx1WUc4G3Fo9kHJeCTkk= X-Google-Smtp-Source: AFSGD/X2HdyJokSI7P9S8vmbLUJwfsWeJhDWr09Qj7gJ3pjMJJmrn1Mj8iWxpSfNOKsX7GFBXb2XWg== X-Received: by 2002:a17:902:14e:: with SMTP id 72mr11379492plb.287.1543162746402; Sun, 25 Nov 2018 08:19:06 -0800 (PST) Received: from arx-s1 ([116.238.148.251]) by smtp.gmail.com with ESMTPSA id e23sm78420517pfh.68.2018.11.25.08.19.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Nov 2018 08:19:05 -0800 (PST) Date: Mon, 26 Nov 2018 00:18:59 +0800 From: Hao Zhang To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, mturquette@baylibre.com, sboyd@kernel.org, thierry.reding@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com, hao5781286@gmail.com Subject: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i. Message-ID: <20181125161859.GA5277@arx-s1> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds Allwinner sun8i pwm binding document. Signed-off-by: Hao Zhang Reviewed-by: Rob Herring --- .../devicetree/bindings/pwm/pwm-sun8i.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt new file mode 100644 index 0000000..7531d85 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt @@ -0,0 +1,24 @@ +Allwinner sun8i R40/V40/T3 SoC PWM controller + +Required properties: + - compatible: Should be one of: + - "allwinner,sun8i-r40-pwm" + - reg: Physical base address and length of the controller's registers + - interrupts: Should contain interrupt. + - clocks: From common clock binding, handle to the parent clock. + - clock-names: Must contain the clock names described just above. + - pwm-channels: PWM channels of the controller. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + +pwm: pwm@1c23400 { + compatible = "allwinner,sun8i-r40-pwm"; + reg = <0x01c23400 0x400>; + interrupts = ; + clocks = <&osc24M>, <&ccu CLK_APB1>; + clock-names = "mux-0", "mux-1"; + pwm-channels = <8>; + #pwm-cells = <3>; +}; From patchwork Sun Nov 25 16:19:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 1002818 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KfftdrzL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432wHV0pD2z9s1c for ; Mon, 26 Nov 2018 03:19:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726447AbeKZDLN (ORCPT ); Sun, 25 Nov 2018 22:11:13 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:37850 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726317AbeKZDLN (ORCPT ); Sun, 25 Nov 2018 22:11:13 -0500 Received: by mail-pf1-f195.google.com with SMTP id u3-v6so5376242pfm.4; Sun, 25 Nov 2018 08:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=D2ubccsUc+lruYN/6q8Va1yZPf6jxpt0taqqepYfPvk=; b=KfftdrzLWD4q9F2i7Hk2IX05icitsDSW6T3mBQwFXi4jcwWe2Cc3e4n4iNjSuY6W2b l2JXe9at78XnNL1ZaU3no2z3VGFd4BzVoVotiDRfJwSdU8rXevm6QnmcUc/aj2cVr0m0 psC6wT+a7kA6lv+68kYL1gaNQ1mAng7Apf6IycuHYJEcsP84KlFOiQSXhjOyV23OOxsy obweFVj1UxMRY94sJtSC5PferxwglbdLF3QM1Gjt3PMULJpyYtQp/JC8l3xuNxBZ/HdU JQ6bQj++JTIiweam4Tpe97MoBwjbH03MpfBQ7vX6cSR7chn7Li8+EDF7noT6TImKz+PC 9+0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=D2ubccsUc+lruYN/6q8Va1yZPf6jxpt0taqqepYfPvk=; b=HcFUjz48xxKSNxKldwX0dk+fPd7P4ZACp0JJS37oS/cLG2wIiCxQBFJMiCAKZcOv29 96+PdytSeARaqf2V81S5Vf4uOuiNKopdaadOriE2bUHok49c3hJ+34Ed61UoFZcW0cZa r1TVBZ411hUgc819AiyR2KjMvsk04Kei8kP8feQGOc8fNVGha05rCE7AiS5j53JqWDuc rKzFgzm7xvvCRJITqxjPX7pw7LjTZaqfP33ZDBKFCFv9gO5WjVtrjBPLSWyrDQSuhHrQ grm9FHTkCpO9lN1+ao7qj4ht2EJrmk1LpCgBLJwRdDPqL3CDbY8aqYbfdzbOtl65hLDh 24Kg== X-Gm-Message-State: AGRZ1gLPNFsV5Q7tR9LMB1rq/iEYSMaC8dPmBUSxl6DOLfe9ozmQVDvb qKEfGrEGgQmqkfay3sK5Y6U= X-Google-Smtp-Source: AJdET5dYwZffezPCRiD0XjloYZtx4Cz6x8UEPuro4rzPC/+ZokmYOOqugNQLfpe4mJe5pr8S7i5s9w== X-Received: by 2002:a62:6001:: with SMTP id u1-v6mr24506297pfb.130.1543162788802; Sun, 25 Nov 2018 08:19:48 -0800 (PST) Received: from arx-s1 ([116.238.148.251]) by smtp.gmail.com with ESMTPSA id g123-v6sm98190883pfc.155.2018.11.25.08.19.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Nov 2018 08:19:48 -0800 (PST) Date: Mon, 26 Nov 2018 00:19:41 +0800 From: Hao Zhang To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, mturquette@baylibre.com, sboyd@kernel.org, thierry.reding@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com, hao5781286@gmail.com Subject: [PATCH v3 2/6] ARM: dtsi: add pwm node for sun8i R40. Message-ID: <20181125161941.GA5305@arx-s1> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds pwm node for sun8i R40. Signed-off-by: Hao Zhang --- arch/arm/boot/dts/sun8i-r40.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 6f4c9ca..cc05b2c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -317,6 +317,7 @@ clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; + }; pio: pinctrl@1c20800 { @@ -373,6 +374,11 @@ bias-pull-up; }; + pwm_ch0_pin: pwm-ch0-pin { + pins = "PB2"; + function = "pwm"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -384,6 +390,17 @@ reg = <0x01c20c90 0x10>; }; + pwm: pwm@1c23400 { + compatible = "allwinner,sun8i-r40-pwm"; + reg = <0x01c23400 0x400>; + interrupts = ; + clocks = <&osc24M>, <&ccu CLK_APB1>; + clock-names = "mux-0", "mux-1"; + pwm-channels = <8>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; From patchwork Sun Nov 25 16:20:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 1002820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="n9Q7V5Ox"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432wJd4Hv9z9s0n for ; Mon, 26 Nov 2018 03:20:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726395AbeKZDMM (ORCPT ); Sun, 25 Nov 2018 22:12:12 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:45984 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726098AbeKZDMM (ORCPT ); Sun, 25 Nov 2018 22:12:12 -0500 Received: by mail-pl1-f196.google.com with SMTP id a14so12658018plm.12; Sun, 25 Nov 2018 08:20:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=oTvQBmsSo+R04V9KH1Sk1+fvcPd9GR80N+lSsbfwtyk=; b=n9Q7V5Ox3Q2J0CmyE35bnOEJqHNc1uau7R+lVBNJdPuNztF7+GOqPXRBQTmvzv/f9e lePL4IpoBLirt4Vk6fIsi0beX3to/IeBlTY9oaceRR7zfr7O7O9nD9E9wM4OFo15XSp9 2kWXp2auG0u/JIid67hgqpNDxLrpo3pgGCTBKRnlK54JueLdrygWdCJHGUcC1LxTMFyY WUyRXX92Z2eRsz6D1/lBzm2clio2tEG3+hAE3fGilyB98qNdelkMdJeN9WdN3lTYgcbk 2M+oKpqRfc4819l3xZYJCpiiMFMYbhAqEyOoXkuZKr6rNjlx4N/i52v5T2iPj0oKnvsn e+ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=oTvQBmsSo+R04V9KH1Sk1+fvcPd9GR80N+lSsbfwtyk=; b=H5Qyd6WqFnff8cHpPj4xjJ+caQ2pQrXIDugx9Ha2oMGhKYdablLNKd88TqABXytP0p MCbGi3AmtToIM9HjxaOquZo4hpXzTs9Lw4CJhZhOrgZs7BBwaTpPRMmO2djjCQil0MlM vu4pwQTRHIQZ+X76UFrFQeORJfOjDDnphgUUO9EBYwzvz7ffeXH7puSSFGv7/s4s40Hk iiswsk45scUEi70qJbRbf2srr9xOpNrrV5Uv3iI3AK4AIQJCJVjk6s2i9KNnjtVoNTpt 3efs7deHevTTg7oY9R1D9vslip00JR962Gt/jCEpOQy6olFoZPUCYSEmSV2BQ1fiuVkF 6/gQ== X-Gm-Message-State: AA+aEWZoPraYznD1TlfhMzjWQ7qUeNxxmulJGQTGcSrL6a9MKkfgGAfI JcBr/FoLXeGGVdPcH4nLDxA= X-Google-Smtp-Source: AFSGD/WmtbVxHcMPsLlItabkNJtYW1DfGfo8Pp3pGEL7ulzJVu0SQUUHENVTil/dY9oXbNhDpi36uw== X-Received: by 2002:a17:902:b787:: with SMTP id e7mr13014732pls.246.1543162847996; Sun, 25 Nov 2018 08:20:47 -0800 (PST) Received: from arx-s1 ([116.238.148.251]) by smtp.gmail.com with ESMTPSA id p15-v6sm101187605pfj.72.2018.11.25.08.20.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Nov 2018 08:20:47 -0800 (PST) Date: Mon, 26 Nov 2018 00:20:40 +0800 From: Hao Zhang To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, mturquette@baylibre.com, sboyd@kernel.org, thierry.reding@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com, hao5781286@gmail.com Subject: [PATCH v3 3/6] ARM: dts: add PWM for Bananapi M2 Ultrar board. Message-ID: <20181125162040.GA5333@arx-s1> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds pwm status for Bananapi M2 Ultrar board and the status also used as LCD-PWM status. Signed-off-by: Hao Zhang --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 438b7b4..d785c9b 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -272,6 +272,12 @@ status = "okay"; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ch0_pin>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From patchwork Sun Nov 25 16:21:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 1002823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lqTSXYBD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432wKR5HLFz9s1c for ; Mon, 26 Nov 2018 03:21:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726429AbeKZDMu (ORCPT ); Sun, 25 Nov 2018 22:12:50 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:38626 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726098AbeKZDMu (ORCPT ); Sun, 25 Nov 2018 22:12:50 -0500 Received: by mail-pg1-f196.google.com with SMTP id g189so5010125pgc.5; Sun, 25 Nov 2018 08:21:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=Omlkkwv0msPmZtThXMkJDsvh3cmK0KZre5FygCF5oVA=; b=lqTSXYBDM3nVfEuliT1hheT5MGrh4hTc1uK718BM1aWQpIeONRz9c+NQluhCE5Y3kN upjcf3t6u/mmkSuYQCbPZQFaHWEBTybRTdsbB6hjehIkZp8YONBeboUkuqjHvoisQGB9 dz5hl2J6KXdjqz39Bn8ib5Jd9OHzdJiCuYTb+Z9ULYUisL/WjhS4827AqgBQ6efD00IX q+REItCL1IOGm1KCMPd/Rkm8C0uHiVuP0qAjAqahR9n6q8qavaFy7QYbnbtIKewhFBXM MBkwvSseWExhYsDeUtFGd/oDpy9AXumnsS8Tzp0fidFY7QqFZ7YCqMS4Yi9lgQQLSnhk ivmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=Omlkkwv0msPmZtThXMkJDsvh3cmK0KZre5FygCF5oVA=; b=c+Hf9ER+GQjjAl9e+9J46HSemFpHKpLe4TUyoaqxnIVSlTVz1regfQiNDB0x/m4z8a QjlLGHGgN6GiYhdHleUXaAWGd16SEXvOPQpkaY3pYPZ+g8eXOlFEr4MNupQxpv/kHRmD oFqtPrirQ/ir/3HRQY2vFkt3+6N4SQNmZhBY5iSvCGGILe+9Q2LSbLmMbg+K3ZDyy7pj vd54XIdgv2SLmqNIRXJM3ePtUsBCHjIufhnOGHGzz6omminfCsqsKwq6J3aL6Vb22Bzj UM+BzE9A8dQH8nqh+VAsDuGxkG6rLUu8JHTc2a6XFBI6CbvpTC/U5kPXbKmjq6gFXjT7 vptQ== X-Gm-Message-State: AGRZ1gIRQejPYrATkP8ZDe9psJ0jORLgDKAWJ+E1qCPRul2kH0FUnp3w LtXZwzA41XQSrVt1QYBCbOA= X-Google-Smtp-Source: AJdET5ciYiampuBjjEcVYaTQGagu+wjsA6VHFu5dMyVjTlj1Xtn2vreUdqcqlusZNdRHJNK/uuSudQ== X-Received: by 2002:a63:7d06:: with SMTP id y6mr21319483pgc.171.1543162885225; Sun, 25 Nov 2018 08:21:25 -0800 (PST) Received: from arx-s1 ([116.238.148.251]) by smtp.gmail.com with ESMTPSA id o189sm44994655pfg.117.2018.11.25.08.21.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Nov 2018 08:21:24 -0800 (PST) Date: Mon, 26 Nov 2018 00:21:18 +0800 From: Hao Zhang To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, mturquette@baylibre.com, sboyd@kernel.org, thierry.reding@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com, hao5781286@gmail.com Subject: [PATCH v3 4/6] DEV: CLK: add function to check the using clock name of driver. Message-ID: <20181125162118.GA5358@arx-s1> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org In some situation we want to check clock whether is we want and after the driver been probed use to change different clock source. Signed-off-by: Hao Zhang --- drivers/clk/clk.c | 6 ++++++ include/linux/clk-provider.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index d31055a..3d2c2cd 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3466,6 +3466,12 @@ static int devm_clk_hw_match(struct device *dev, void *res, void *data) return hw == data; } +bool devm_clk_name_match(struct clk *clk, const char *string) +{ + return match_string(&clk->con_id, 1, string) == 0; +} +EXPORT_SYMBOL_GPL(devm_clk_name_match); + /** * devm_clk_unregister - resource managed clk_unregister() * @clk: clock to unregister diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 08b1aa7..5cd2eed 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -764,6 +764,7 @@ struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); +bool devm_clk_name_match(struct clk *clk, const char *string); void clk_unregister(struct clk *clk); void devm_clk_unregister(struct device *dev, struct clk *clk); From patchwork Sun Nov 25 16:22:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 1002824 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WoDya4d0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432wLv3MRfz9s0n for ; Mon, 26 Nov 2018 03:22:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726735AbeKZDOG (ORCPT ); Sun, 25 Nov 2018 22:14:06 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:35443 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726395AbeKZDOG (ORCPT ); Sun, 25 Nov 2018 22:14:06 -0500 Received: by mail-pl1-f195.google.com with SMTP id p8so2396958plo.2; Sun, 25 Nov 2018 08:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=oRZLwlngBTRlgTkLLHYb5YuavMVSU0mKsDQHiQNPGqw=; b=WoDya4d0Ue/2VK8tsjlG5qxNEH6E1C5gKxxqNiQgkXdU1cCFgdsBntdmt7nKOrJBQp TIHmt1VvsDbaqd4B6tKvFEBYLRLpTV38Fv8u6cQgUG7eEll03jp8eWZ9FiKBBbLce9UU y38ECjyYYf+CaxBhGuUQGv3SxyXFkvWxu6oX5d1eppWCXy5X5OjpYZDsphvzb+fgW7+d ec9PFSsIT6nGJcAF05DgSV2JXfJCctcRnEKnuyxn56QyuahMocAK00pgvp01SNT2laB2 9mbFFJTLZEY5epvdajUWHlu7AdJ0YJKyGh6b97nLSDMcy4RGvJ4Oj5Nbf/0v9LhtlARi 3oOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=oRZLwlngBTRlgTkLLHYb5YuavMVSU0mKsDQHiQNPGqw=; b=KHAVHK6E1HZ9hKsmpoAOWYST37wQfWVT6F9sMWzIiROCgJg+NB2Jgd1NiLkdnwllp6 /CyvY79sdZUulxziSK8okco61MevYPaqUAU3ucFgABPRwYBuVW9w074UZQRS6vc6oZ5K e4KG8Pt7nmlhXMVsjrzg8bTI+JH1yPHzbVLFpV6fBFRcTNqfbooMxllapeATSf09Ni+K 1psm4/xl3NQn81hUwISbSe7iM2YAvaCUwBHNwgis4blmm3wfvo1JXcoQwJiAf8REUnOE OdSNewDfGKLprj4Ot1QTuYhJ+u+kOBceehGdOzXIfMoVHa0oF7txofuExJFYdL53U7ac AVrA== X-Gm-Message-State: AA+aEWaYMNigRE9TtLaknx0BS0GhRqJ56j44LTtPsUBmi2RXtHzQIjSN 43Me4yDRa0aRlG5LvSQTlUE= X-Google-Smtp-Source: AFSGD/XG/ppJrvo3uySEydwXN3OS+lrhza3wBuf9w8NDGdNIdZo1lXT/fNXfaLUAJeFZfDgvtBR8gg== X-Received: by 2002:a17:902:f20d:: with SMTP id gn13mr23129317plb.11.1543162961002; Sun, 25 Nov 2018 08:22:41 -0800 (PST) Received: from arx-s1 ([116.238.148.251]) by smtp.gmail.com with ESMTPSA id t13sm123088987pgr.42.2018.11.25.08.22.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Nov 2018 08:22:40 -0800 (PST) Date: Mon, 26 Nov 2018 00:22:03 +0800 From: Hao Zhang To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, mturquette@baylibre.com, sboyd@kernel.org, thierry.reding@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com, hao5781286@gmail.com Subject: [PATCH v3 5/6] DEV: CLK: sunxi ccu: export clk_apb1 for sun8i-r40 soc pwm. Message-ID: <20181125162203.GA5392@arx-s1> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The clock source for sun8i R40 is from apb1, so export it for dt parses. Signed-off-by: Hao Zhang Reviewed-by: Rob Herring --- drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 4 +++- include/dt-bindings/clock/sun8i-r40-ccu.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h index db2a124..181ab26 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h @@ -51,7 +51,9 @@ #define CLK_AXI 25 #define CLK_AHB1 26 -#define CLK_APB1 27 + +/* The APB1 clock is exported */ + #define CLK_APB2 28 /* All the bus gates are exported */ diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h index f9e15a2..a2b8f06 100644 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ b/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -49,6 +49,8 @@ #define CLK_CPU 24 +#define CLK_APB1 27 + #define CLK_BUS_MIPI_DSI 29 #define CLK_BUS_CE 30 #define CLK_BUS_DMA 31 From patchwork Sun Nov 25 16:23:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 1002827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="s9TzMsvz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432wMh0j8Yz9s0n for ; Mon, 26 Nov 2018 03:23:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726356AbeKZDOw (ORCPT ); Sun, 25 Nov 2018 22:14:52 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:45500 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbeKZDOv (ORCPT ); Sun, 25 Nov 2018 22:14:51 -0500 Received: by mail-pg1-f194.google.com with SMTP id y4so4994396pgc.12; Sun, 25 Nov 2018 08:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=l5cyqGj3FK1HXmO4T0ciMbIqltxYRJ3GO4Qb3G/D5NA=; b=s9TzMsvzKX4wXUJ9KjmBxi2+wonhTcbTfdtkJ3x8Piuk2hZrDR/vjJXWZzZRQgwSYM fjW3fCTCIO3BnAbb7zX8PCkmEKG3RbqPHYotgYJUfjiLy0jnwFvfraji0oSbfXU+Jprw +sSjgqkwukFh1LeUA1nF07BU0D04nnWFOnR5daCUl5nrip4S5VS1Tp2bTiJNkvSgLKaZ fDEjAK4s+sOlevOV/lr2dtupHnXnWekZ7HN5AwbHoEyCkvXNNHA3A43jI9cn4ImY4kWf 9zIu77+dOQAK8xuBg7H8r7INhZ8LmziWfMzmJsInWYdoR3WhbQ0zMrK8Y92sFoybrZuI KvvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=l5cyqGj3FK1HXmO4T0ciMbIqltxYRJ3GO4Qb3G/D5NA=; b=YV+iUQc0oZS4i8e4pqXX3LqyjT+3lRGgUTWDpwYMfTIVa36ojQKH7/6AhNZH9uAq7a hhQ0PoSLhyxf2t4qC9vqOvmwiyxusZl2QVES163g8VoQEoSPOReKeYHKiXAylb9Z/o75 D/J7MhuDeW1tuFxEAoBl2M6++iDbR4dzvsgwZvxSVZRHypT8lzEXXaGEcY/Q8Hdtgo1U SdtBxofqXx4bwFtzCQkS8vYS8bQxG5SHHdH7YuCNsQfTohtSoZcDLN/lgkOUxoTOKcO9 f8sBBQ8TvK9FZecKbmusEBA217eHFtRLE8ROSIvlRFxuOo5JvxxHWtAEk+scNu46V1Hk Ilig== X-Gm-Message-State: AA+aEWZnScNbfO0JvO7i7qsStPvU0J1/I/65tdqtcnO1ZeEHRdoecX93 QpOook9e1md5nUlStWQOQRw= X-Google-Smtp-Source: AFSGD/UrQbQzdy6FVMawuvQfX7Ymm6IW6ELYdTt7I4USIidy36aUP84eZFHyKXIENd6SiWkmI4hcHA== X-Received: by 2002:a63:8441:: with SMTP id k62mr21287276pgd.392.1543163006087; Sun, 25 Nov 2018 08:23:26 -0800 (PST) Received: from arx-s1 ([116.238.148.251]) by smtp.gmail.com with ESMTPSA id y12sm14444309pfk.70.2018.11.25.08.23.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Nov 2018 08:23:25 -0800 (PST) Date: Mon, 26 Nov 2018 00:23:19 +0800 From: Hao Zhang To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, mturquette@baylibre.com, sboyd@kernel.org, thierry.reding@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com, hao5781286@gmail.com Subject: [PATCH v3 6/6] ARM: PWM: add allwinner sun8i R40/T3/V40 PWM support. Message-ID: <20181125162319.GA5422@arx-s1> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The sun8i R40/T3/V40 PWM has 8 PWM channals and divides to 4 PWM pairs, each PWM pair built-in 1 clock module, 2 timer logic module and 1 programmable dead-time generator, it also support waveform capture. It has 2 clock sources OSC24M and APB1, it is different with the sun4i-pwm driver, Therefore add a new driver for it. Signed-off-by: Hao Zhang --- drivers/pwm/Kconfig | 12 +- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun8i.c | 418 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 drivers/pwm/pwm-sun8i.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 504d252..6105ac8 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -426,7 +426,7 @@ config PWM_STMPE expanders. config PWM_SUN4I - tristate "Allwinner PWM support" + tristate "Allwinner SUN4I PWM support" depends on ARCH_SUNXI || COMPILE_TEST depends on HAS_IOMEM && COMMON_CLK help @@ -435,6 +435,16 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. +config PWM_SUN8I + tristate "Allwinner SUN8I (R40/V40/T3) PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on HAS_IOMEM && COMMON_CLK + help + Generic PWM framework driver for Allwinner R40/V40/T3 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun8i. + config PWM_TEGRA tristate "NVIDIA Tegra PWM support" depends on ARCH_TEGRA diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9c676a0..32c8d2d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o +obj-$(CONFIG_PWM_SUN8I) += pwm-sun8i.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o diff --git a/drivers/pwm/pwm-sun8i.c b/drivers/pwm/pwm-sun8i.c new file mode 100644 index 0000000..d8597e4 --- /dev/null +++ b/drivers/pwm/pwm-sun8i.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hao Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_IRQ_ENABLE_REG 0x0000 +#define PCIE(ch) BIT(ch) + +#define PWM_IRQ_STATUS_REG 0x0004 +#define PIS(ch) BIT(ch) + +#define CAPTURE_IRQ_ENABLE_REG 0x0010 +#define CRIE(ch) BIT((ch) * 2) +#define CFIE(ch) BIT((ch) * 2 + 1) + +#define CAPTURE_IRQ_STATUS_REG 0x0014 +#define CRIS(ch) BIT((ch) * 2) +#define CFIS(ch) BIT((ch) * 2 + 1) + +#define CLK_CFG_REG(ch) (0x0020 + ((ch) >> 1) * 4) +#define CLK_SRC_SEL GENMASK(8, 7) +#define CLK_SRC_BYPASS_SEC BIT(6) +#define CLK_SRC_BYPASS_FIR BIT(5) +#define CLK_GATING BIT(4) +#define CLK_DIV_M GENMASK(3, 0) + +#define PWM_DZ_CTR_REG(ch) (0x0030 + ((ch) >> 1) * 4) +#define PWM_DZ_INTV GENMASK(15, 8) +#define PWM_DZ_EN BIT(0) + +#define PWM_ENABLE_REG 0x0040 +#define PWM_EN(ch) BIT(ch) + +#define CAPTURE_ENABLE_REG 0x0044 +#define CAP_EN(ch) BIT(ch) + +#define PWM_CTR_REG(ch) (0x0060 + (ch) * 0x20) +#define PWM_PERIOD_RDY BIT(11) +#define PWM_PUL_START BIT(10) +#define PWM_MODE BIT(9) +#define PWM_ACT_STA BIT(8) +#define PWM_PRESCAL_K GENMASK(7, 0) + +#define PWM_PERIOD_REG(ch) (0x0064 + (ch) * 0x20) +#define PWM_ENTIRE_CYCLE GENMASK(31, 16) +#define PWM_ACT_CYCLE GENMASK(15, 0) + +#define PWM_CNT_REG(ch) (0x0068 + (ch) * 0x20) +#define PWM_CNT_VAL GENMASK(15, 0) + +#define CAPTURE_CTR_REG(ch) (0x006c + (ch) * 0x20) +#define CAPTURE_CRLF BIT(2) +#define CAPTURE_CFLF BIT(1) +#define CAPINV BIT(0) + +#define CAPTURE_RISE_REG(ch) (0x0070 + (ch) * 0x20) +#define CAPTURE_CRLR GENMASK(15, 0) + +#define CAPTURE_FALL_REG(ch) (0x0074 + (ch) * 0x20) +#define CAPTURE_CFLR GENMASK(15, 0) + +struct sun8i_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + const struct sun8i_pwm_data *data; + struct regmap *regmap; +}; + +static struct sun8i_pwm_chip *to_sun8i_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct sun8i_pwm_chip, chip); +} + +static u32 sun8i_pwm_read(struct sun8i_pwm_chip *sun8i_pwm, + unsigned long offset) +{ + u32 val; + + regmap_read(sun8i_pwm->regmap, offset, &val); + return val; +} + +static void sun8i_pwm_set_bit(struct sun8i_pwm_chip *sun8i_pwm, + unsigned long reg, u32 bit) +{ + regmap_update_bits(sun8i_pwm->regmap, reg, bit, bit); +} + +static void sun8i_pwm_clear_bit(struct sun8i_pwm_chip *sun8i_pwm, + unsigned long reg, u32 bit) +{ + regmap_update_bits(sun8i_pwm->regmap, reg, bit, 0); +} + +static void sun8i_pwm_set_value(struct sun8i_pwm_chip *sun8i_pwm, + unsigned long reg, u32 mask, u32 val) +{ + regmap_update_bits(sun8i_pwm->regmap, reg, mask, val); +} + +static void sun8i_pwm_set_polarity(struct sun8i_pwm_chip *chip, u32 ch, + enum pwm_polarity polarity) +{ + if (polarity == PWM_POLARITY_NORMAL) + sun8i_pwm_set_bit(chip, PWM_CTR_REG(ch), PWM_ACT_STA); + else + sun8i_pwm_clear_bit(chip, PWM_CTR_REG(ch), PWM_ACT_STA); +} + +static int sun8i_pwm_config(struct sun8i_pwm_chip *sun8i_pwm, u8 ch, + struct pwm_state *state) +{ + u64 clk_rate, clk_div, val; + u16 prescaler = 0; + u16 div_id = 0; + struct clk *clk; + bool is_clk; + int ret; + + clk_rate = clk_get_rate(sun8i_pwm->clk); + + /* check period and select clock source */ + val = state->period * clk_rate; + do_div(val, NSEC_PER_SEC); + is_clk = devm_clk_name_match(sun8i_pwm->clk, "mux-0"); + if (val <= 1 && is_clk) { + clk = devm_clk_get(sun8i_pwm->chip.dev, "mux-1"); + if (IS_ERR(clk)) { + dev_err(sun8i_pwm->chip.dev, + "Period expects a larger value\n"); + return -EINVAL; + } + + clk_rate = clk_get_rate(clk); + val = state->period * clk_rate; + do_div(val, NSEC_PER_SEC); + if (val <= 1) { + dev_err(sun8i_pwm->chip.dev, + "Period expects a larger value\n"); + return -EINVAL; + } + + /* change clock source to "mux-1" */ + clk_disable_unprepare(sun8i_pwm->clk); + devm_clk_put(sun8i_pwm->chip.dev, sun8i_pwm->clk); + sun8i_pwm->clk = clk; + + ret = clk_prepare_enable(sun8i_pwm->clk); + if (ret) { + dev_err(sun8i_pwm->chip.dev, + "Failed to enable PWM clock\n"); + return ret; + } + + } else { + dev_err(sun8i_pwm->chip.dev, + "Period expects a larger value\n"); + return -EINVAL; + } + + is_clk = devm_clk_name_match(sun8i_pwm->clk, "mux-0"); + if (is_clk) + sun8i_pwm_set_value(sun8i_pwm, CLK_CFG_REG(ch), + CLK_SRC_SEL, 0 << 7); + else + sun8i_pwm_set_value(sun8i_pwm, CLK_CFG_REG(ch), + CLK_SRC_SEL, 1 << 7); + + dev_info(sun8i_pwm->chip.dev, "clock source freq:%lldHz\n", clk_rate); + + /* calculate and set prescaler, div table, PWM entire cycle */ + clk_div = val; + while (clk_div > 65535) { + prescaler++; + clk_div = val; + do_div(clk_div, 1U << div_id); + do_div(clk_div, prescaler + 1); + + if (prescaler == 255) { + prescaler = 0; + div_id++; + if (div_id == 9) { + dev_err(sun8i_pwm->chip.dev, + "unsupport period value\n"); + return -EINVAL; + } + } + } + + sun8i_pwm_set_value(sun8i_pwm, PWM_PERIOD_REG(ch), + PWM_ENTIRE_CYCLE, clk_div << 16); + sun8i_pwm_set_value(sun8i_pwm, PWM_CTR_REG(ch), + PWM_PRESCAL_K, prescaler << 0); + sun8i_pwm_set_value(sun8i_pwm, CLK_CFG_REG(ch), + CLK_DIV_M, div_id << 0); + + /* set duty cycle */ + val = state->period; + do_div(val, clk_div); + clk_div = state->duty_cycle; + do_div(clk_div, val); + if (clk_div > 65535) + clk_div = 65535; + + sun8i_pwm_set_value(sun8i_pwm, PWM_PERIOD_REG(ch), + PWM_ACT_CYCLE, clk_div << 0); + + return 0; +} + +static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + int ret; + struct sun8i_pwm_chip *sun8i_pwm = to_sun8i_pwm_chip(chip); + struct pwm_state cstate; + + pwm_get_state(pwm, &cstate); + if (!cstate.enabled) { + ret = clk_prepare_enable(sun8i_pwm->clk); + if (ret) { + dev_err(chip->dev, "Failed to enable PWM clock\n"); + return ret; + } + } + + if ((cstate.period != state->period) || + (cstate.duty_cycle != state->duty_cycle)) { + ret = sun8i_pwm_config(sun8i_pwm, pwm->hwpwm, state); + if (ret) { + dev_err(chip->dev, "Failed to config PWM\n"); + return ret; + } + } + + if (state->polarity != cstate.polarity) + sun8i_pwm_set_polarity(sun8i_pwm, pwm->hwpwm, state->polarity); + + if (state->enabled) { + sun8i_pwm_set_bit(sun8i_pwm, + CLK_CFG_REG(pwm->hwpwm), CLK_GATING); + + sun8i_pwm_set_bit(sun8i_pwm, + PWM_ENABLE_REG, PWM_EN(pwm->hwpwm)); + } else { + sun8i_pwm_clear_bit(sun8i_pwm, + CLK_CFG_REG(pwm->hwpwm), CLK_GATING); + + sun8i_pwm_clear_bit(sun8i_pwm, + PWM_ENABLE_REG, PWM_EN(pwm->hwpwm)); + } + + return 0; +} + +static void sun8i_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sun8i_pwm_chip *sun8i_pwm = to_sun8i_pwm_chip(chip); + u64 clk_rate, tmp; + u32 val; + u16 clk_div, act_cycle; + u8 prescal, div_id; + u8 chn = pwm->hwpwm; + + clk_rate = clk_get_rate(sun8i_pwm->clk); + + val = sun8i_pwm_read(sun8i_pwm, PWM_CTR_REG(chn)); + if (PWM_ACT_STA & val) + state->polarity = PWM_POLARITY_NORMAL; + else + state->polarity = PWM_POLARITY_INVERSED; + + prescal = PWM_PRESCAL_K & val; + + val = sun8i_pwm_read(sun8i_pwm, PWM_ENABLE_REG); + if (PWM_EN(chn) & val) + state->enabled = true; + else + state->enabled = false; + + val = sun8i_pwm_read(sun8i_pwm, PWM_PERIOD_REG(chn)); + act_cycle = PWM_ACT_CYCLE & val; + clk_div = val >> 16; + + val = sun8i_pwm_read(sun8i_pwm, CLK_CFG_REG(chn)); + div_id = CLK_DIV_M & val; + + tmp = act_cycle * prescal * (1U << div_id) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); + tmp = clk_div * prescal * (1U << div_id) * NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); +} + +static const struct regmap_config sun8i_pwm_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = CAPTURE_FALL_REG(7), +}; + +static const struct pwm_ops sun8i_pwm_ops = { + .apply = sun8i_pwm_apply, + .get_state = sun8i_pwm_get_state, + .owner = THIS_MODULE, +}; + +static const struct of_device_id sun8i_pwm_dt_ids[] = { + { + .compatible = "allwinner,sun8i-r40-pwm", + .data = NULL, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids); + +static int sun8i_pwm_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct sun8i_pwm_chip *pwm; + struct resource *res; + int ret; + const struct of_device_id *match; + + match = of_match_device(sun8i_pwm_dt_ids, &pdev->dev); + if (!match) { + dev_err(&pdev->dev, "Error: No device match found\n"); + return -ENODEV; + } + + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pwm->base)) + return PTR_ERR(pwm->base); + + pwm->regmap = devm_regmap_init_mmio(&pdev->dev, pwm->base, + &sun8i_pwm_regmap_config); + if (IS_ERR(pwm->regmap)) { + dev_err(&pdev->dev, "Failed to create regmap\n"); + return PTR_ERR(pwm->regmap); + } + + /* we use mux-0 as default clock source */ + pwm->clk = devm_clk_get(&pdev->dev, "mux-0"); + if (IS_ERR(pwm->clk)) { + pwm->clk = devm_clk_get(&pdev->dev, "mux-1"); + if (IS_ERR(pwm->clk)) { + dev_err(&pdev->dev, "Failed to get PWM clock\n"); + return PTR_ERR(pwm->clk); + } + } + + ret = of_property_read_u32(np, "pwm-channels", &pwm->chip.npwm); + if (ret && !pwm->chip.npwm) { + dev_err(&pdev->dev, "Can't get pwm-channels\n"); + return ret; + } + + dev_info(&pdev->dev, "pwm-channels:%d\n", pwm->chip.npwm); + pwm->data = match->data; + pwm->chip.dev = &pdev->dev; + pwm->chip.ops = &sun8i_pwm_ops; + pwm->chip.base = -1; + pwm->chip.of_xlate = of_pwm_xlate_with_flags; + pwm->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add(&pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to add PWM chip: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int sun8i_pwm_remove(struct platform_device *pdev) +{ + struct sun8i_pwm_chip *pwm = platform_get_drvdata(pdev); + + clk_disable_unprepare(pwm->clk); + return pwmchip_remove(&pwm->chip); +} + +static struct platform_driver sun8i_pwm_driver = { + .driver = { + .name = "sun8i-pwm", + .of_match_table = sun8i_pwm_dt_ids, + }, + .probe = sun8i_pwm_probe, + .remove = sun8i_pwm_remove, +}; +module_platform_driver(sun8i_pwm_driver); + +MODULE_ALIAS("platform: sun8i-pwm"); +MODULE_AUTHOR("Hao Zhang "); +MODULE_DESCRIPTION("Allwinner sun8i PWM driver"); +MODULE_LICENSE("GPL v2");