From patchwork Thu Oct 12 07:27:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 824711 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZO4mDXMx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yCMrT1nC1z9t2m for ; Thu, 12 Oct 2017 18:27:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F268FC21EEE; Thu, 12 Oct 2017 07:27:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 76360C21D99; Thu, 12 Oct 2017 07:27:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2BD9FC21D82; Thu, 12 Oct 2017 07:27:40 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 86886C21D99 for ; Thu, 12 Oct 2017 07:27:39 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id z80so4970398pff.4 for ; Thu, 12 Oct 2017 00:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=Jt1cimZ9cWXJIq5RcrLuuq8LVPS3XznC0eGVWKW3Yg4=; b=ZO4mDXMxD9boeLpLh2Oilk3lKknO7F963i3MPh5l8dE8HPCEtRvsTyBTJCwVLwF2kN MK+KBHYrIYx2Et2Jf8AsR1UbiKzTYoNKR5E7pNhVgB7WEhLN7kJIcRNbUG+FIOUyrfIu 7d7/HCmqcTFlYyCANVm4u26JIgfk+ihUeJR6N3YtkOXRb0mlyHUpsW9mYwUK8enL0A9T 1tlxubXWHsmN3eCk3F+cUfzKcCM8L1l4odhlsS5auhpx2Zv5EybrRAM0njOc+UGskcbI g71xeOcXxWnAUB7vVry9UVge3Y1vzkd3VXahPzWmiGQZiLgZM4iju/PDmFGUi7OMzeHQ 5ibA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=Jt1cimZ9cWXJIq5RcrLuuq8LVPS3XznC0eGVWKW3Yg4=; b=bUiFZ2FwiO+0Sz0Xj+qyIUYdNIpgjLIhKZwfp5QwtOdwclhGb5DVYWS3p5QBrXndY7 LfR2QNhheG/NRxhmQCD8PMt9zwcsMeQ2WpLzQhLmES8gzVsIN7mzEjUmJLkO5WTI8cMe 27KHOUTXuIQvM5Y4YdMjZnaO3G/D9Az/sn80Qr0lH4Vry0GRd9BliT3SZkfXhZwoQCo4 SfzFs0dHhqQwy04Cg1wEBImKM9jIqFQ6f62gZOiYcGuyktQABWnYecYnVsBFWno48P0d eRsQoppKbrsaZI6Pct7gKYI2tRtmhvAm9pHV5U9J/b6vEoNIMd7hyqKkA452wBpZpSQi X5kw== X-Gm-Message-State: AMCzsaXhEsVbpIFGcxdEfHCCJAFsf6QHc3uenvw2oTwiTfl/6u7cwel0 z2/gh88kSqQPfH3sFgBFW+N7RA== X-Google-Smtp-Source: AOwi7QCAjffvTD28HHJAto5zmh2RW/1Bp58jKuvfpLAU6xa3q0OuGcvjTKAg2gyMXZGUa4Nnd41Mlw== X-Received: by 10.159.255.12 with SMTP id bi12mr1372935plb.61.1507793257938; Thu, 12 Oct 2017 00:27:37 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id r22sm26476100pfl.15.2017.10.12.00.27.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 00:27:37 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Thu, 12 Oct 2017 15:27:29 +0800 Message-Id: <1507793249-14386-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 Cc: Jacob Chen , David Wu Subject: [U-Boot] [PATCH] rockchip: rk3399: init CPU clock when rkclk_init() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Init the CPU and its buses to speed up the boot time. Move rkclk_init() to a place after rk3399_configure_cpu has defined at the same time, or else there will be a warning. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk3399.c | 157 +++++++++++++++++++------------------- 1 file changed, 79 insertions(+), 78 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 50faf5d..b9b1ead 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -398,84 +398,6 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -#ifdef CONFIG_SPL_BUILD -static void rkclk_init(struct rk3399_cru *cru) -{ - u32 aclk_div; - u32 hclk_div; - u32 pclk_div; - - /* - * some cru registers changed by bootrom, we'd better reset them to - * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these three lines as a fix of bootrom bug. - */ - rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); - rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); - rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); - - /* configure gpll cpll */ - rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); - rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); - - /* configure perihp aclk, hclk, pclk */ - aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; - assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); - - hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; - assert((hclk_div + 1) * PERIHP_HCLK_HZ == - PERIHP_ACLK_HZ && (hclk_div < 0x4)); - - pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; - assert((pclk_div + 1) * PERIHP_PCLK_HZ == - PERIHP_ACLK_HZ && (pclk_div < 0x7)); - - rk_clrsetreg(&cru->clksel_con[14], - PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | - ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, - pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | - hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | - ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | - aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); - - /* configure perilp0 aclk, hclk, pclk */ - aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; - assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); - - hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; - assert((hclk_div + 1) * PERILP0_HCLK_HZ == - PERILP0_ACLK_HZ && (hclk_div < 0x4)); - - pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; - assert((pclk_div + 1) * PERILP0_PCLK_HZ == - PERILP0_ACLK_HZ && (pclk_div < 0x7)); - - rk_clrsetreg(&cru->clksel_con[23], - PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | - ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, - pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | - hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | - ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | - aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); - - /* perilp1 hclk select gpll as source */ - hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; - assert((hclk_div + 1) * PERILP1_HCLK_HZ == - GPLL_HZ && (hclk_div < 0x1f)); - - pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; - assert((pclk_div + 1) * PERILP1_HCLK_HZ == - PERILP1_HCLK_HZ && (hclk_div < 0x7)); - - rk_clrsetreg(&cru->clksel_con[25], - PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | - HCLK_PERILP1_PLL_SEL_MASK, - pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | - hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | - HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); -} -#endif - void rk3399_configure_cpu(struct rk3399_cru *cru, enum apll_l_frequencies apll_l_freq) { @@ -1004,6 +926,85 @@ static struct clk_ops rk3399_clk_ops = { .enable = rk3399_clk_enable, }; +#ifdef CONFIG_SPL_BUILD +static void rkclk_init(struct rk3399_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + rk3399_configure_cpu(cru, APLL_L_600_MHZ); + /* + * some cru registers changed by bootrom, we'd better reset them to + * reset/default values described in TRM to avoid confusion in kernel. + * Please consider these three lines as a fix of bootrom bug. + */ + rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); + rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); + rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); + + /* configure gpll cpll */ + rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); + rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); + + /* configure perihp aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; + assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; + assert((hclk_div + 1) * PERIHP_HCLK_HZ == + PERIHP_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; + assert((pclk_div + 1) * PERIHP_PCLK_HZ == + PERIHP_ACLK_HZ && (pclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[14], + PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | + ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, + pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | + hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | + ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | + aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); + + /* configure perilp0 aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; + assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; + assert((hclk_div + 1) * PERILP0_HCLK_HZ == + PERILP0_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; + assert((pclk_div + 1) * PERILP0_PCLK_HZ == + PERILP0_ACLK_HZ && (pclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[23], + PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | + ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, + pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | + ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | + aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); + + /* perilp1 hclk select gpll as source */ + hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; + assert((hclk_div + 1) * PERILP1_HCLK_HZ == + GPLL_HZ && (hclk_div < 0x1f)); + + pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; + assert((pclk_div + 1) * PERILP1_HCLK_HZ == + PERILP1_HCLK_HZ && (hclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[25], + PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | + HCLK_PERILP1_PLL_SEL_MASK, + pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | + HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); +} +#endif + static int rk3399_clk_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD