From patchwork Sun Nov 18 14:17:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AdlozcMz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYy66szSz9rxp for ; Mon, 19 Nov 2018 01:19:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727487AbeKSAir (ORCPT ); Sun, 18 Nov 2018 19:38:47 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:45493 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726180AbeKSAir (ORCPT ); Sun, 18 Nov 2018 19:38:47 -0500 Received: by mail-wr1-f67.google.com with SMTP id v6so7434064wrr.12; Sun, 18 Nov 2018 06:18:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3cTRTYQX1dq39tst1PgcbJbQuLmJE6rf6FzcT64LsY8=; b=AdlozcMztriRqCcXr2wC8A6d8B3pcSLWJquUK38SXn16JOCZu104KACuuzxrkqW+Q2 yK394JGpcxwkGvX36XAow7Ql6MlIhtKWg/VfY4xXJiQSWfzW+5NmGAfDOpakmG2DdQjv pBBGnnxW+oAyvqJF2fOo7sPEX6FY7MfPOZjHXZnpFs4/aP7czu8X939dBXaqXFakOyOp Ng5A54dAoHP4bT5Lze0tlVzQkYTO/JoKiH+lcj4hZ6qx9L0Rw7NXN/u2gQ0J+Ly/A9eU jqAWEXm+Shgq8d//Uaajw0nRIkHlQBpZgE7e/UoE2cMYIwsLcU8+nDeRcmilKbYN+zFP dNKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3cTRTYQX1dq39tst1PgcbJbQuLmJE6rf6FzcT64LsY8=; b=dGt9zj0IKjdnCfqxYh8RZcyi1sYBxWw/TmrOqCdp5RxczJeOPAEknTwyHJtxpYOkK3 nw2utB0hQiOE1kNh7OC6wII65gkMmeGy2T9unzhHIlbT7345BM7BoFosr5BvWbzz4v3G 6S+ii0UTlRCM+pqgN/G46TraKHVofDADm0WaKlpc/7LQsHFrbMc3k7DyJJ/4Rm4MPdfh gS30KmE/CtSb5wc4uSTmKe65AdlUYdSn0u4tkIY/VS8JeISL4I6kWIimq0vChYG7mZJ4 j1LJVAi92iQP0rT8+dzWxaRCWyEKauhTNEyMNesi9o3j3OwEFxHHXqAU1EYAac5zgiFZ enbw== X-Gm-Message-State: AA+aEWYscxS1H54Ovbf8fI7CjkhWKO97wKvSAp1mtamHP6jdUVALJdL9 9iqz/Q8nAS3/Qzb+g9Hvf3m5RFVOCvE= X-Google-Smtp-Source: AFSGD/Ul9+8jogXL1LM/tbFPPz/NcOS93aYqOSylUm0a3gUBIekLyN+Yxm+bh0ag0YGPhG1/Le5f6Q== X-Received: by 2002:adf:d112:: with SMTP id a18mr2317549wri.17.1542550698939; Sun, 18 Nov 2018 06:18:18 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:18 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 01/14] ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs Date: Sun, 18 Nov 2018 17:17:00 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Allwinner also has some ARMv5 SoCs. In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI a common option which is selected by both V7 and V5 sunxi option. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- arch/arm/mach-sunxi/Kconfig | 25 +++++++++++++++++-------- arch/arm/mach-sunxi/Makefile | 2 +- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d9c8ecf..5db17ec 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -6,31 +6,38 @@ menuconfig ARCH_SUNXI select GENERIC_IRQ_CHIP select GPIOLIB select PINCTRL - select PM_OPP - select SUN4I_TIMER select RESET_CONTROLLER + help + Support for Allwinner ARM-based family of processors if ARCH_SUNXI +if ARCH_MULTI_V7 + +config ARCH_SUNXI_V7 + bool + select PM_OPP + select SUN4I_TIMER + config MACH_SUN4I bool "Allwinner A10 (sun4i) SoCs support" - default ARCH_SUNXI + select ARCH_SUNXI_V7 config MACH_SUN5I bool "Allwinner A10s / A13 (sun5i) SoCs support" - default ARCH_SUNXI + select ARCH_SUNXI_V7 select SUN5I_HSTIMER config MACH_SUN6I bool "Allwinner A31 (sun6i) SoCs support" - default ARCH_SUNXI + select ARCH_SUNXI_V7 select ARM_GIC select MFD_SUN6I_PRCM select SUN5I_HSTIMER config MACH_SUN7I bool "Allwinner A20 (sun7i) SoCs support" - default ARCH_SUNXI + select ARCH_SUNXI_V7 select ARM_GIC select ARM_PSCI select ARCH_SUPPORTS_BIG_ENDIAN @@ -39,13 +46,13 @@ config MACH_SUN7I config MACH_SUN8I bool "Allwinner sun8i Family SoCs support" - default ARCH_SUNXI + select ARCH_SUNXI_V7 select ARM_GIC select MFD_SUN6I_PRCM config MACH_SUN9I bool "Allwinner (sun9i) SoCs support" - default ARCH_SUNXI + select ARCH_SUNXI_V7 select ARM_GIC config ARCH_SUNXI_MC_SMP @@ -56,3 +63,5 @@ config ARCH_SUNXI_MC_SMP select ARM_CPU_SUSPEND endif + +endif diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 71429aa..c9a83ab 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1,5 +1,5 @@ CFLAGS_mc_smp.o += -march=armv7-a -obj-$(CONFIG_ARCH_SUNXI) += sunxi.o +obj-$(CONFIG_ARCH_SUNXI_V7) += sunxi.o obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o From patchwork Sun Nov 18 14:17:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UXSUS3jB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYy43klYz9s8F for ; Mon, 19 Nov 2018 01:19:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726180AbeKSAit (ORCPT ); Sun, 18 Nov 2018 19:38:49 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33128 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727421AbeKSAis (ORCPT ); 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Sun, 18 Nov 2018 06:18:20 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:20 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 02/14] dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC Date: Sun, 18 Nov 2018 17:17:01 +0300 Message-Id: <5ef0af61c17ae1fd523f15673042f63461e57cff.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add new Allwinner ARMv5 F1C100s SoC's compatible string Signed-off-by: Mesih Kilinc --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index e4beec3..12f1b00 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -3,6 +3,7 @@ Allwinner sunXi Platforms Device Tree Bindings Each device tree must specify which Allwinner SoC it uses, using one of the following compatible strings: + allwinner,suniv-f1c100s allwinner,sun4i-a10 allwinner,sun5i-a10s allwinner,sun5i-a13 From patchwork Sun Nov 18 14:17:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mapB0eIs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYwf4XKhz9s8F for ; Mon, 19 Nov 2018 01:18:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727586AbeKSAiw (ORCPT ); Sun, 18 Nov 2018 19:38:52 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:34426 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727551AbeKSAiv (ORCPT ); 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Sun, 18 Nov 2018 06:18:22 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:22 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 03/14] ARM: sunxi: add Allwinner ARMv5 SoCs Date: Sun, 18 Nov 2018 17:17:02 +0300 Message-Id: <8f07fac854eaaea63e199fe0e80cf20004dffbdf.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600). Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- arch/arm/mach-sunxi/Kconfig | 14 +++++++++++++- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/sunxi_v5.c | 22 ++++++++++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-sunxi/sunxi_v5.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 5db17ec..066644c 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,6 +1,6 @@ menuconfig ARCH_SUNXI bool "Allwinner SoCs" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V5 || ARCH_MULTI_V7 select ARCH_HAS_RESET_CONTROLLER select CLKSRC_MMIO select GENERIC_IRQ_CHIP @@ -64,4 +64,16 @@ config ARCH_SUNXI_MC_SMP endif +if ARCH_MULTI_V5 + +config ARCH_SUNXI_V5 + bool + select SUN4I_TIMER + +config MACH_SUNIV + bool "Allwinner new F-series (suniv) SoCs support" + select ARCH_SUNXI_V5 + +endif + endif diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index c9a83ab..fd17fdd 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1,5 +1,6 @@ CFLAGS_mc_smp.o += -march=armv7-a obj-$(CONFIG_ARCH_SUNXI_V7) += sunxi.o +obj-$(CONFIG_ARCH_SUNXI_V5) += sunxi_v5.o obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-sunxi/sunxi_v5.c b/arch/arm/mach-sunxi/sunxi_v5.c new file mode 100644 index 0000000..15f2d7a --- /dev/null +++ b/arch/arm/mach-sunxi/sunxi_v5.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for Allwinner F series SoCs + * + * Copyright (C) 2017 Icenowy Zheng + * Copyright (C) 2018 Mesih Kilinc + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +static const char * const suniv_board_dt_compat[] = { + "allwinner,suniv-f1c100s", + NULL, +}; + +DT_MACHINE_START(SUNXI_DT, "Allwinner suniv Family") + .dt_compat = suniv_board_dt_compat, +MACHINE_END From patchwork Sun Nov 18 14:17:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TKRrsbji"; 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Sun, 18 Nov 2018 06:18:23 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 04/14] dt-bindings: interrupt-controller: Add suniv interrupt-controller Date: Sun, 18 Nov 2018 17:17:03 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for Alwinner suniv F1C100s SoC interrupt controller which is stripped version of sun4i Signed-off-by: Mesih Kilinc --- .../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index b290ca1..e04ddb4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt @@ -2,7 +2,10 @@ Allwinner Sunxi Interrupt Controller Required properties: -- compatible : should be "allwinner,sun4i-a10-ic" +- compatible: should be "allwinner,--ic" to identify + Allwinner IRQ chip such as: + "allwinner,sun4i-a10-ic" + "allwinner,suniv-f1c100s-ic" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an From patchwork Sun Nov 18 14:17:04 2018 Content-Type: text/plain; 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Sun, 18 Nov 2018 06:18:26 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:25 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 05/14] irqchip/sun4i: add support for suniv interrupt controller Date: Sun, 18 Nov 2018 17:17:04 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13. Add support for it in irq-sun4i driver. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- drivers/irqchip/irq-sun4i.c | 47 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index e3e5b91..2abf662 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -23,13 +23,26 @@ #include +enum sun4i_irq_type { + sun4i_ic, + suniv_ic +}; + +static enum sun4i_irq_type sun4i_irq_type; +static int sun4i_irq_enable_reg_offset; +static int sun4i_irq_mask_reg_offset; + #define SUN4I_IRQ_VECTOR_REG 0x00 #define SUN4I_IRQ_PROTECTION_REG 0x08 #define SUN4I_IRQ_NMI_CTRL_REG 0x0c #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) -#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) -#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 +#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 +#define SUN4I_IRQ_ENABLE_REG(x) (sun4i_irq_enable_reg_offset + 0x4 * x) +#define SUN4I_IRQ_MASK_REG(x) (sun4i_irq_mask_reg_offset + 0x4 * x) static void __iomem *sun4i_irq_base; static struct irq_domain *sun4i_irq_domain; @@ -115,8 +128,9 @@ static int __init sun4i_of_init(struct device_node *node, writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); - /* Enable protection mode */ - writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); + /* Enable protection mode (not available in suniv) */ + if (sun4i_irq_type == sun4i_ic) + writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); /* Configure the external interrupt source type */ writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); @@ -130,7 +144,30 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + sun4i_irq_type = sun4i_ic; + sun4i_irq_enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + sun4i_irq_mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + sun4i_of_init(node, parent); + + return 0; +} +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + sun4i_irq_type = suniv_ic; + sun4i_irq_enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + sun4i_irq_mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + sun4i_of_init(node, parent); + + return 0; +} +IRQCHIP_DECLARE(allwinner_suniv_ic, "allwinner,suniv-f1c100s-ic", suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) { From patchwork Sun Nov 18 14:17:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; 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Sun, 18 Nov 2018 06:18:28 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:27 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 06/14] dt-bindings: timer: Add Allwinner suniv timer Date: Sun, 18 Nov 2018 17:17:05 +0300 Message-Id: <64b7dbecd4479e0078ad0252af1218cbb4b2b409.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for Allwinner suniv timer which is similar to sun4i timer. Signed-off-by: Mesih Kilinc --- Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt index 5c2e235..9c02a4b 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt @@ -2,7 +2,10 @@ Allwinner A1X SoCs Timer Controller Required properties: -- compatible : should be "allwinner,sun4i-a10-timer" +- compatible: should be "allwinner,--timer" to identify + Allwinner SoCs timer such as: + "allwinner,sun4i-a10-timer" + "allwinner,suniv-f1c100s-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The interrupt of the first timer - clocks: phandle to the source clock (usually a 24 MHz fixed clock) From patchwork Sun Nov 18 14:17:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999483 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sElgiw+h"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYwq0n24z9sBZ for ; Mon, 19 Nov 2018 01:18:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727841AbeKSAi7 (ORCPT ); Sun, 18 Nov 2018 19:38:59 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:37218 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727551AbeKSAi6 (ORCPT ); Sun, 18 Nov 2018 19:38:58 -0500 Received: by mail-wr1-f67.google.com with SMTP id j10so15080725wru.4; Sun, 18 Nov 2018 06:18:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oGuO4g5d4BywTnSWFeiSH0OPNxp/zYl7PCyVPQHD8Yk=; b=sElgiw+hYJBO0PQjhcVYNlAGxyhgXBSR7WiYFdMLsvlqK58H/fJpY8jKVD6U5SqR88 IkPgmL/m9qXuwAhdPa2E8wkHH2pM/QffmRJvkV8nP1bq+BPG/gN41gVeNz4wNnM6q/EE 9v5h2xtaaJizv9S8qOrTe5TpYwOy8gNfWFIs8V9MpGAphLWnJbtAF9dNmfE6K80GJmW/ Ac4oyuxJk1x11ksjB/j14WDZzdSiIF8NannGCgRRZhfRNi52QvMwyIbm7R/NRxgEO21g QJ1P3Eyjs/UAD0M5PkMwjtBbMmfrEf7PsCaLqXfRSlXfgnweX6LpYGxXe0IDmPPGe6GW WQYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oGuO4g5d4BywTnSWFeiSH0OPNxp/zYl7PCyVPQHD8Yk=; b=QXvGAobcxppQvTuy6xn+wJbwtvJMUn6aMI2mOxgb3mbv3hb7jRGgOrH52WqVLtg52h womXGEstKsBNnFJUJCZzOjoThp6p12TSoaxdFByI0SVuw8MS8Ae8rt6oA4d8rmyCBfyO fb9wnGoM61UcQJSZBHZiOydAAw6ket6jLRaNeQDdT+aF0+hi9tJMShyJsaW4CfGadPTH u3MNPcEKM8NtOziEdx0stih9s9MV1L5KXXMwySqjtDb0r3Jci+TKkXw0rlcfAq7t8wag WU0KeFo1qMToF+GqS4DoNUdlgI98iPxThAAoSBLa4ccOXxvNrSYl27tdvQgKNwC5dJvk 2IKg== X-Gm-Message-State: AA+aEWZwVr56y4PVWb7SuY1G7vsYeuRYYaignxR9RyPB85U5Qbqu26Uq tFmjt4e6qDOOXm0k4HwgeLwr4qrwfgk= X-Google-Smtp-Source: AFSGD/UiZb28HJFBCaBxFmvxj87YRZJRXFPZ2ob5bOSngZaTCMSzkM6/d/ZiAXMYnhXwTt+McL2dkw== X-Received: by 2002:adf:fe11:: with SMTP id n17mr12730881wrr.329.1542550709892; Sun, 18 Nov 2018 06:18:29 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:29 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 07/14] clocksource: sun4i: add a compatible for suniv Date: Sun, 18 Nov 2018 17:17:06 +0300 Message-Id: <9edf969f763ecb7433a9d56adfc36cf8a0ec998d.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- drivers/clocksource/sun4i_timer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 6e0180a..6b57187 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -218,3 +218,5 @@ static int __init sun4i_timer_init(struct device_node *node) } TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", sun4i_timer_init); +TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer", + sun4i_timer_init); From patchwork Sun Nov 18 14:17:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gM08RfzR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYxg421Lz9s8F for ; Mon, 19 Nov 2018 01:19:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbeKSAjA (ORCPT ); Sun, 18 Nov 2018 19:39:00 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:52554 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727421AbeKSAjA (ORCPT ); Sun, 18 Nov 2018 19:39:00 -0500 Received: by mail-wm1-f68.google.com with SMTP id r11-v6so2816264wmb.2; Sun, 18 Nov 2018 06:18:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nOWCmF7nU3ccya4YN9rbWAijBsLEbSVxqe2kT30yoK8=; b=gM08RfzRh7oxMGyyvxU7Nb+mwt8uopmtlJcbDXbuw5O/7gun4iV8O8lUXigBvmWwUG 0X0i3KN44ezJ5kMY2DYzzsu5X6nllr939V3VMBKt6G4oJne+UJ+ixl0aoUYxmpSG9ACW ARc6Qeg4AtVM50uJ4/Woaye1d0HqJhhEh8iJdFPnzExh7hlJXG7agEOeVN0+ORbhvqUd 8iOwOkAkPcMmCEDA4N65wWBJfHApYx6nhTUFuZhf9yp8PUTMqMb8Bh9rk7mx8IcRmQ9t lemcSglmwd8RL497od4RIVFf6RtskrHJwdP4D6JAN4+rUHD/C1klbG+Q+7yd9jBeyDk+ 7WRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nOWCmF7nU3ccya4YN9rbWAijBsLEbSVxqe2kT30yoK8=; b=j9+zvcX/WBSAVq+mlWg5sVjSsoO9IShBk/Q0QrK7x8bgAEgeTz7O31Wq0B2A677K9x Ld85ZIT/GmxUk5GAxjWTyDur9PsZawYNo93yvnt0UB5aZ5sl2buaFtCvciSYrno4swO/ WHSfZa6HbYu2KLPCz4Oq8ljldqJNNPNlk9qhDBdW13JJ1aqFKBmpwsi50Yizcw+CzAm+ h7yXCllukohTTSYLT3PCg/cqcxqvC03DABB3eJ+paD+Vg9CZ/5u++1dOA4kGdB80FPNp T2xnM9f5tHlK2v0Ko8I3R2D79l+hEnaXPTwOlqnXfF9NZbVqwAN/pVFeAi81ssDDyNXE WqHA== X-Gm-Message-State: AA+aEWYjOQzl4/NNQyCnFKcYPDyGYl4PSoLFRnfFSo4NMrXLu1S1mkRg bHd72kVJ/y9xixh66L3cHSWO7z7zkpQ= X-Google-Smtp-Source: AJdET5dzgXfJvWLPs/9AKObcoIH/A1ISLaEEO/kKPV1MZ1mpcIefoTpNAXD/K7WtMZJBN2Z1rYBGxw== X-Received: by 2002:a1c:5788:: with SMTP id l130-v6mr4306653wmb.60.1542550711887; Sun, 18 Nov 2018 06:18:31 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:31 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 08/14] clocksource/drivers/sun4i: register as sched_clock on suniv Date: Sun, 18 Nov 2018 17:17:07 +0300 Message-Id: <6f4773bdef8979bff71e958c9ca2c832c68ada0d.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv chip (newer F-series Allwinner SoCs) is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- drivers/clocksource/sun4i_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 6b57187..65f38f6 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || - of_machine_is_compatible("allwinner,sun5i-a10s")) + of_machine_is_compatible("allwinner,sun5i-a10s") || + of_machine_is_compatible("allwinner,suniv-f1c100s")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); From patchwork Sun Nov 18 14:17:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999484 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Yo2E4Lbr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYwt2g40z9sB5 for ; Mon, 19 Nov 2018 01:18:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727944AbeKSAjC (ORCPT ); Sun, 18 Nov 2018 19:39:02 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:41209 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727551AbeKSAjC (ORCPT ); Sun, 18 Nov 2018 19:39:02 -0500 Received: by mail-wr1-f67.google.com with SMTP id x10so645790wrs.8; Sun, 18 Nov 2018 06:18:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Xu7tw3hMoHQOvn1iK3m+Q2vz8pwKTqStprFDM6Xgq1g=; b=Yo2E4LbrQyhK97AQI7z5/bqdXWwiPK5qHe6RWcvCWl6Kw9cQEk+7zZSPKHsbjGbUsk /pJSj67BUi5AAzWP8I/l4VOdm+0uEBV2SWvvdbn1ImqjERj7GqnZkGCQ4XWirgvJaNlE 4XDtN9zbpZHJawKM4iMOTzBEroK7vlmVMlOMwUoUL7n1SSXi+gxoXUeiyU1hEsN8mABG bfTreFAAx1WcwqNkRUxR5sQqTOekdzy4PHyY8oOBpiYozq9Chhpb2gpu7MKZHImd4HkA v7Mteh6eC4GvvwtuHGZsFdRKFoHBCtlA4nXpZH/HkE267Wn3C7WKMZ+wQS+uBS46F4sN l2yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xu7tw3hMoHQOvn1iK3m+Q2vz8pwKTqStprFDM6Xgq1g=; b=Xf6VuROdAqQF/KVQnEkUX57EHHA23SygRP7xZjlsE5DjJQA15S+7a66obOEwdpvXNc y3xdqrzNibQkYgGn0rrCNHq3wGGgzmPLO6dqwY0eXiawgrqu67kygp7CE07VZy6xltAK GbvIvma0zv7elmBOGGZRZzfs06K3HGv0chwudX6QN2uDWGVb7CF+WJtL0vdurY5cbSiO PfFLOLmF/nmzkp+c0rq9O+vamDj/RO+P+h4h89IXygbIbX05Qz0RFgdFx0NvZebeNtvn 7bgd+H9q9g2I3J2Z9LriyzpGRwmEnJ1fPmCXZKbwNgYt81VfKsTAON/gfU0xEp2wOEZQ 2IAw== X-Gm-Message-State: AGRZ1gLWxP+hPfO7hUejo4nB+E2oByz9mFC1qgq+bFZFkTjXGemchRyW ZJBtox+6aWnUB1nT9y0JcqQ2oKtaCxk= X-Google-Smtp-Source: AJdET5drRZyaoUj+oRtrwP5TlR566/kACuA+hKmYzMciamLXhomsM1i8qzYhAGUwTm6FUUDMixDzSA== X-Received: by 2002:a5d:4cc6:: with SMTP id c6-v6mr14832444wrt.75.1542550713632; Sun, 18 Nov 2018 06:18:33 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:33 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 09/14] dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl Date: Sun, 18 Nov 2018 17:17:08 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for Allwinner suniv F1C100s SoC's pinctrl. Signed-off-by: Mesih Kilinc --- Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 258a464..5086734 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -7,6 +7,7 @@ the pins includes drive strength and pull-up. Required properties: - compatible: Should be one of the following (depending on your SoC): + "allwinner,suniv-f1c100s-pinctrl" "allwinner,sun4i-a10-pinctrl" "allwinner,sun5i-a10s-pinctrl" "allwinner,sun5i-a13-pinctrl" From patchwork Sun Nov 18 14:17:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OWSCqmUC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42yYxW4X43z9s6w for ; Mon, 19 Nov 2018 01:19:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727974AbeKSAjF (ORCPT ); Sun, 18 Nov 2018 19:39:05 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46425 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727885AbeKSAjE (ORCPT ); Sun, 18 Nov 2018 19:39:04 -0500 Received: by mail-wr1-f66.google.com with SMTP id l9so16423120wrt.13; Sun, 18 Nov 2018 06:18:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=86NOAPJc/1O/jJXH27ZQpP/igqBpUm1CiXzQRoBQ5tk=; b=OWSCqmUCODKZZc4M4hKGnJZ0Fvcuyrbt6TFWOhdLFKvq/KMDloTkxHfCXRXvhbDhMG 4fm0LK3y67TMnjsRtf6fhJM+QTYW6/7ieWhbUQL3BbQYrnCFx5sMyAKUiB6kAm5zJLAS O4FUjYRz8yU1Gfb41p7/HDkID39TFIzPYJ5LN3ftzt1FU3J4w0kF6/+8Kc3X6yg0+/Zz DZaiV5QrWAfVlZsmTZOZZbD2fG9js5XxJnoJl3CFvxSpWModm77DtZT9NbXyEZJBCr55 sv/LUEqMQIsMxpHYr52kp85xGEc4aBK/ZzFQCVfD+LzLl/6MLKRqTzTePm80o5Mivtmt ciFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=86NOAPJc/1O/jJXH27ZQpP/igqBpUm1CiXzQRoBQ5tk=; b=CKSMM5lhkSRw6CAAx1jDVRv30Dss+7nTg3bgSVCU80uPoEGKxvnqpv1V/wox7eNfV4 8eVJseyHXwN6XwzpBp7BgYSjr8zEVgz0yAzt7MtbHOjFZLOJAeZqcqqLIaQw+Cozck+u lgSnHRqaTVUU+9ZPUtkUJ3ZOVR9gREHfrS9F1cVtOO7xA/cyOmf0E2sGZxvMrrW0O9KD FyYcpMABzP+zs6zM5Ppql0FOAGnXP89EZaYfisV63lOH4Ic6xmNkHdI2xR8NGVbiMf2a xo3/WzZJGj19hK3lqLmo21QdFctvkMCkbSs8Tb5OQE8rhE2MltIqAAFNjMxGQDz+6n4b HiZg== X-Gm-Message-State: AGRZ1gK2KUl+Z0B214m9B7l8x5jc0bAMfsW79oSvbvSX0rM270gmaOyx /yw9VjZkyoUJ8b2tUSd+3jIQ6AYkvfQ= X-Google-Smtp-Source: AJdET5eDF/o7lk50eFJUdDZPk82dkc/I4MC8D3cAPD0IIxKyT28YzdlPsfhaQKIFITqFTh5myBfmew== X-Received: by 2002:a5d:40cc:: with SMTP id b12-v6mr16040764wrq.133.1542550715845; Sun, 18 Nov 2018 06:18:35 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:35 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 10/14] pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs) Date: Sun, 18 Nov 2018 17:17:09 +0300 Message-Id: <706ba2bf049396c1aa99b8a47260f451935d2dc2.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c | 417 ++++++++++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 95282cd..a731fc9 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -6,6 +6,10 @@ config PINCTRL_SUNXI select GENERIC_PINCONF select GPIOLIB +config PINCTRL_SUNIV_F1C100S + def_bool MACH_SUNIV + select PINCTRL_SUNXI + config PINCTRL_SUN4I_A10 def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index adb8443..fafcdae 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -3,6 +3,7 @@ obj-y += pinctrl-sunxi.o # SoC Drivers +obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c new file mode 100644 index 0000000..46d5667 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c @@ -0,0 +1,417 @@ +/* + * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver. + * + * Copyright (C) 2018 Icenowy Zheng + * + * Icenowy Zheng + * + * Copyright (C) 2014 Jackie Hwang + * + * Jackie Hwang + * + * Copyright (C) 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" +static const struct sunxi_desc_pin suniv_f1c100s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X2 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* CKE */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D4*/ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ + SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ + SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ + SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ + SUNXI_FUNCTION(0x3, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ + SUNXI_FUNCTION(0x3, "i2s"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi0"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D0 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION(0x5, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D1 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION(0x5, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "lcd"), /* D8 */ + SUNXI_FUNCTION(0x4, "clk"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D9 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D16 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D17 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "clk0"), /* OUT */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "ir"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION(0x4, "ir0"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "dgb0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), +}; + +static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = { + .pins = suniv_f1c100s_pins, + .npins = ARRAY_SIZE(suniv_f1c100s_pins), + .irq_banks = 3, + .disable_strict_mode = true, +}; + +static int suniv_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &suniv_f1c100s_pinctrl_data); +} + +static const struct of_device_id suniv_f1c100s_pinctrl_match[] = { + { .compatible = "allwinner,suniv-f1c100s-pinctrl", }, + {} +}; + +static struct platform_driver suniv_f1c100s_pinctrl_driver = { + .probe = suniv_pinctrl_probe, + .driver = { + .name = "suniv-f1c100s-pinctrl", + .of_match_table = suniv_f1c100s_pinctrl_match, + }, +}; +builtin_platform_driver(suniv_f1c100s_pinctrl_driver); From patchwork Sun Nov 18 14:17:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999488 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; 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PATCH v2 11/14] dt-bindings: clock: Add Allwinner suniv F1C100s CCU Date: Sun, 18 Nov 2018 17:17:10 +0300 Message-Id: <5f0322d5e37726f0c597b919f59e121f0b2855c3.1542546735.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc --- .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + include/dt-bindings/clock/suniv-ccu-f1c100s.h | 69 ++++++++++++++++++++++ include/dt-bindings/reset/suniv-ccu-f1c100s.h | 37 ++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 47d2e90..92c16eb 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -3,6 +3,7 @@ Allwinner Clock Control Unit Binding Required properties : - compatible: must contain one of the following compatibles: + - "allwinner,suniv-f1c100s-ccu" - "allwinner,sun4i-a10-ccu" - "allwinner,sun5i-a10s-ccu" - "allwinner,sun5i-a13-ccu" diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h new file mode 100644 index 0000000..56f6d0d --- /dev/null +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2018 Icenowy Zheng + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ + +#define CLK_CPU 11 + +#define CLK_BUS_MMC0 14 +#define CLK_BUS_MMC1 15 +#define CLK_BUS_DRAM 16 +#define CLK_BUS_SPI0 17 +#define CLK_BUS_SPI1 18 +#define CLK_BUS_OTG 19 +#define CLK_BUS_VE 20 +#define CLK_BUS_LCD 21 +#define CLK_BUS_DEINTERLACE 22 +#define CLK_BUS_CSI 23 +#define CLK_BUS_TVD 24 +#define CLK_BUS_TVE 25 +#define CLK_BUS_DE_BE 26 +#define CLK_BUS_DE_FE 27 +#define CLK_BUS_CODEC 28 +#define CLK_BUS_SPDIF 29 +#define CLK_BUS_IR 30 +#define CLK_BUS_RSB 31 +#define CLK_BUS_I2S0 32 +#define CLK_BUS_I2C0 33 +#define CLK_BUS_I2C1 34 +#define CLK_BUS_I2C2 35 +#define CLK_BUS_PIO 36 +#define CLK_BUS_UART0 37 +#define CLK_BUS_UART1 38 +#define CLK_BUS_UART2 39 + +#define CLK_MMC0 40 +#define CLK_MMC0_SAMPLE 41 +#define CLK_MMC0_OUTPUT 42 +#define CLK_MMC1 43 +#define CLK_MMC1_SAMPLE 44 +#define CLK_MMC1_OUTPUT 45 +#define CLK_I2S 46 +#define CLK_SPDIF 47 + +#define CLK_USB_PHY0 48 + +#define CLK_DRAM_VE 49 +#define CLK_DRAM_CSI 50 +#define CLK_DRAM_DEINTERLACE 51 +#define CLK_DRAM_TVD 52 +#define CLK_DRAM_DE_FE 53 +#define CLK_DRAM_DE_BE 54 + +#define CLK_DE_BE 55 +#define CLK_DE_FE 56 +#define CLK_TCON 57 +#define CLK_DEINTERLACE 58 +#define CLK_TVE2_CLK 59 +#define CLK_TVE1_CLK 60 +#define CLK_TVD 61 +#define CLK_CSI 62 +#define CLK_VE 63 +#define CLK_CODEC 64 +#define CLK_AVS 65 + +#endif diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h new file mode 100644 index 0000000..95f1ed0 --- /dev/null +++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Icenowy Zheng + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ + +#define RST_USB_PHY0 0 +#define RST_BUS_MMC0 1 +#define RST_BUS_MMC1 2 +#define RST_BUS_DRAM 3 +#define RST_BUS_SPI0 4 +#define RST_BUS_SPI1 5 +#define RST_BUS_OTG 6 +#define RST_BUS_VE 7 +#define RST_BUS_LCD 8 +#define RST_BUS_DEINTERLACE 9 +#define RST_BUS_CSI 10 +#define RST_BUS_TVD 11 +#define RST_BUS_TVE 12 +#define RST_BUS_DE_BE 13 +#define RST_BUS_DE_FE 14 +#define RST_BUS_CODEC 15 +#define RST_BUS_SPDIF 16 +#define RST_BUS_IR 17 +#define RST_BUS_RSB 18 +#define RST_BUS_I2S0 19 +#define RST_BUS_I2C0 20 +#define RST_BUS_I2C1 21 +#define RST_BUS_I2C2 22 +#define RST_BUS_UART0 23 +#define RST_BUS_UART1 24 +#define RST_BUS_UART2 25 + +#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ From patchwork Sun Nov 18 14:17:11 2018 Content-Type: text/plain; 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Sun, 18 Nov 2018 06:18:40 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:39 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 12/14] clk: sunxi-ng: add support for suniv F1C100s SoC Date: Sun, 18 Nov 2018 17:17:11 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv F1C100s SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 536 +++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 34 ++ 4 files changed, 576 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 826674d..429ea4a 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -6,6 +6,11 @@ config SUNXI_CCU if SUNXI_CCU +config SUNIV_F1C100S_CCU + bool "Support for the Allwinner newer F1C100s CCU" + default MACH_SUNIV + depends on MACH_SUNIV || COMPILE_TEST + config SUN50I_A64_CCU bool "Support for the Allwinner A64 CCU" default ARM64 && ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 4945470..4c7bee8 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -21,6 +21,7 @@ obj-y += ccu_nm.o obj-y += ccu_mp.o # SoC support +obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file mode 100644 index 0000000..d933dba --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2016 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-suniv-f1c100s.h" + +static struct ccu_nkmp pll_cpu_clk = { + .enable = BIT(31), + .lock = BIT(28), + + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + /* MAX is guessed by the BSP table */ + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + + .common = { + .reg = 0x000, + .hw.init = CLK_HW_INIT("pll-cpu", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUNIV_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_IS_CRITICAL); + +static struct ccu_nk pll_periph_clk = { + .enable = BIT(31), + .lock = BIT(28), + .k = _SUNXI_CCU_MULT(4, 2), + .n = _SUNXI_CCU_MULT(8, 5), + .common = { + .reg = 0x028, + .hw.init = CLK_HW_INIT("pll-periph", "osc24M", + &ccu_nk_ops, 0), + }, +}; + +static const char * const cpu_parents[] = { "osc32k", "osc24M", + "pll-cpu", "pll-cpu" }; +static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); + +static const char * const ahb_parents[] = { "osc32k", "osc24M", + "cpu", "pll-periph" }; +static const struct ccu_mux_var_prediv ahb_predivs[] = { + { .index = 3, .shift = 6, .width = 2 }, +}; +static struct ccu_div ahb_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .var_predivs = ahb_predivs, + .n_var_predivs = ARRAY_SIZE(ahb_predivs), + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb", + ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb", + 0x054, 8, 2, apb_div_table, 0); + +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb", + 0x060, BIT(24), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb", + 0x064, BIT(5), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb", + 0x064, BIT(9), 0); +static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb", + 0x064, BIT(10), 0); +static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb", + 0x064, BIT(14), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb", + 0x068, BIT(2), 0); +static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb", + 0x068, BIT(3), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb", + 0x068, BIT(16), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb", + 0x068, BIT(17), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb", + 0x068, BIT(18), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb", + 0x068, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb", + 0x068, BIT(20), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb", + 0x068, BIT(21), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb", + 0x068, BIT(22), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", + 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", + 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", + 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", + 0x08c, 8, 3, 0); + +static const char * const i2s_spdif_parents[] = { "pll-audio-8x", + "pll-audio-4x", + "pll-audio-2x", + "pll-audio" }; + +static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, + 0x0b4, 16, 2, BIT(31), 0); + +/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */ + +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", + "pll-ddr", 0x100, BIT(2), 0); +static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr", + 0x100, BIT(3), 0); +static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", + 0x100, BIT(24), 0); +static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", + 0x100, BIT(26), 0); + +static const char * const de_parents[] = { "pll-video", "pll-periph" }; +static const u8 de_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", + de_parents, de_table, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", + de_parents, de_table, + 0x10c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 tcon_table[] = { 0, 2, }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon", + tcon_parents, tcon_table, + 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + +static const char * const deinterlace_parents[] = { "pll-video", + "pll-video-2x" }; +static const u8 deinterlace_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace", + deinterlace_parents, deinterlace_table, + 0x11c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tve_clk2_parents[] = { "pll-video", + "pll-video-2x" }; +static const u8 tve_clk2_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2", + tve_clk2_parents, tve_clk2_table, + 0x120, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2", + 0x120, 8, 1, BIT(15), 0); + +static const char * const tvd_parents[] = { "pll-video", "osc24M", + "pll-video-2x" }; +static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, + 0x124, 0, 4, 24, 3, BIT(31), 0); + +static const char * const csi_parents[] = { "pll-video", "osc24M" }; +static const u8 csi_table[] = { 0, 5, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, + 0x120, 0, 4, 8, 3, BIT(15), 0); + +/* + * TODO: BSP says the parent is pll-audio, however common sense and experience + * told us it should be pll-ve. pll-ve is totally not used in BSP code. + */ +static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0); + +static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0); + +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); + +static struct ccu_common *suniv_ccu_clks[] = { + &pll_cpu_clk.common, + &pll_audio_base_clk.common, + &pll_video_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph_clk.common, + &cpu_clk.common, + &ahb_clk.common, + &apb_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_dram_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ve_clk.common, + &bus_lcd_clk.common, + &bus_deinterlace_clk.common, + &bus_csi_clk.common, + &bus_tve_clk.common, + &bus_tvd_clk.common, + &bus_de_be_clk.common, + &bus_de_fe_clk.common, + &bus_codec_clk.common, + &bus_spdif_clk.common, + &bus_ir_clk.common, + &bus_rsb_clk.common, + &bus_i2s0_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_pio_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &i2s_clk.common, + &spdif_clk.common, + &usb_phy0_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_deinterlace_clk.common, + &dram_tvd_clk.common, + &dram_de_fe_clk.common, + &dram_de_be_clk.common, + &de_be_clk.common, + &de_fe_clk.common, + &tcon_clk.common, + &deinterlace_clk.common, + &tve_clk2_clk.common, + &tve_clk1_clk.common, + &tvd_clk.common, + &csi_clk.common, + &ve_clk.common, + &codec_clk.common, + &avs_clk.common, +}; + +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", + "pll-video", 1, 2, 0); + +static struct clk_hw_onecell_data suniv_hw_clks = { + .hws = { + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, + [CLK_CPU] = &cpu_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB] = &apb_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_TVD] = &bus_tvd_clk.common.hw, + [CLK_BUS_TVE] = &bus_tve_clk.common.hw, + [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, + [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_IR] = &bus_ir_clk.common.hw, + [CLK_BUS_RSB] = &bus_rsb_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_I2S] = &i2s_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, + [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw, + [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, + [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, + [CLK_DE_BE] = &de_be_clk.common.hw, + [CLK_DE_FE] = &de_fe_clk.common.hw, + [CLK_TCON] = &tcon_clk.common.hw, + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, + [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw, + [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw, + [CLK_TVD] = &tvd_clk.common.hw, + [CLK_CSI] = &csi_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_CODEC] = &codec_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map suniv_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_LCD] = { 0x2c4, BIT(4) }, + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_TVD] = { 0x2c4, BIT(9) }, + [RST_BUS_TVE] = { 0x2c4, BIT(10) }, + [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, + [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, + [RST_BUS_IR] = { 0x2d0, BIT(2) }, + [RST_BUS_RSB] = { 0x2d0, BIT(3) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2C0] = { 0x2d0, BIT(16) }, + [RST_BUS_I2C1] = { 0x2d0, BIT(17) }, + [RST_BUS_I2C2] = { 0x2d0, BIT(18) }, + [RST_BUS_UART0] = { 0x2d0, BIT(20) }, + [RST_BUS_UART1] = { 0x2d0, BIT(21) }, + [RST_BUS_UART2] = { 0x2d0, BIT(22) }, +}; + +static const struct sunxi_ccu_desc suniv_ccu_desc = { + .ccu_clks = suniv_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks), + + .hw_clks = &suniv_hw_clks, + + .resets = suniv_ccu_resets, + .num_resets = ARRAY_SIZE(suniv_ccu_resets), +}; + +static struct ccu_pll_nb suniv_pll_cpu_nb = { + .common = &pll_cpu_clk.common, + /* copy from pll_cpu_clk */ + .enable = BIT(31), + .lock = BIT(28), +}; + +static struct ccu_mux_nb suniv_cpu_nb = { + .common = &cpu_clk.common, + .cm = &cpu_clk.mux, + .delay_us = 1, /* > 8 clock cycles at 24 MHz */ + .bypass_index = 1, /* index of 24 MHz oscillator */ +}; + +static void __init suniv_f1c100s_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%pOF: Could not map the clock registers\n", node); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUNIV_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG); + + sunxi_ccu_probe(node, reg, &suniv_ccu_desc); + + /* Gate then ungate PLL CPU after any rate changes */ + ccu_pll_notifier_register(&suniv_pll_cpu_nb); + + /* Reparent CPU during PLL CPU rate changes */ + ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, + &suniv_cpu_nb); +} +CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu", + suniv_f1c100s_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h new file mode 100644 index 0000000..1da687a --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h @@ -0,0 +1,34 @@ +/* + * Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CCU_SUNIV_F1C100S_H_ +#define _CCU_SUNIV_F1C100S_H_ + +#include +#include + +#define CLK_PLL_CPU 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_AUDIO_2X 3 +#define CLK_PLL_AUDIO_4X 4 +#define CLK_PLL_AUDIO_8X 5 +#define CLK_PLL_VIDEO 6 +#define CLK_PLL_VIDEO_2X 7 +#define CLK_PLL_VE 8 +#define CLK_PLL_DDR0 9 +#define CLK_PLL_PERIPH 10 + +/* CPU clock is exported */ + +#define CLK_AHB 12 +#define CLK_APB 13 + +/* All bus gates, DRAM gates and mod clocks are exported */ + +#define CLK_NUMBER (CLK_AVS + 1) + +#endif /* _CCU_SUNIV_F1C100S_H_ */ From patchwork Sun Nov 18 14:17:12 2018 Content-Type: text/plain; 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Sun, 18 Nov 2018 06:18:42 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:42 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby , Mesih Kilinc Subject: [RFC PATCH v2 13/14] ARM: dts: suniv: add initial DTSI file for F1C100s Date: Sun, 18 Nov 2018 17:17:12 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 158 +++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 0000000..d98f658 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + * Copyright 2018 Mesih Kilinc + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + fake100M: clk-100M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "fake-100M"; + }; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pins_a: uart-pins-pe { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + }; +}; From patchwork Sun Nov 18 14:17:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 999485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Sun, 18 Nov 2018 06:18:44 -0800 (PST) Received: from ThinkPad.home ([185.219.176.209]) by smtp.gmail.com with ESMTPSA id d4sm29814412wrp.89.2018.11.18.06.18.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Nov 2018 06:18:43 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v2 14/14] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano Date: Sun, 18 Nov 2018 17:17:13 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Icenowy Zheng Signed-off-by: Mesih Kilinc --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d..2b96a5b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1066,6 +1066,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts new file mode 100644 index 0000000..6ae5ccc --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +/ { + model = "Lichee Pi Nano"; + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +};