From patchwork Mon Nov 12 17:08:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyVM0rQpz9s3q for ; Tue, 13 Nov 2018 04:31:38 +1100 (AEDT) Received: from localhost ([::1]:49890 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG3j-00068q-Ex for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:31:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFih-0004p9-Ne for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFid-0001J7-Vl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:51 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFiY-0008MG-Ez for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:45 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhF-0005qq-DX for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:21 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:01 +0000 Message-Id: <20181112170816.500-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/16] target/arm: Remove workaround for small SAU regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Before we supported direct execution from MMIO regions, we implemented workarounds in commit 720424359917887c926a33d2 which let us avoid doing so, even if the SAU or MPU region was less than page-sized. Once we implemented execute-from-MMIO, we removed part of those workarounds in commit d4b6275df320cee76; but we forgot the one in get_phys_addr_pmsav8() which suppressed use of small SAU regions in executable regions. Remove that workaround now. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20181106163801.14474-1-peter.maydell@linaro.org --- target/arm/helper.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 96301930cc8..ec56becc394 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10560,18 +10560,6 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, txattrs, prot, &mpu_is_subpage, fi, NULL); - /* - * TODO: this is a temporary hack to ignore the fact that the SAU region - * is smaller than a page if this is an executable region. We never - * supported small MPU regions, but we did (accidentally) allow small - * SAU regions, and if we now made small SAU regions not be executable - * then this would break previously working guest code. We can't - * remove this until/unless we implement support for execution from - * small regions. - */ - if (*prot & PAGE_EXEC) { - sattrs.subpage = false; - } *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } From patchwork Mon Nov 12 17:08:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyQp6Pqrz9s3q for ; Tue, 13 Nov 2018 04:28:34 +1100 (AEDT) Received: from localhost ([::1]:49872 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG0m-0003cT-3g for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:28:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFiJ-0004V6-UH for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFiJ-0001C1-Aj for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFiJ-0008MG-3g for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhG-0005r5-9Y for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:02 +0000 Message-Id: <20181112170816.500-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/16] target/arm: Remove antique TODO comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Remove a TODO comment about implementing the vectored interrupt controller. We have had an implementation of that for a decade; it's in hw/intc/pl190.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181106164118.16184-1-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- target/arm/helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ec56becc394..851ea9aa977 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8378,7 +8378,6 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) return; } - /* TODO: Vectored interrupt controller. */ switch (cs->exception_index) { case EXCP_UDEF: new_mode = ARM_CPU_MODE_UND; From patchwork Mon Nov 12 17:08:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyN36yx4z9s47 for ; Tue, 13 Nov 2018 04:26:11 +1100 (AEDT) Received: from localhost ([::1]:49863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFyT-0001D5-7u for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:26:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFiJ-0004UN-46 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFiI-0001BD-D8 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFiI-0008MG-4Z for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:26 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhH-0005rJ-5w for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:23 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:03 +0000 Message-Id: <20181112170816.500-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/16] MAINTAINERS: Add an entry for the 'collie' machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth There is no active maintainer, but since Peter is picking up patches via qemu-arm@nongnu.org, I think we could at least use "Odd Fixes" as status here. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 1541528230-31817-1-git-send-email-thuth@redhat.com [PMM: Also add myself as an M: contact] Signed-off-by: Peter Maydell --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c076758b3d6..4b8db618f51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -591,6 +591,13 @@ F: hw/*/pxa2xx* F: hw/misc/mst_fpga.c F: include/hw/arm/pxa.h +Sharp SL-5500 (Collie) PDA +M: Peter Maydell +L: qemu-arm@nongnu.org +S: Odd Fixes +F: hw/arm/collie.c +F: hw/arm/strongarm* + Stellaris M: Peter Maydell L: qemu-arm@nongnu.org From patchwork Mon Nov 12 17:08:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996570 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyK06pcwz9s3Z for ; Tue, 13 Nov 2018 04:23:32 +1100 (AEDT) Received: from localhost ([::1]:49844 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFvu-0007Wt-Cj for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:23:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFi8-0004KL-5s for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFi7-0000sQ-AF for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:16 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFi7-0008MG-1G for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhI-0005rX-2z for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:04 +0000 Message-Id: <20181112170816.500-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/16] hw/arm/sysbus-fdt: Only call match_fn callback if the type matches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger Commit af7d64ede0b9 (hw/arm/sysbus-fdt: Allow device matching with DT compatible value) introduced a match_fn callback which gets called for each registered combo to check whether a sysbus device can be dynamically instantiated. However the callback gets called even if the device type does not match the binding combo typename field. This causes an assert when passing "-device ramfb" to the qemu command line as vfio_platform_match() gets called on a non vfio-platform device. To fix this regression, let's change the add_fdt_node() logic so that we first check the type and if the match_fn callback is defined, then we also call it. Binding combos only requesting a type check do not define the match_fn callback. Fixes: af7d64ede0b9 (hw/arm/sysbus-fdt: Allow device matching with DT compatible value) Signed-off-by: Eric Auger Reported-by: Thomas Huth Reviewed-by: Alex Williamson Tested-by: Geert Uytterhoeven Message-id: 20181106184212.29377-1-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/sysbus-fdt.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/arm/sysbus-fdt.c b/hw/arm/sysbus-fdt.c index 0e24c803a1c..ad698d4832c 100644 --- a/hw/arm/sysbus-fdt.c +++ b/hw/arm/sysbus-fdt.c @@ -449,7 +449,7 @@ static bool type_match(SysBusDevice *sbdev, const BindingEntry *entry) return !strcmp(object_get_typename(OBJECT(sbdev)), entry->typename); } -#define TYPE_BINDING(type, add_fn) {(type), NULL, (add_fn), type_match} +#define TYPE_BINDING(type, add_fn) {(type), NULL, (add_fn), NULL} /* list of supported dynamic sysbus bindings */ static const BindingEntry bindings[] = { @@ -481,10 +481,12 @@ static void add_fdt_node(SysBusDevice *sbdev, void *opaque) for (i = 0; i < ARRAY_SIZE(bindings); i++) { const BindingEntry *iter = &bindings[i]; - if (iter->match_fn(sbdev, iter)) { - ret = iter->add_fn(sbdev, opaque); - assert(!ret); - return; + if (type_match(sbdev, iter)) { + if (!iter->match_fn || iter->match_fn(sbdev, iter)) { + ret = iter->add_fn(sbdev, opaque); + assert(!ret); + return; + } } } error_report("Device %s can not be dynamically instantiated", From patchwork Mon Nov 12 17:08:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyVb1pFCz9s3Z for ; Tue, 13 Nov 2018 04:31:50 +1100 (AEDT) Received: from localhost ([::1]:49892 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG3v-0006Fi-Si for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:31:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60703) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFi6-0004Iq-Kv for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFi5-0000qr-Q5 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:14 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFi5-0008MG-G2 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:13 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhI-0005rl-Vt for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:05 +0000 Message-Id: <20181112170816.500-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/16] target/arm: Fix typo in tlbi_aa64_vmalle1_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This would cause an infinite recursion or loop. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20181110121711.15257-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 851ea9aa977..d167bc5deff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3155,7 +3155,7 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = ENV_GET_CPU(env); if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1_write(env, NULL, value); + tlbi_aa64_vmalle1is_write(env, NULL, value); return; } From patchwork Mon Nov 12 17:08:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyCb2tBVz9s3q for ; Tue, 13 Nov 2018 04:18:51 +1100 (AEDT) Received: from localhost ([::1]:49813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFrM-0003pj-U9 for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:18:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhv-00048t-1Q for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhu-0000gz-99 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:03 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFht-0008MG-Vh for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:02 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhK-0005rz-Kl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:06 +0000 Message-Id: <20181112170816.500-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/16] target/arm64: properly handle DBGVR RESS bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée This only fails with some (broken) versions of gdb but we should treat the top bits of DBGBVR as RESS. Properly sign extend QEMU's reference copy of dbgbvr and also update the register descriptions in the comment. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac57..6351a54b287 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -103,7 +103,7 @@ static void kvm_arm_init_debug(CPUState *cs) * capable of fancier matching but that will require exposing that * fanciness to GDB's interface * - * D7.3.2 DBGBCR_EL1, Debug Breakpoint Control Registers + * DBGBCR_EL1, Debug Breakpoint Control Registers * * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0 * +------+------+-------+-----+----+------+-----+------+-----+---+ @@ -115,12 +115,25 @@ static void kvm_arm_init_debug(CPUState *cs) * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12) * BAS: Byte Address Select (RES1 for AArch64) * E: Enable bit + * + * DBGBVR_EL1, Debug Breakpoint Value Registers + * + * 63 53 52 49 48 2 1 0 + * +------+-----------+----------+-----+ + * | RESS | VA[52:49] | VA[48:2] | 0 0 | + * +------+-----------+----------+-----+ + * + * Depending on the addressing mode bits the top bits of the register + * are a sign extension of the highest applicable VA bit. Some + * versions of GDB don't do it correctly so we ensure they are correct + * here so future PC comparisons will work properly. */ + static int insert_hw_breakpoint(target_ulong addr) { HWBreakpoint brk = { .bcr = 0x1, /* BCR E=1, enable */ - .bvr = addr + .bvr = sextract64(addr, 0, 53) }; if (cur_hw_bps >= max_hw_bps) { From patchwork Mon Nov 12 17:08:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyR94pRrz9s3Z for ; Tue, 13 Nov 2018 04:28:53 +1100 (AEDT) Received: from localhost ([::1]:49874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG14-0003pe-Um for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:28:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFht-00046J-Rx for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFht-0000ge-92 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:01 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFht-0008MG-1V for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:01 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhL-0005sD-H1 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:07 +0000 Message-Id: <20181112170816.500-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/16] target/arm64: hold BQL when calling do_interrupt() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Fix the assertion failure when running interrupts. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6351a54b287..c39150e5e18 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1000,7 +1000,9 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) cs->exception_index = EXCP_BKPT; env->exception.syndrome = debug_exit->hsr; env->exception.vaddress = debug_exit->far; + qemu_mutex_lock_iothread(); cc->do_interrupt(cs); + qemu_mutex_unlock_iothread(); return false; } From patchwork Mon Nov 12 17:08:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyW035wNz9s3Z for ; Tue, 13 Nov 2018 04:32:12 +1100 (AEDT) Received: from localhost ([::1]:49894 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG4H-0006Y2-Vd for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:32:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60616) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhs-00045B-Va for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhs-0000gI-9r for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:00 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhs-0008MG-2e for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:00 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhM-0005sR-DH for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:08 +0000 Message-Id: <20181112170816.500-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/16] target/arm64: kvm debug set target_el when passing exception to guest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée When we are debugging the guest all exceptions come our way but might be for the guest's own debug exceptions. We use the ->do_interrupt() infrastructure to inject the exception into the guest. However, we are missing a full setup of the exception structure, causing an assert later down the line. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index c39150e5e18..46fbe6d8ff6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1000,6 +1000,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) cs->exception_index = EXCP_BKPT; env->exception.syndrome = debug_exit->hsr; env->exception.vaddress = debug_exit->far; + env->exception.target_el = 1; qemu_mutex_lock_iothread(); cc->do_interrupt(cs); qemu_mutex_unlock_iothread(); From patchwork Mon Nov 12 17:08:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996573 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyNM62mTz9s3Z for ; Tue, 13 Nov 2018 04:26:27 +1100 (AEDT) Received: from localhost ([::1]:49865 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFyi-0001NM-Gz for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:26:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhs-00043J-1m for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhr-0000fu-AM for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhr-0008MG-2O for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhN-0005sf-9Y for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:09 +0000 Message-Id: <20181112170816.500-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/16] tests/guest-debug: fix scoping of failcount X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée You should declare you are using a global version of a variable before you attempt to modify it in a function. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- tests/guest-debug/test-gdbstub.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/guest-debug/test-gdbstub.py b/tests/guest-debug/test-gdbstub.py index 0e4ac014260..c7e3986a249 100644 --- a/tests/guest-debug/test-gdbstub.py +++ b/tests/guest-debug/test-gdbstub.py @@ -16,6 +16,7 @@ def report(cond, msg): print ("PASS: %s" % (msg)) else: print ("FAIL: %s" % (msg)) + global failcount failcount += 1 From patchwork Mon Nov 12 17:08:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyRR5H0Nz9s3Z for ; Tue, 13 Nov 2018 04:29:07 +1100 (AEDT) Received: from localhost ([::1]:49876 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG1I-00044g-K5 for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:29:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhr-00042F-26 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhq-0000fN-AZ for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhp-0008MG-UD for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:58 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhO-0005st-6B for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:10 +0000 Message-Id: <20181112170816.500-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/16] arm: use symbolic MDCR_TDE in arm_debug_target_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée We already have this symbol defined so lets use it. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b5eff79f73b..1efff21a18d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2743,7 +2743,7 @@ static inline int arm_debug_target_el(CPUARMState *env) if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & (1 << 8); + env->cp15.mdcr_el2 & MDCR_TDE; } if (route_to_el2) { From patchwork Mon Nov 12 17:08:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyNd3VWrz9s3Z for ; Tue, 13 Nov 2018 04:26:40 +1100 (AEDT) Received: from localhost ([::1]:49866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFyv-0001ZY-RH for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:26:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhq-00041G-9k for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhp-0000ew-8E for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:58 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFho-0008MG-Sl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:57 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhP-0005t7-2b for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:11 +0000 Message-Id: <20181112170816.500-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/16] arm: fix aa64_generate_debug_exceptions to work with EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée The test was incomplete and incorrectly caused debug exceptions to be generated when returning to EL2 after a failed attempt to single-step an EL1 instruction. Fix this while cleaning up the function a little. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1efff21a18d..814ff69bc22 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2764,23 +2764,35 @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; } +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ static inline bool aa64_generate_debug_exceptions(CPUARMState *env) { - if (arm_is_secure(env)) { - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 - || arm_current_el(env) == 3) { - return false; - } + int cur_el = arm_current_el(env); + int debug_el; + + if (cur_el == 3) { + return false; } - if (arm_current_el(env) == arm_debug_target_el(env)) { - if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) - || (env->daif & PSTATE_D)) { - return false; - } + /* MDCR_EL3.SDD disables debug events from Secure state */ + if (arm_is_secure_below_el3(env) + && extract32(env->cp15.mdcr_el3, 16, 1)) { + return false; } - return true; + + /* + * Same EL to same EL debug exceptions need MDSCR_KDE enabled + * while not masking the (D)ebug bit in DAIF. + */ + debug_el = arm_debug_target_el(env); + + if (cur_el == debug_el) { + return extract32(env->cp15.mdscr_el1, 13, 1) + && !(env->daif & PSTATE_D); + } + + /* Otherwise the debug target needs to be a higher EL */ + return debug_el > cur_el; } static inline bool aa32_generate_debug_exceptions(CPUARMState *env) @@ -2833,9 +2845,6 @@ static inline bool aa32_generate_debug_exceptions(CPUARMState *env) * since the pseudocode has it at all callsites except for the one in * CheckSoftwareStep(), where it is elided because both branches would * always return the same value. - * - * Parts of the pseudocode relating to EL2 and EL3 are omitted because we - * don't yet implement those exception levels or their associated trap bits. */ static inline bool arm_generate_debug_exceptions(CPUARMState *env) { From patchwork Mon Nov 12 17:08:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyJK0Yjlz9s3Z for ; Tue, 13 Nov 2018 04:22:57 +1100 (AEDT) Received: from localhost ([::1]:49841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFvK-00079G-IS for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:22:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhp-00040C-Al for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFho-0000e4-4w for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:57 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhn-0008MG-S4 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhP-0005tL-Vc for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:12 +0000 Message-Id: <20181112170816.500-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/16] Revert "target/arm: Implement HCR.VI and VF" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This reverts commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f. The implementation of HCR.VI and VF in that commit is not correct -- they do not track the overall "is there a pending VIRQ or VFIQ" status, but whether there is a pending interrupt due to "this mechanism", ie the hypervisor having set the VI/VF bits. The overall pending state for VIRQ and VFIQ is effectively the logical OR of the inbound lines from the GIC with the VI and VF bits. Commit 8a0fc3a29fc231 would result in pending VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR. As a preliminary to implementing the HCR.VI/VF feature properly, revert the broken one entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20181109134731.11605-2-peter.maydell@linaro.org --- target/arm/helper.c | 47 ++++----------------------------------------- 1 file changed, 4 insertions(+), 43 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d167bc5deff..3c0c485a3a3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3931,7 +3931,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = ENV_GET_CPU(env); uint64_t valid_mask = HCR_MASK; if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -3950,28 +3949,6 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &= valid_mask; - /* - * VI and VF are kept in cs->interrupt_request. Modifying that - * requires that we have the iothread lock, which is done by - * marking the reginfo structs as ARM_CP_IO. - * Note that if a write to HCR pends a VIRQ or VFIQ it is never - * possible for it to be taken immediately, because VIRQ and - * VFIQ are masked unless running at EL0 or EL1, and HCR - * can only be written at EL2. - */ - g_assert(qemu_mutex_iothread_locked()); - if (value & HCR_VI) { - cs->interrupt_request |= CPU_INTERRUPT_VIRQ; - } else { - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - } - if (value & HCR_VF) { - cs->interrupt_request |= CPU_INTERRUPT_VFIQ; - } else { - cs->interrupt_request &= ~CPU_INTERRUPT_VFIQ; - } - value &= ~(HCR_VI | HCR_VF); - /* These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups @@ -3999,32 +3976,16 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } -static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* The VI and VF bits live in cs->interrupt_request */ - uint64_t ret = env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF); - CPUState *cs = ENV_GET_CPU(env); - - if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { - ret |= HCR_VI; - } - if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { - ret |= HCR_VF; - } - return ret; -} - static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write, .readfn = hcr_read }, + .writefn = hcr_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_writelow, .readfn = hcr_read }, + .writefn = hcr_writelow }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, @@ -4261,7 +4222,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { static const ARMCPRegInfo el2_v8_cp_reginfo[] = { { .name = "HCR2", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), From patchwork Mon Nov 12 17:08:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyKH3BZfz9s3Z for ; Tue, 13 Nov 2018 04:23:47 +1100 (AEDT) Received: from localhost ([::1]:49847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFw8-0007hw-OO for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:23:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFho-0003zP-K5 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhn-0000dH-4l for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhm-0008MG-R8 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:55 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhQ-0005tZ-SI for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:32 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:13 +0000 Message-Id: <20181112170816.500-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/16] target/arm: Track the state of our irq lines from the GIC explicitly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently we track the state of the four irq lines from the GIC only via the cs->interrupt_request or KVM irq state. That means that we assume that an interrupt is asserted if and only if the external line is set. This assumption is incorrect for VIRQ and VFIQ, because the HCR_EL2.{VI,VF} bits allow assertion of VIRQ and VFIQ separately from the state of the external line. To handle this, start tracking the state of the external lines explicitly in a CPU state struct field, as is common practice for devices. The complicated part of this is dealing with inbound migration from an older QEMU which didn't have this state. We assume in that case that the older QEMU did not implement the HCR_EL2.{VI,VF} bits as generating interrupts, and so the line state matches the current state in cs->interrupt_request. (This is not quite true between commit 8a0fc3a29fc2315325400c7 and its revert, but that commit is broken and never made it into any released QEMU version.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20181109134731.11605-3-peter.maydell@linaro.org --- target/arm/cpu.h | 3 +++ target/arm/cpu.c | 16 ++++++++++++++ target/arm/machine.c | 51 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 814ff69bc22..2a73fed9a01 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -538,6 +538,9 @@ typedef struct CPUARMState { uint64_t esr; } serror; + /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ + uint32_t irq_line_state; + /* Thumb-2 EE state. */ uint32_t teecr; uint32_t teehbr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 784a4c2dfcc..45c16ae90ba 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -449,6 +449,12 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ }; + if (level) { + env->irq_line_state |= mask[irq]; + } else { + env->irq_line_state &= ~mask[irq]; + } + switch (irq) { case ARM_CPU_VIRQ: case ARM_CPU_VFIQ: @@ -473,17 +479,27 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) ARMCPU *cpu = opaque; CPUState *cs = CPU(cpu); int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; + uint32_t linestate_bit; switch (irq) { case ARM_CPU_IRQ: kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; + linestate_bit = CPU_INTERRUPT_HARD; break; case ARM_CPU_FIQ: kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; + linestate_bit = CPU_INTERRUPT_FIQ; break; default: g_assert_not_reached(); } + + if (level) { + env->irq_line_state |= linestate_bit; + } else { + env->irq_line_state &= ~linestate_bit; + } + kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d1..2033816a64e 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -192,6 +192,22 @@ static const VMStateDescription vmstate_serror = { } }; +static bool irq_line_state_needed(void *opaque) +{ + return true; +} + +static const VMStateDescription vmstate_irq_line_state = { + .name = "cpu/irq-line-state", + .version_id = 1, + .minimum_version_id = 1, + .needed = irq_line_state_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.irq_line_state, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static bool m_needed(void *opaque) { ARMCPU *cpu = opaque; @@ -625,11 +641,44 @@ static int cpu_pre_save(void *opaque) return 0; } +static int cpu_pre_load(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + /* + * Pre-initialize irq_line_state to a value that's never valid as + * real data, so cpu_post_load() can tell whether we've seen the + * irq-line-state subsection in the incoming migration state. + */ + env->irq_line_state = UINT32_MAX; + + return 0; +} + static int cpu_post_load(void *opaque, int version_id) { ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; int i, v; + /* + * Handle migration compatibility from old QEMU which didn't + * send the irq-line-state subsection. A QEMU without it did not + * implement the HCR_EL2.{VI,VF} bits as generating interrupts, + * so for TCG the line state matches the bits set in cs->interrupt_request. + * For KVM the line state is not stored in cs->interrupt_request + * and so this will leave irq_line_state as 0, but this is OK because + * we only need to care about it for TCG. + */ + if (env->irq_line_state == UINT32_MAX) { + CPUState *cs = CPU(cpu); + + env->irq_line_state = cs->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ | + CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); + } + /* Update the values list from the incoming migration data. * Anything in the incoming data which we don't know about is * a migration failure; anything we know about but the incoming @@ -680,6 +729,7 @@ const VMStateDescription vmstate_arm_cpu = { .version_id = 22, .minimum_version_id = 22, .pre_save = cpu_pre_save, + .pre_load = cpu_pre_load, .post_load = cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), @@ -747,6 +797,7 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_sve, #endif &vmstate_serror, + &vmstate_irq_line_state, NULL } }; From patchwork Mon Nov 12 17:08:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyDp1vhVz9s4s for ; Tue, 13 Nov 2018 04:19:54 +1100 (AEDT) Received: from localhost ([::1]:49818 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFsN-0004Ww-Ol for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:19:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhn-0003xw-6A for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhm-0000cY-3N for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:55 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhl-0008MG-Qg for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:54 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhR-0005tn-Of for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:33 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:14 +0000 Message-Id: <20181112170816.500-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/16] target/arm: Correctly implement handling of HCR_EL2.{VI, VF} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In commit 8a0fc3a29fc2315325400 we tried to implement HCR_EL2.{VI,VF}, but we got it wrong and had to revert it. In that commit we implemented them as simply tracking whether there is a pending virtual IRQ or virtual FIQ. This is not correct -- these bits cause a software-generated VIRQ/VFIQ, which is distinct from whether there is a hardware-generated VIRQ/VFIQ caused by the external interrupt controller. So we need to track separately the HCR_EL2 bit state and the external virq/vfiq line state, and OR the two together to get the actual pending VIRQ/VFIQ state. Fixes: 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181109134731.11605-4-peter.maydell@linaro.org --- target/arm/internals.h | 18 ++++++++++++++++ target/arm/cpu.c | 48 +++++++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 20 ++++++++++++++++-- 3 files changed, 83 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c2bb2deebd..a32d359dd03 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -871,4 +871,22 @@ static inline const char *aarch32_mode_name(uint32_t psr) return cpu_mode_names[psr & 0xf]; } +/** + * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request + * + * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following + * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. + * Must be called with the iothread lock held. + */ +void arm_cpu_update_virq(ARMCPU *cpu); + +/** + * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request + * + * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following + * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. + * Must be called with the iothread lock held. + */ +void arm_cpu_update_vfiq(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45c16ae90ba..6fbea4dc88c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -436,6 +436,48 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #endif +void arm_cpu_update_virq(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VIRQ, which is the logical OR of + * the HCR_EL2.VI bit and the input line level from the GIC. + */ + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + + bool new_state = (env->cp15.hcr_el2 & HCR_VI) || + (env->irq_line_state & CPU_INTERRUPT_VIRQ); + + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); + } + } +} + +void arm_cpu_update_vfiq(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VFIQ, which is the logical OR of + * the HCR_EL2.VF bit and the input line level from the GIC. + */ + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + + bool new_state = (env->cp15.hcr_el2 & HCR_VF) || + (env->irq_line_state & CPU_INTERRUPT_VFIQ); + + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { @@ -457,9 +499,13 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) switch (irq) { case ARM_CPU_VIRQ: + assert(arm_feature(env, ARM_FEATURE_EL2)); + arm_cpu_update_virq(cpu); + break; case ARM_CPU_VFIQ: assert(arm_feature(env, ARM_FEATURE_EL2)); - /* fall through */ + arm_cpu_update_vfiq(cpu); + break; case ARM_CPU_IRQ: case ARM_CPU_FIQ: if (level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 3c0c485a3a3..0ebe4d1b4ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3958,6 +3958,21 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) tlb_flush(CPU(cpu)); } env->cp15.hcr_el2 = value; + + /* + * Updates to VI and VF require us to update the status of + * virtual interrupts, which are the logical OR of these bits + * and the state of the input lines from the GIC. (This requires + * that we have the iothread lock, which is done by marking the + * reginfo structs as ARM_CP_IO.) + * Note that if a write to HCR pends a VIRQ or VFIQ it is never + * possible for it to be taken immediately, because VIRQ and + * VFIQ are masked unless running at EL0 or EL1, and HCR + * can only be written at EL2. + */ + g_assert(qemu_mutex_iothread_locked()); + arm_cpu_update_virq(cpu); + arm_cpu_update_vfiq(cpu); } static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3978,11 +3993,12 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .writefn = hcr_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .writefn = hcr_writelow }, @@ -4222,7 +4238,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { static const ARMCPRegInfo el2_v8_cp_reginfo[] = { { .name = "HCR2", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), From patchwork Mon Nov 12 17:08:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42tyFr5RXCz9s3Z for ; Tue, 13 Nov 2018 04:20:48 +1100 (AEDT) Received: from localhost ([::1]:49825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFtG-0005Ae-40 for incoming@patchwork.ozlabs.org; Mon, 12 Nov 2018 12:20:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhm-0003xW-Mq for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhl-0000bc-49 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhk-0008MG-Od for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhS-0005u1-L4 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:34 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:15 +0000 Message-Id: <20181112170816.500-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/16] target/arm: Hyp mode R14 is shared with User and System X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Hyp mode is an exception to the general rule that each AArch32 mode has its own r13, r14 and SPSR -- it has a banked r13 and SPSR but shares its r14 with User and System mode. We were incorrectly implementing it as banked, which meant that on entry to Hyp mode r14 was 0 rather than the USR/SYS r14. We provide a new function r14_bank_number() which is like the existing bank_number() but provides the index into env->banked_r14[]; bank_number() provides the index to use for env->banked_r13[] and env->banked_cpsr[]. All the points in the code that were using bank_number() to index into env->banked_r14[] are updated for consintency: * switch_mode() -- this is the only place where we fix an actual bug * aarch64_sync_32_to_64() and aarch64_sync_64_to_32(): no behavioural change as we already special-cased Hyp R14 * kvm32.c: no behavioural change since the guest can't ever be in Hyp mode, but conceptually the right thing to do * msr_banked()/mrs_banked(): we can never get to the case that accesses banked_r14[] with tgtmode == ARM_CPU_MODE_HYP, so no behavioural change Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 20181109173553.22341-2-peter.maydell@linaro.org --- target/arm/internals.h | 16 ++++++++++++++++ target/arm/helper.c | 29 +++++++++++++++-------------- target/arm/kvm32.c | 4 ++-- target/arm/op_helper.c | 4 ++-- 4 files changed, 35 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a32d359dd03..d208b70a64f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -145,6 +145,22 @@ static inline int bank_number(int mode) g_assert_not_reached(); } +/** + * r14_bank_number: Map CPU mode onto register bank for r14 + * + * Given an AArch32 CPU mode, return the index into the saved register + * banks to use for the R14 (LR) in that mode. This is the same as + * bank_number(), except for the special case of Hyp mode, where + * R14 is shared with USR and SYS, unlike its R13 and SPSR. + * This should be used as the index into env->banked_r14[], and + * bank_number() used for the index into env->banked_r13[] and + * env->banked_spsr[]. + */ +static inline int r14_bank_number(int mode) +{ + return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); +} + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ebe4d1b4ad..0da1424f72d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6432,13 +6432,14 @@ static void switch_mode(CPUARMState *env, int mode) i = bank_number(old_mode); env->banked_r13[i] = env->regs[13]; - env->banked_r14[i] = env->regs[14]; env->banked_spsr[i] = env->spsr; i = bank_number(mode); env->regs[13] = env->banked_r13[i]; - env->regs[14] = env->banked_r14[i]; env->spsr = env->banked_spsr[i]; + + env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; + env->regs[14] = env->banked_r14[r14_bank_number(mode)]; } /* Physical Interrupt Target EL Lookup Table @@ -8017,7 +8018,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) if (mode == ARM_CPU_MODE_HYP) { env->xregs[14] = env->regs[14]; } else { - env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; + env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; } } @@ -8031,7 +8032,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[16] = env->regs[14]; env->xregs[17] = env->regs[13]; } else { - env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; + env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; } @@ -8039,7 +8040,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[18] = env->regs[14]; env->xregs[19] = env->regs[13]; } else { - env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; + env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; } @@ -8047,7 +8048,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[20] = env->regs[14]; env->xregs[21] = env->regs[13]; } else { - env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; + env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; } @@ -8055,7 +8056,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[22] = env->regs[14]; env->xregs[23] = env->regs[13]; } else { - env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; + env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; } @@ -8072,7 +8073,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[i] = env->fiq_regs[i - 24]; } env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; - env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; } env->pc = env->regs[15]; @@ -8122,7 +8123,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) if (mode == ARM_CPU_MODE_HYP) { env->regs[14] = env->xregs[14]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; } } @@ -8136,7 +8137,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[16]; env->regs[13] = env->xregs[17]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; } @@ -8144,7 +8145,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[18]; env->regs[13] = env->xregs[19]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; } @@ -8152,7 +8153,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[20]; env->regs[13] = env->xregs[21]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; } @@ -8160,7 +8161,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[22]; env->regs[13] = env->xregs[23]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; } @@ -8177,7 +8178,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->fiq_regs[i - 24] = env->xregs[i]; } env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; - env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; } env->regs[15] = env->pc; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5e..cb3fb73a961 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -318,8 +318,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); } env->banked_r13[bn] = env->regs[13]; - env->banked_r14[bn] = env->regs[14]; env->banked_spsr[bn] = env->spsr; + env->banked_r14[r14_bank_number(mode)] = env->regs[14]; /* Now we can safely copy stuff down to the kernel */ for (i = 0; i < ARRAY_SIZE(regs); i++) { @@ -430,8 +430,8 @@ int kvm_arch_get_registers(CPUState *cs) memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); } env->regs[13] = env->banked_r13[bn]; - env->regs[14] = env->banked_r14[bn]; env->spsr = env->banked_spsr[bn]; + env->regs[14] = env->banked_r14[r14_bank_number(mode)]; /* VFP registers */ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 90741f6331d..eb6fb82fb81 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -694,7 +694,7 @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, env->banked_r13[bank_number(tgtmode)] = value; break; case 14: - env->banked_r14[bank_number(tgtmode)] = value; + env->banked_r14[r14_bank_number(tgtmode)] = value; break; case 8 ... 12: switch (tgtmode) { @@ -725,7 +725,7 @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) case 13: return env->banked_r13[bank_number(tgtmode)]; case 14: - return env->banked_r14[bank_number(tgtmode)]; + return env->banked_r14[r14_bank_number(tgtmode)]; case 8 ... 12: switch (tgtmode) { case ARM_CPU_MODE_USR: From patchwork Mon Nov 12 17:08:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 996559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42ty7v6DGrz9s3Z for ; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/16] target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Cortex-A15 and Cortex-A7 both have EL2; now we've implemented it properly we can enable the feature bit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-id: 20181109173553.22341-3-peter.maydell@linaro.org --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6fbea4dc88c..f4efda0a00c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1649,6 +1649,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; @@ -1695,6 +1696,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1;