From patchwork Wed Nov 7 09:14:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 994151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489217-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="T0nbnofB"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nIRbZKXu"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42qgj23F9Bz9sCm for ; Wed, 7 Nov 2018 20:14:30 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=rPQyceI60B0IayC 59AQTvDh6V6jh9XbN+H+fcbOyRErKSCc4BguW9ZPl1Y3jqtBtTijTrAJyOCZ65oY 4fvPYZOE0/bRG5hpwPmbEAq57aGhC2fjW8V+V4NACEA1DE3LeMcDUYOYkmA4DcsJ ogDZM+dEEwO7kwbkjvCn96Jvr5k4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; s=default; bh=2xzDQut9Lu+0WDZ8OUOXP +txaKs=; b=T0nbnofB4eO3UwKWVYM/OrlsTtbnt1e6uqmwaUlEciJWJNWcxzF3/ E2SC6BV+bZ0CoGYYMwr+aTvqBvL6xjlT4QBmDEw6Kha8q47Yh2vtXpfJxgweVHrs PGi7fZUHNyzevDFmosOAw2/D0j3N0xWcbabehiA+DeMhwYnKR8Cz+4= Received: (qmail 27824 invoked by alias); 7 Nov 2018 09:14:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 27814 invoked by uid 89); 7 Nov 2018 09:14:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=9217 X-HELO: mail-ot1-f51.google.com Received: from mail-ot1-f51.google.com (HELO mail-ot1-f51.google.com) (209.85.210.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:14:21 +0000 Received: by mail-ot1-f51.google.com with SMTP id n46so9916061otb.9 for ; Wed, 07 Nov 2018 01:14:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QgM90SIilK9iZR4xqtFQOi13si4iDfVdFAjF/JdliK0=; b=nIRbZKXuO34P9V4XPbWu7M+mgQyAbAPpPhdn4fUylXO9xqj+mK+b6CarGCbU+qxuU2 FX/X2nSOkqHRhgAdIIoFje4cD91lxPgBUZ7oAEN8kguxAAAOx73IzRBL0ukzGmFEbwvV f9DNPf0tN4e4haBl7KZXKXVegm3YxU6M3XiAXma4tEc3oCwOx8CjpwFpeQE5FGUbQHUP AyRuZUuGfmRP4/i8j/KDqDsv90WRd1x8Wf6IDrSNp7kG8y5VFTfbichj6bDVwcisHVKv 5SmRDnp8NYPQi0MKYAZvXlNkY+nciLRbhCKxlWSKyD+2QRspKk+zLICHxQPLpK3LBA5N 86vw== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:14:07 +0800 Message-ID: Subject: [PATCH v4 2/6, Committed] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From b1dfcb228934e3cde90f408056192ed7faff4417 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Tue, 6 Nov 2018 17:04:36 +0800 Subject: [PATCH 2/6] Add support for Loongson EXT instructions. gcc/ * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_ext. (MIPS_ASE_LOONGSON_EXT_SPEC): New. (BASE_DRIVER_SELF_SPECS): march=loongson3a implies -mloongson-ext. (ASM_SPEC): Add mloongson-ext and mno-loongson-ext. * config/mips/mips.md (mul3, mul3_mul3_nohilo, div3, mod3, prefetch): Use TARGET_LOONGSON_EXT instead of TARGET_LOONGSON_3A. * config/mips/mips.opt (-mloongson-ext): Add option. * gcc/doc/invoke.texi (-mloongson-ext): Document. gcc/testsuite/ * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext option. (mips-dg-options): Add mips_option_dependency options "-mmicromips" vs "-mno-loongson-ext", --- gcc/config/mips/mips.h | 14 +++++++++++++- gcc/config/mips/mips.md | 16 ++++++++-------- gcc/config/mips/mips.opt | 4 ++++ gcc/doc/invoke.texi | 7 +++++++ gcc/testsuite/gcc.target/mips/mips.exp | 2 ++ 5 files changed, 34 insertions(+), 9 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 27c0222ee46..7237c8da8ac 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -596,6 +596,12 @@ struct mips_cpu_info { builtin_define ("__mips_loongson_mmi"); \ } \ \ + /* Whether Loongson EXT modes are enabled. */ \ + if (TARGET_LOONGSON_EXT) \ + { \ + builtin_define ("__mips_loongson_ext"); \ + } \ + \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ builtin_define ("__OCTEON__"); \ @@ -881,7 +887,8 @@ struct mips_cpu_info { #define BASE_DRIVER_SELF_SPECS \ MIPS_ISA_NAN2008_SPEC, \ MIPS_ASE_DSP_SPEC, \ - MIPS_ASE_LOONGSON_MMI_SPEC + MIPS_ASE_LOONGSON_MMI_SPEC, \ + MIPS_ASE_LOONGSON_EXT_SPEC #define MIPS_ASE_DSP_SPEC \ "%{!mno-dsp: \ @@ -893,6 +900,10 @@ struct mips_cpu_info { "%{!mno-loongson-mmi: \ %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}" +#define MIPS_ASE_LOONGSON_EXT_SPEC \ + "%{!mno-loongson-ext: \ + %{march=loongson3a: -mloongson-ext}}" + #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ BASE_DRIVER_SELF_SPECS @@ -1367,6 +1378,7 @@ struct mips_cpu_info { %{mginv} %{mno-ginv} \ %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ +%{mloongson-ext} %{mno-loongson-ext} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index a88c1c53134..4b7a627b7a6 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1599,7 +1599,7 @@ { rtx lo; - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL) emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1], operands[2])); else if (ISA_HAS_MUL3) @@ -1622,11 +1622,11 @@ [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL" { if (TARGET_LOONGSON_2EF) return "multu.g\t%0,%1,%2"; - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return "gsmultu\t%0,%1,%2"; else return "mul\t%0,%1,%2"; @@ -3016,11 +3016,11 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV" { if (TARGET_LOONGSON_2EF) return mips_output_division ("div.g\t%0,%1,%2", operands); - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return mips_output_division ("gsdiv\t%0,%1,%2", operands); else return mips_output_division ("div\t%0,%1,%2", operands); @@ -3032,11 +3032,11 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV" { if (TARGET_LOONGSON_2EF) return mips_output_division ("mod.g\t%0,%1,%2", operands); - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return mips_output_division ("gsmod\t%0,%1,%2", operands); else return mips_output_division ("mod\t%0,%1,%2", operands); @@ -7136,7 +7136,7 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) { /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ if (TARGET_64BIT) diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 6767c47fa65..a8fe8db3c66 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -463,3 +463,7 @@ Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) mloongson-mmi Target Report Mask(LOONGSON_MMI) Use Loongson MultiMedia extensions Instructions (MMI) instructions. + +mloongson-ext +Target Report Mask(LOONGSON_EXT) +Use Loongson EXTension (EXT) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ba98b489fad..ae92323eb06 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -921,6 +921,7 @@ Objective-C and Objective-C++ Dialects}. -mmicromips -mno-micromips @gol -mmsa -mno-msa @gol -mloongson-mmi -mno-loongson-mmi @gol +-mloongson-ext -mno-loongson-ext @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21294,6 +21295,12 @@ Use (do not use) the MIPS Global INValidate (GINV) instructions. @opindex mno-loongson-mmi Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). +@item -mloongson-ext +@itemx -mno-loongson-ext +@opindex mloongson-ext +@opindex mno-loongson-ext +Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 9e447b554f3..ceb86cc0276 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -297,6 +297,7 @@ foreach option { odd-spreg msa loongson-mmi + loongson-ext } { lappend mips_option_groups $option "-m(no-|)$option" } @@ -1055,6 +1056,7 @@ proc mips-dg-options { args } { mips_option_dependency options "-mips16" "-mno-loongson-mmi" mips_option_dependency options "-mmicromips" "-mno-loongson-mmi" mips_option_dependency options "-msoft-float" "-mno-loongson-mmi" + mips_option_dependency options "-mmicromips" "-mno-loongson-ext" # Work out information about the current ABI. set abi_test_option_p [mips_test_option_p options abi] -- 2.18.0 From patchwork Wed Nov 7 09:14:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 994152 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=t0 X-HELO: mail-ot1-f44.google.com Received: from mail-ot1-f44.google.com (HELO mail-ot1-f44.google.com) (209.85.210.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:15:22 +0000 Received: by mail-ot1-f44.google.com with SMTP id z33so14035857otz.11 for ; Wed, 07 Nov 2018 01:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/jTxF9jIJjnPhmPdmScuuJiB+0IW9QJHoPUpxetMC+8=; b=mGSRiJS5nDcNJAp/oSyxIAnlf+bQ+PbGKkFL0nFBfp0i+rjBifDtlCffsmf+/Z2Q/4 2w9LZbB5oDJ9aM9TcytolGUxHDLFaob55clSv/8OShm0Bq+NmrtqCHJOYEXsU2vdblM9 bPYPQroSh2My5xH53P0BCqDHttTgDnYW9YK9xkRtZHQ1rxOvNCe5GjRDkkH4IHqAbwBf WszCBqog5sCOqAJQJzOFtR8Ly297E7JS5ho4/ZTYQ7JXdSgPKQxiS7fu2oi3QZ68xg2U R3crgHlqR+BExmM67hyWdlSeYqFOKaawoeg/At6gRndDr0jg0Zb6PWhSs0FKI8vQ8eRs 47vQ== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:14:53 +0800 Message-ID: Subject: [PATCH v4 3/6, Committed] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From 73a4aac5034307cf7369bb70fa407709502fffbf Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 11:55:48 +0800 Subject: [PATCH 3/6] Add support for Loongson EXT2 instructions. gcc/ * config/mips/mips-protos.h (mips_loongson_ext2_prefetch_cookie): New prototype. * config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New. (mips_option_override): Enable TARGET_LOONGSON_EXT when TARGET_LOONGSON_EXT2 is true. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_ext2, __mips_loongson_ext_rev=2. (ISA_HAS_CTZ_CTO): New, true if TARGET_LOONGSON_EXT2. (ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2. (ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2. (define_insn "ctz2"): New insn pattern. (define_insn "prefetch"): Include TARGET_LOONGSON_EXT2. (define_insn "prefetch_indexed_"): Include TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2. * config/mips/mips.opt (-mloongson-ext2): Add option. * gcc/doc/invoke.texi (-mloongson-ext2): Document. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: New test. * gcc.target/mips/loongson-dctz.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext2 option. --- gcc/config/mips/mips-protos.h | 1 + gcc/config/mips/mips.c | 28 +++++++++++ gcc/config/mips/mips.h | 15 +++++- gcc/config/mips/mips.md | 47 +++++++++++++++++-- gcc/config/mips/mips.opt | 4 ++ gcc/doc/invoke.texi | 7 +++ gcc/testsuite/gcc.target/mips/loongson-ctz.c | 11 +++++ gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 +++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 9 files changed, 120 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 099120db7b4..7cde2424016 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -323,6 +323,7 @@ extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *); extern bool mips_store_data_bypass_p (rtx_insn *, rtx_insn *); extern int mips_dspalu_bypass_p (rtx, rtx); extern rtx mips_prefetch_cookie (rtx, rtx); +extern rtx mips_loongson_ext2_prefetch_cookie (rtx, rtx); extern const char *current_section_name (void); extern unsigned int current_section_flags (void); diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b579c3c3a2a..1c2075044d0 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -15142,6 +15142,22 @@ mips_prefetch_cookie (rtx write, rtx locality) /* store_retained / load_retained. */ return GEN_INT (INTVAL (write) + 6); } + +/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1 + (prefetch for store), other hint just scale to hint = 0 and hint = 1. */ + +rtx +mips_loongson_ext2_prefetch_cookie (rtx write, rtx locality) +{ + /* store. */ + if (INTVAL (write) == 1) + return GEN_INT (INTVAL (write)); + + /* load. */ + if (INTVAL (write) == 0) + return GEN_INT (INTVAL (write)); +} + /* Flags that indicate when a built-in function is available. @@ -20171,6 +20187,18 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); + /* If TARGET_LOONGSON_EXT2, enable TARGET_LOONGSON_EXT. */ + if (TARGET_LOONGSON_EXT2) + { + /* Make sure that when TARGET_LOONGSON_EXT2 is true, TARGET_LOONGSON_EXT + is true. If a user explicitly says -mloongson-ext2 -mno-loongson-ext + then that is an error. */ + if (!TARGET_LOONGSON_EXT + && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0)) + error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>"); + target_flags |= MASK_LOONGSON_EXT; + } + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7237c8da8ac..beeb4bcf20d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -600,6 +600,13 @@ struct mips_cpu_info { if (TARGET_LOONGSON_EXT) \ { \ builtin_define ("__mips_loongson_ext"); \ + if (TARGET_LOONGSON_EXT2) \ + { \ + builtin_define ("__mips_loongson_ext2"); \ + builtin_define ("__mips_loongson_ext_rev=2"); \ + } \ + else \ + builtin_define ("__mips_loongson_ext_rev=1"); \ } \ \ /* Historical Octeon macro. */ \ @@ -1134,6 +1141,9 @@ struct mips_cpu_info { /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) +/* ISA has count tailing zeroes/ones instruction. */ +#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) + /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ @@ -1195,7 +1205,9 @@ struct mips_cpu_info { 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ISA_HAS_FP4 +#define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \ + || TARGET_LOONGSON_EXT \ + || TARGET_LOONGSON_EXT2) /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d @@ -1379,6 +1391,7 @@ struct mips_cpu_info { %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ %{mloongson-ext} %{mno-loongson-ext} \ +%{mloongson-ext2} %{mno-loongson-ext2} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4b7a627b7a6..8358218d8ac 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3146,6 +3146,23 @@ [(set_attr "type" "clz") (set_attr "mode" "")]) +;; +;; ................... +;; +;; Count tailing zeroes. +;; +;; ................... +;; + +(define_insn "ctz2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))] + "ISA_HAS_CTZ_CTO" + "ctz\t%0,%1" + [(set_attr "type" "clz") + (set_attr "mode" "")]) + + ;; ;; ................... ;; @@ -7136,13 +7153,20 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2) { - /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ + /* Loongson ext2 implementation pref insnstructions. */ + if (TARGET_LOONGSON_EXT2) + { + operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1], + operands[2]); + return "pref\t%1, %a0"; + } + /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */ if (TARGET_64BIT) - return "ld\t$0,%a0"; + return "ld\t$0,%a0"; else - return "lw\t$0,%a0"; + return "lw\t$0,%a0"; } operands[1] = mips_prefetch_cookie (operands[1], operands[2]); return "pref\t%1,%a0"; @@ -7156,6 +7180,21 @@ (match_operand 3 "const_int_operand" "n"))] "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" { + if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2) + { + /* Loongson ext2 implementation pref insnstructions. */ + if (TARGET_LOONGSON_EXT2) + { + operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2], + operands[3]); + return "prefx\t%2,%1(%0)"; + } + /* Loongson Loongson ext use index load to $0 for prefetching. */ + if (TARGET_64BIT) + return "gsldx\t$0,0(%0,%1)"; + else + return "gslwx\t$0,0(%0,%1)"; + } operands[2] = mips_prefetch_cookie (operands[2], operands[3]); return "prefx\t%2,%1(%0)"; } diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index a8fe8db3c66..c0c8005b025 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -467,3 +467,7 @@ Use Loongson MultiMedia extensions Instructions (MMI) instructions. mloongson-ext Target Report Mask(LOONGSON_EXT) Use Loongson EXTension (EXT) instructions. + +mloongson-ext2 +Target Report Mask(LOONGSON_EXT2) +Use Loongson EXTension R2 (EXT2) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ae92323eb06..d36a15a34ef 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -922,6 +922,7 @@ Objective-C and Objective-C++ Dialects}. -mmsa -mno-msa @gol -mloongson-mmi -mno-loongson-mmi @gol -mloongson-ext -mno-loongson-ext @gol +-mloongson-ext2 -mno-loongson-ext2 @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21301,6 +21302,12 @@ Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). @opindex mno-loongson-ext Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. +@item -mloongson-ext2 +@itemx -mno-loongson-ext2 +@opindex mloongson-ext2 +@opindex mno-loongson-ext2 +Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c new file mode 100644 index 00000000000..8df66a00dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned int foo(unsigned int x) +{ + return __builtin_ctz (x); +} + +/* { dg-final { scan-assembler "ctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c new file mode 100644 index 00000000000..8c47433459f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned long long foo(unsigned long long x) +{ + return __builtin_ctzl (x); +} + +/* { dg-final { scan-assembler "dctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index ceb86cc0276..e70d416d0dd 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -298,6 +298,7 @@ foreach option { msa loongson-mmi loongson-ext + loongson-ext2 } { lappend mips_option_groups $option "-m(no-|)$option" } -- 2.18.0 From patchwork Wed Nov 7 09:16:10 2018 Content-Type: text/plain; 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bh=4YrBXh+47jIXz118hJe/d3y2lAqT48i9NeplzVRHqC4=; b=ax+1s7YQeOmW1czsiYNpvIwcSClU+mfrhIguwfbPRiwm8PwSESAjQPpf7+ZsTkKAC9 DETfoqPNHWZtsu7d1WzhIVDvL2PT78jo7ba4z2MA4nW8/V3BJdu1uaHeqSUEwKgnPsqE w2VUTCuHAZV3v43ZhhtZ3FK9pW+qoBnBeZr8qFNgPfIYorNKk21UhzSU0BOu5KtDFxqa KLE4/KU7sCU3GKbKhVUj8TC+AaAaCqdVPQabtO9bM8Ur2y0eu0UY6+aL5QdFSXhB5yD1 ff/iqaJJ4eqRGekIOMes90UpfQjqhetVun1z4qoUTaEOfN33dW4AVSi7H5zFjyKEXRat rUwA== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:16:10 +0800 Message-ID: Subject: [PATCH v4 4/6, Committed] [MIPS] Add Loongson 3A1000 processor support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From ef10d77f03e693299611e6b4eee2ae6375a5841d Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Tue, 6 Nov 2018 21:12:46 +0800 Subject: [PATCH 4/6] Add support for Loongson 3A1000 processor. gcc/ * config/mips/loongson3a.md: Rename to ... * config/mips/gs464.md: ... here. * config/mips/mips-cpus.def: Define gs464; Add loongson3a as an alias of gs464 processor. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464 instead of PROCESSOR_LOONGSON_3A. (mips_multipass_dfa_lookahead): Use TUNE_GS464 instead of TUNE_LOONGSON_3A. (mips_option_override): Enable MMI and EXT for gs464. * config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464; Rename TUNE_LOONGSON_3A to TUNE_GS464. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464. (ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4, ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of TARGET_LOONGSON_3A. * config/mips/mips.md: Include gs464.md instead of loongson3a.md. (processor): Add gs464; * doc/invoke.texi: Add gs464 to supported architectures. --- gcc/config/mips/gs464.md | 137 ++++++++++++++++++++++++++++++++ gcc/config/mips/loongson3a.md | 137 -------------------------------- gcc/config/mips/mips-cpus.def | 3 +- gcc/config/mips/mips-tables.opt | 19 +++-- gcc/config/mips/mips.c | 6 +- gcc/config/mips/mips.h | 17 ++-- gcc/config/mips/mips.md | 4 +- gcc/doc/invoke.texi | 2 +- 8 files changed, 165 insertions(+), 160 deletions(-) create mode 100644 gcc/config/mips/gs464.md delete mode 100644 gcc/config/mips/loongson3a.md diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md new file mode 100644 index 00000000000..82efb66786f --- /dev/null +++ b/gcc/config/mips/gs464.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464 cores. + +;; Copyright (C) 2011-2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464_alu1" "gs464_a_alu") +(define_cpu_unit "gs464_alu2" "gs464_a_alu") +(define_cpu_unit "gs464_mem" "gs464_a_mem") +(define_cpu_unit "gs464_falu1" "gs464_a_falu") +(define_cpu_unit "gs464_falu2" "gs464_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464_arith" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464_alu1 | gs464_alu2") + +(define_insn_reservation "gs464_branch" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464_alu1") + +(define_insn_reservation "gs464_mfhilo" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464_imul3nc" 5 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul3nc")) + "gs464_alu2") + +(define_insn_reservation "gs464_imul" 7 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul,imadd")) + "gs464_alu2 * 7") + +(define_insn_reservation "gs464_idiv_si" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464_alu2 * 12") + +(define_insn_reservation "gs464_idiv_di" 25 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464_alu2 * 25") + +(define_insn_reservation "gs464_load" 3 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load")) + "gs464_mem") + +(define_insn_reservation "gs464_fpload" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load,mfc,mtc")) + "gs464_mem") + +(define_insn_reservation "gs464_prefetch" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "prefetch,prefetchx")) + "gs464_mem") + +(define_insn_reservation "gs464_store" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464_mem") + +;; All the fp operations can be executed in FALU1. Only fp add, +;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. +(define_insn_reservation "gs464_fadd" 6 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464_falu2 | gs464_falu1") + +(define_insn_reservation "gs464_fcmp" 2 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464_falu1") + +(define_insn_reservation "gs464_fcvt" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fcvt")) + "gs464_falu1") + +(define_insn_reservation "gs464_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464_falu1 * 12") + +(define_insn_reservation "gs464_fdiv_df" 19 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464_falu1 * 19") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464_unknown" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464_alu1 + gs464_alu2 + gs464_falu1 + gs464_falu2 + gs464_mem") + +;; End of DFA-based pipeline description for gs464 diff --git a/gcc/config/mips/loongson3a.md b/gcc/config/mips/loongson3a.md deleted file mode 100644 index 2ebde6824cd..00000000000 --- a/gcc/config/mips/loongson3a.md +++ /dev/null @@ -1,137 +0,0 @@ -;; Pipeline model for Loongson-3A cores. - -;; Copyright (C) 2011-2018 Free Software Foundation, Inc. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. -;; -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. -;; -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . - -;; Uncomment the following line to output automata for debugging. -;; (automata_option "v") - -;; Automaton for integer instructions. -(define_automaton "ls3a_a_alu") - -;; Automaton for floating-point instructions. -(define_automaton "ls3a_a_falu") - -;; Automaton for memory operations. -(define_automaton "ls3a_a_mem") - -;; Describe the resources. - -(define_cpu_unit "ls3a_alu1" "ls3a_a_alu") -(define_cpu_unit "ls3a_alu2" "ls3a_a_alu") -(define_cpu_unit "ls3a_mem" "ls3a_a_mem") -(define_cpu_unit "ls3a_falu1" "ls3a_a_falu") -(define_cpu_unit "ls3a_falu2" "ls3a_a_falu") - -;; Describe instruction reservations. - -(define_insn_reservation "ls3a_arith" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "arith,clz,const,logical, - move,nop,shift,signext,slt")) - "ls3a_alu1 | ls3a_alu2") - -(define_insn_reservation "ls3a_branch" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "branch,jump,call,condmove,trap")) - "ls3a_alu1") - -(define_insn_reservation "ls3a_mfhilo" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "mfhi,mflo,mthi,mtlo")) - "ls3a_alu2") - -;; Operation imul3nc is fully pipelined. -(define_insn_reservation "ls3a_imul3nc" 5 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul3nc")) - "ls3a_alu2") - -(define_insn_reservation "ls3a_imul" 7 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul,imadd")) - "ls3a_alu2 * 7") - -(define_insn_reservation "ls3a_idiv_si" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "SI"))) - "ls3a_alu2 * 12") - -(define_insn_reservation "ls3a_idiv_di" 25 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "DI"))) - "ls3a_alu2 * 25") - -(define_insn_reservation "ls3a_load" 3 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load")) - "ls3a_mem") - -(define_insn_reservation "ls3a_fpload" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load,mfc,mtc")) - "ls3a_mem") - -(define_insn_reservation "ls3a_prefetch" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "prefetch,prefetchx")) - "ls3a_mem") - -(define_insn_reservation "ls3a_store" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "store,fpstore,fpidxstore")) - "ls3a_mem") - -;; All the fp operations can be executed in FALU1. Only fp add, -;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. -(define_insn_reservation "ls3a_fadd" 6 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fadd,fmul,fmadd")) - "ls3a_falu2 | ls3a_falu1") - -(define_insn_reservation "ls3a_fcmp" 2 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fabs,fcmp,fmove,fneg")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fcvt" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fcvt")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fdiv_sf" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "SF"))) - "ls3a_falu1 * 12") - -(define_insn_reservation "ls3a_fdiv_df" 19 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "DF"))) - "ls3a_falu1 * 19") - -;; Force single-dispatch for unknown or multi. -(define_insn_reservation "ls3a_unknown" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "unknown,multi,atomic,syncloop")) - "ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem") - -;; End of DFA-based pipeline description for loongson_3a diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 6a545634417..eabe045cf39 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -162,7 +162,8 @@ MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ -MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 11be4639fc3..3114fce7c70 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -679,26 +679,29 @@ EnumValue Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(97) Canonical +Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(98) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(103) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 1c2075044d0..e6dd3795694 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -836,7 +836,7 @@ static const struct mips_rtx_cost_data { /* Loongson-2F */ DEFAULT_COSTS }, - { /* Loongson-3A */ + { /* Loongson gs464. */ DEFAULT_COSTS }, { /* M4k */ @@ -14614,7 +14614,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: - case PROCESSOR_LOONGSON_3A: + case PROCESSOR_GS464: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14746,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) + if (TUNE_LOONGSON_2EF || TUNE_GS464) return 4; if (TUNE_OCTEON) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index beeb4bcf20d..9666107077e 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -266,7 +266,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) -#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) +#define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -298,7 +298,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_74KF3_2) #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) -#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) +#define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,7 +792,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -909,7 +910,7 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ - %{march=loongson3a: -mloongson-ext}}" + %{march=loongson3a|march=gs464: -mloongson-ext}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -962,7 +963,7 @@ struct mips_cpu_info { /* ISA has 32 single-precision registers. */ #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ - && !TARGET_LOONGSON_3A) \ + && !TARGET_GS464) \ || TARGET_FLOAT64 \ || TARGET_MIPS5900) @@ -1005,7 +1006,7 @@ struct mips_cpu_info { because the former are faster and can also have the effect of reducing code size. */ #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A) \ + || TARGET_GS464) \ && !TARGET_MIPS16) /* ISA supports instructions DDIV and DDIVU. */ @@ -1098,14 +1099,14 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_LOONGSON_3A)) + || TARGET_GS464)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_LOONGSON_3A) + && !TARGET_GS464) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 8358218d8ac..d347a253ff1 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -37,7 +37,7 @@ 74kf3_2 loongson_2e loongson_2f - loongson_3a + gs464 m4k octeon octeon2 @@ -1173,7 +1173,7 @@ (include "9000.md") (include "10000.md") (include "loongson2ef.md") -(include "loongson3a.md") +(include "gs464.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d36a15a34ef..9780cb8f255 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20799,7 +20799,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, @samp{interaptiv}, -@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, +@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.18.0 From patchwork Wed Nov 7 09:16:50 2018 Content-Type: text/plain; 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run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 35602 invoked by uid 89); 7 Nov 2018 09:17:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=1647 X-HELO: mail-ot1-f44.google.com Received: from mail-ot1-f44.google.com (HELO mail-ot1-f44.google.com) (209.85.210.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:17:03 +0000 Received: by mail-ot1-f44.google.com with SMTP id 81so14192317otj.2 for ; Wed, 07 Nov 2018 01:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=noHMl1/LNjEZum3kaPyv0n5Jlm9ifb5HdJZBU3wQtx8=; b=HDpJ+jVHZPQzJK3B9RAhqvIZm1UWYk2oHaOWt7Jm1QL50TL6w2GNAaQ3QUB9avJuos v/01aIbvyOTcKUlfEyoVHnb/97PWIsmtPOOR+oWhkmEqr5PZJQdFzvl9RnfVSMXPQp2F z/3md66DZUpgiGXkBh2y70w6Y+tIdTSVrVyhOf2iX9+zxkx92JqQr+xdIQXAWKxc1QYe gjewYheugFZf1YkrfATWuuyN286tX1oYGpkRDrfI8SxFmtu8zgP4avuNJsU255XtZfoC Ew3aZKJaf/3Zp/+zCWicIxNuR455DAqSLPaSd9xDc25HfsZquibkje2mZfKptV2/5WNz yw7A== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:16:50 +0800 Message-ID: Subject: [PATCH v4 5/6, Committed] [MIPS] Add Loongson 3A2000/3A3000 processor support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From 51c914e8c2b2e4c7cc93718e563a8f55f0161ff9 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Wed, 7 Nov 2018 09:27:05 +0800 Subject: [PATCH 5/6] Add support for Loongson 3A2000/3A3000 processor. gcc/ * config/mips/gs464e.md: New. * config/mips/mips-cpus.def: Define gs464e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs464e. (mips_issue_rate): Add support for gs464e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT and EXT2 for gs464e. * config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E. * config/mips/mips.md: Include gs464e.md. (processor): Add gs464e. * doc/invoke.texi: Add gs464e to supported architectures. --- gcc/config/mips/gs464e.md | 137 ++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++-- gcc/config/mips/mips.c | 6 +- gcc/config/mips/mips.h | 13 ++- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 1 + 7 files changed, 166 insertions(+), 13 deletions(-) create mode 100644 gcc/config/mips/gs464e.md diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md new file mode 100644 index 00000000000..60e0e6b0463 --- /dev/null +++ b/gcc/config/mips/gs464e.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464e cores. + +;; Copyright (C) 2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464e_alu1" "gs464e_a_alu") +(define_cpu_unit "gs464e_alu2" "gs464e_a_alu") +(define_cpu_unit "gs464e_mem1" "gs464e_a_mem") +(define_cpu_unit "gs464e_mem2" "gs464e_a_mem") +(define_cpu_unit "gs464e_falu1" "gs464e_a_falu") +(define_cpu_unit "gs464e_falu2" "gs464e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464e_arith" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_branch" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_mfhilo" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464e_alu1 | gs464e_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464e_imul3nc" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul3nc")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_imul" 7 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul,imadd")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_si" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_di" 25 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_load" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fpload" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load,mfc,mtc")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_prefetch" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "prefetch,prefetchx")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_store" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fadd" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcmp" 2 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcvt" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fcvt")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_df" 19 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464e_falu1 | gs464e_falu2") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464e_unknown" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464e_alu1 + gs464e_alu2 + gs464e_falu1 + + gs464e_falu2 + gs464e_mem1 + gs464e_mem2") + +;; End of DFA-based pipeline description for gs464e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index eabe045cf39..b05b455c3c5 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -164,6 +164,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 3114fce7c70..539266aec89 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -682,26 +682,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical +Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e6dd3795694..74f6f8dfdae 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -839,6 +839,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464. */ DEFAULT_COSTS }, + { /* Loongson gs464e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14615,6 +14618,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: case PROCESSOR_GS464: + case PROCESSOR_GS464E: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14750,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_GS464) + if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; if (TUNE_OCTEON) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 9666107077e..193d399d0b8 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -267,6 +267,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) +#define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -299,6 +300,7 @@ struct mips_cpu_info { #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) +#define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,7 +794,7 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ @@ -910,7 +912,8 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ - %{march=loongson3a|march=gs464: -mloongson-ext}}" + %{march=loongson3a|march=gs464: -mloongson-ext} \ + {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -1099,14 +1102,16 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_GS464)) + || TARGET_GS464 \ + || TARGET_GS464E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_GS464) + && !TARGET_GS464 \ + && !TARGET_GS464E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d347a253ff1..acf572ab0d3 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -38,6 +38,7 @@ loongson_2e loongson_2f gs464 + gs464e m4k octeon octeon2 @@ -1174,6 +1175,7 @@ (include "10000.md") (include "loongson2ef.md") (include "gs464.md") +(include "gs464e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9780cb8f255..32929915622 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20800,6 +20800,7 @@ The processor names are: @samp{i6400}, @samp{i6500}, @samp{interaptiv}, @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464}, +@samp{gs464e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.18.0 From patchwork Wed Nov 7 09:17:27 2018 Content-Type: text/plain; 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run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 38881 invoked by uid 89); 7 Nov 2018 09:17:43 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-oi1-f173.google.com Received: from mail-oi1-f173.google.com (HELO mail-oi1-f173.google.com) (209.85.167.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:17:40 +0000 Received: by mail-oi1-f173.google.com with SMTP id k19-v6so13216321oic.11 for ; Wed, 07 Nov 2018 01:17:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=pPhVkeLz0EhR0uU+8ijZshTmfhW2xwdAu35ruVSexM8=; b=UWtbrc4HoFJRMG6hZnkL2HM7j7xDK1g4wQ/3FcOZiYuSU6S76Oc79qISgHqzsTrL5m 2Hdx5+fvwPMENRF4gyFk/7eymROzEh5I92ltnwZ4C/ujcLfY32Of4ZxMtl3CC58Ju5BF hrhITUm5W+eCBjHQPvJpcU3VsHRs3l9EK7ITAcznaG4y/IQW883W3GmBFi0FGS6/kQas OGq+Z513n9aNB0aeePDH7xteeXbMM8uJoGwkkMllYDZbMHlZw7W9hEQT2JBlpeU1gryM kFaihtqpM2hvCp8d5JLTA5rez/YEUBVzGtQfPp9iv7xd2h6lQuypfENZ5pslHtXsFaqt Xy8A== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:17:27 +0800 Message-ID: Subject: [PATCH v4 6/6, Committed] [MIPS] Add Loongson 2K1000 processor support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From 7ab0637b28b22bdb00e021692ceb8372855c8a87 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Wed, 7 Nov 2018 09:38:09 +0800 Subject: [PATCH 6/6] Add support for Loongson 2K1000 processor. gcc/ * config/mips/gs264e.md: New. * config/mips/mips-cpus.def: Define gs264e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs264e. (mips_issue_rate): Add support for gs264e. (mips_multipass_dfa_lookahead): Likewise. * config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e. (MIPS_ASE_MSA_SPEC): New. (BASE_DRIVER_SELF_SPECS): march=gs264e implies -mmsa. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E. * config/mips/mips.md: Include gs264e.md. (processor): Add gs264e. * config/mips/mips.opt (MSA): Use Mask instead of Var. * doc/invoke.texi: Add gs264e to supported architectures. --- gcc/config/mips/gs264e.md | 133 ++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++-- gcc/config/mips/mips.c | 6 +- gcc/config/mips/mips.h | 23 ++++-- gcc/config/mips/mips.md | 2 + gcc/config/mips/mips.opt | 2 +- gcc/doc/invoke.texi | 2 +- 8 files changed, 171 insertions(+), 17 deletions(-) create mode 100644 gcc/config/mips/gs264e.md diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md new file mode 100644 index 00000000000..8f1f9e17e08 --- /dev/null +++ b/gcc/config/mips/gs264e.md @@ -0,0 +1,133 @@ +;; Pipeline model for Loongson gs264e cores. + +;; Copyright (C) 2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs264e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs264e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs264e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs264e_alu1" "gs264e_a_alu") +(define_cpu_unit "gs264e_mem1" "gs264e_a_mem") +(define_cpu_unit "gs264e_falu1" "gs264e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs264e_arith" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_branch" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_mfhilo" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs264e_alu1") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs264e_imul3nc" 7 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "imul3nc")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_imul" 7 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "imul,imadd")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_idiv_si" 12 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs264e_alu1") + +(define_insn_reservation "gs264e_idiv_di" 25 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs264e_alu1") + +(define_insn_reservation "gs264e_load" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "load")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_fpload" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "load,mfc,mtc")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_prefetch" 0 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "prefetch,prefetchx")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_store" 0 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_fadd" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fcmp" 2 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fcvt" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fcvt")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fdiv_df" 19 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs264e_falu1") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs264e_unknown" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs264e_alu1 + gs264e_falu1 + gs264e_mem1") + +;; End of DFA-based pipeline description for gs264e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index b05b455c3c5..747739f4b90 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -165,6 +165,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs264e", PROCESSOR_GS264E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 539266aec89..7ab2cf5414b 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -685,26 +685,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical +Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 74f6f8dfdae..2b83e4ec679 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -842,6 +842,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464e. */ DEFAULT_COSTS }, + { /* Loongson gs264e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14605,6 +14608,7 @@ mips_issue_rate (void) case PROCESSOR_OCTEON2: case PROCESSOR_OCTEON3: case PROCESSOR_I6400: + case PROCESSOR_GS264E: return 2; case PROCESSOR_SB1: @@ -14753,7 +14757,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; - if (TUNE_OCTEON) + if (TUNE_OCTEON || TUNE_GS264E) return 2; if (TUNE_P5600 || TUNE_P6600 || TUNE_I6400) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 193d399d0b8..0a92cf6788a 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -268,6 +268,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) +#define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -301,6 +302,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) +#define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -794,8 +796,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ - |march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ + |march=octeon|march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -898,7 +900,9 @@ struct mips_cpu_info { MIPS_ISA_NAN2008_SPEC, \ MIPS_ASE_DSP_SPEC, \ MIPS_ASE_LOONGSON_MMI_SPEC, \ - MIPS_ASE_LOONGSON_EXT_SPEC + MIPS_ASE_LOONGSON_EXT_SPEC, \ + MIPS_ASE_MSA_SPEC + #define MIPS_ASE_DSP_SPEC \ "%{!mno-dsp: \ @@ -913,7 +917,12 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ %{march=loongson3a|march=gs464: -mloongson-ext} \ - {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}" + %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \ + -mloongson-ext2 -mloongson-ext}}}" + +#define MIPS_ASE_MSA_SPEC \ + "%{!mno-msa: \ + %{march=gs264e: -mmsa}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -1103,7 +1112,8 @@ struct mips_cpu_info { #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ || TARGET_GS464 \ - || TARGET_GS464E)) + || TARGET_GS464E \ + || TARGET_GS264E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ @@ -1111,7 +1121,8 @@ struct mips_cpu_info { && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ && !TARGET_GS464 \ - && !TARGET_GS464E) + && !TARGET_GS464E \ + && !TARGET_GS264E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index acf572ab0d3..9e222dc0df0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -39,6 +39,7 @@ loongson_2f gs464 gs464e + gs264e m4k octeon octeon2 @@ -1176,6 +1177,7 @@ (include "loongson2ef.md") (include "gs464.md") (include "gs464e.md") +(include "gs264e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index c0c8005b025..16c33d12e22 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -300,7 +300,7 @@ Target Report Mask(MICROMIPS) Use microMIPS instructions. mmsa -Target Report Var(TARGET_MSA) +Target Report Mask(MSA) Use MIPS MSA Extension instructions. mmt diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 32929915622..5c6745eadaf 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20800,7 +20800,7 @@ The processor names are: @samp{i6400}, @samp{i6500}, @samp{interaptiv}, @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464}, -@samp{gs464e}, +@samp{gs464e}, @samp{gs264e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.18.0