From patchwork Tue Nov 6 12:05:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 993647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489154-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="igXC4n0+"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mittosystems.com header.i=@mittosystems.com header.b="RwIbkHnn"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42q7YL3kb5z9sNF for ; Tue, 6 Nov 2018 23:05:57 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=GHcCg6rG/JBqsjrY6on7qxo3iKh9qp63tYy63+s8gLyiCbqk9n JzvLPEHontwsE0ZqB5bqwytNuyfXXRNxBNUp5v4YKK8QwRNQz/KlEXSrYZ4N30Iw 77OABMI5bG8WwR+IyXJ6Sf7szA271wcARQQI7UdbhAtwPM/VYnkCME65k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=9SHPhwhJHNEZ81vwJTgZ3jv9nw4=; b=igXC4n0+7KU/tdsVv5Wa 36FEk525T5POGy0LlJKUtZQ3UMKvv2IJpSMd16m/a7Cm3HqSNK0gXDGwYFxdnXt+ Zbi1A0veti7VZyeBKYtb5UpVx9j2nSFGEQXV2BIZM+2g8Lc1S68997SKDh1RpW5N kLPhmQ+ps5LsCi3G4fl3nQY= Received: (qmail 120180 invoked by alias); 6 Nov 2018 12:05:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 120167 invoked by uid 89); 6 Nov 2018 12:05:49 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=inconsistencies X-HELO: mail-wr1-f44.google.com Received: from mail-wr1-f44.google.com (HELO mail-wr1-f44.google.com) (209.85.221.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Nov 2018 12:05:47 +0000 Received: by mail-wr1-f44.google.com with SMTP id i17-v6so13189984wre.7 for ; Tue, 06 Nov 2018 04:05:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=to:from:subject:message-id:date:user-agent:mime-version :content-language; bh=ksb+rjx9kv0UftYXaX/E8qxTWXClUehvdJfkvUB2OO8=; b=RwIbkHnnZRp0sWaZR+hv7FL9sHx/lqwy+h9C0t3GAOp28tyI8wnZ0/DUpKE02qJMId 79yrLBI81DM47nH4PQAyG8RPyL5C3ROlO2TE+XykCRFT4bjNwzEojKzdJdxtFf+9PHKL JmQtWM1+AUnosnQj46uFGBf448Hi9I296ZMkuV/FlMoSJ7vaZ0KqlqEBhmPrvpvzz6H8 I2Q3J1mUFdo61/9Q24nzrZ1Ti8oAHsFMB3qxcwqhPBH/ZdARyBaRbYVJttEO81SEoYDJ s8iTZel1NrW72BY8AL4F38QvRbD8TLpxxdgDaPlSjb8HlgzGBVTWzz9m0Bjp1lbRgZha cFwQ== Received: from [192.168.1.145] ([88.98.203.54]) by smtp.gmail.com with ESMTPSA id k5-v6sm33224367wre.82.2018.11.06.04.05.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Nov 2018 04:05:43 -0800 (PST) To: GCC Patches From: Jozef Lawrynowicz Subject: [committed][MSP430] Fix classification of PC, CG1 and CG2 registers Message-ID: <022ef79f-d4b1-5fe9-95ee-7259b6e4dfed@mittosystems.com> Date: Tue, 6 Nov 2018 12:05:43 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 X-IsSubscribed: yes An ICE in gcc.dg/tree-ssa/asm-3.c for msp430-elf exposed some inconsistencies in the classification of some of the "special" registers, R0 (PC), R2 (SR/CG1) and R3 (CG2). REG_CLASS_CONTENTS[GEN_REGS] does not have the bit for any of these registers set, yet REGNO_REG_CLASS returns GEN_REGS for them. Fixed by setting bit 0 for R0 in REG_CLASS_CONTENTS[GEN_REGS], and for R2 and R3, REGNO_REG_CLASS will now return NO_REGS. It is appropriate for R0 (PC) to be in the GEN_REGS class, as it can be used as an operand in any instruction and using any addressing mode. Successfully regtested the attached patch on trunk, and committed. From 9e26066f2a0f979a6bea538d27524e03b81618f3 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Fri, 2 Nov 2018 20:59:10 +0000 Subject: [PATCH] [MSP430] Fix register classification of PC, CG1 and CG2 2018-11-06 Jozef Lawrynowicz * gcc/config/msp430/msp430.h (REG_CLASS_CONTENTS): Add R0 to REG_CLASS_CONTENTS[GEN_REGS]. (REGNO_REG_CLASS): Return NO_REGS for R2 and R3. * gcc/testsuite/gcc.target/msp430/special-regs.c: New test. --- gcc/config/msp430/msp430.h | 11 +++++++++-- gcc/testsuite/gcc.target/msp430/special-regs.c | 16 ++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/msp430/special-regs.c diff --git a/gcc/config/msp430/msp430.h b/gcc/config/msp430/msp430.h index 6bfe28c..380e63e 100644 --- a/gcc/config/msp430/msp430.h +++ b/gcc/config/msp430/msp430.h @@ -241,10 +241,15 @@ enum reg_class 0x00000000, \ 0x00001000, \ 0x00002000, \ - 0x0000fff2, \ + 0x0000fff3, \ 0x0001ffff \ } +/* GENERAL_REGS just means that the "g" and "r" constraints can use these + registers. + Even though R0 (PC) and R1 (SP) are not "general" in that they can be used + for any purpose by the register allocator, they are general in that they can + be used by any instruction in any addressing mode. */ #define GENERAL_REGS GEN_REGS #define BASE_REG_CLASS GEN_REGS #define INDEX_REG_CLASS GEN_REGS @@ -259,7 +264,9 @@ enum reg_class #define FIRST_PSEUDO_REGISTER 17 -#define REGNO_REG_CLASS(REGNO) ((REGNO) < 17 \ +#define REGNO_REG_CLASS(REGNO) (REGNO != 2 \ + && REGNO != 3 \ + && REGNO < 17 \ ? GEN_REGS : NO_REGS) #define TRAMPOLINE_SIZE 4 /* FIXME */ diff --git a/gcc/testsuite/gcc.target/msp430/special-regs.c b/gcc/testsuite/gcc.target/msp430/special-regs.c new file mode 100644 index 0000000..c9121e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/special-regs.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ + +int foo (void) +{ + register int pc __asm__("R0"); + register int sp __asm__("R1"); + register int cg1 __asm__("R2"); /* { dg-error "the register specified for 'cg1' is not general enough" } */ + register int cg2 __asm__("R3"); /* { dg-error "the register specified for 'cg2' is not general enough" } */ + + asm("" : "=r"(pc)); + asm("" : "=r"(sp)); + asm("" : "=r"(cg1)); + asm("" : "=r"(cg2)); + + return pc + sp + cg1 + cg2; +} -- 2.7.4