From patchwork Mon Nov 5 21:45:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 993411 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="c1ZjH3uG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42pmTL2yFnz9sDC for ; Tue, 6 Nov 2018 08:46:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0FF04C2242C; Mon, 5 Nov 2018 21:46:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E9307C21FA3; Mon, 5 Nov 2018 21:46:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 148B6C21DF8; Mon, 5 Nov 2018 21:46:03 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id 3BAA1C21D4A for ; Mon, 5 Nov 2018 21:46:02 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id y3-v6so10893375wrh.10 for ; Mon, 05 Nov 2018 13:46:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=cFGTrqSPcsXyc1c4c8xF2YevMOGbNqXy3Tktv6/EI0Y=; b=c1ZjH3uGCvkw8eedXHRLH/L84b73g5fVdxXz8eYRQwMi2v13awE1U7b645lQsQFFGs 7UTMp3hesE05YjxjRyTvVmZDERck5l9kl5ElY5ppU79nCuN5+fUeOnUEm0hPMzjPQiaG 8phunxXd+Ws0/BCPIrfrKDErSX5X6LhRKR92coVKOqXl1UneeuKnViJydaqjC9ZRltA3 yY2dYmNe+I2y/X+xPk/KwvjCToYPO5h2AVqln+DEe23YFYj26ZjzvRT3tGoDAvuMNC4k cScUOinf8nuFvFW+gPBSlKhX0aH0akXilC7cXOMXG6lYpH2X1FBjPja+gjv7uzzClsPZ jPXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=cFGTrqSPcsXyc1c4c8xF2YevMOGbNqXy3Tktv6/EI0Y=; b=Kj0E6X9vBqxkxlvN7TSktHaMEE+R1C8cwNrWpaRVnBjYJIvJgO/8ySYpe8NLM6dSJp 3Mnwvexv10QzoG3MrY9HLO1agIT1ioaIj8eSAiCYco1swNR0owMWr+0GOIfbn94lnRPB JAkB24czVRhho7hmMQPh5h77kWDSd/cIjaCmg1UFI39o5UBoHeHByOin1eO+i6V19Uct fhmZYGGnlz8s71rAVnnsZPaK1TDC95c15/IxcR2vljvXT4YIhhT7YC/wm9GUip6MCBth an8uJS4zMeel1d1honA0X0VGdIYzste5NQQxk1fkpW1HrhuDCq7fO/vWOLqpTR1xE53k 6ibQ== X-Gm-Message-State: AGRZ1gIbVZ5ti7nVwmne+xbEdX9OTS9JWtfc6aN+95SDdE1EnQcloOUV 6P9LOo/9RQRbQzrQ04y09pl2LUHN X-Google-Smtp-Source: AJdET5eZsfXT0N49U8ipMxIu8i4TbWFt1ItcgqJtdsTiuANdQsJoSLyg8rd4vGSd8v5vs3R3D3S39Q== X-Received: by 2002:a5d:4012:: with SMTP id n18-v6mr20483699wrp.185.1541454361307; Mon, 05 Nov 2018 13:46:01 -0800 (PST) Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz. [86.49.110.70]) by smtp.gmail.com with ESMTPSA id 78-v6sm25596250wma.38.2018.11.05.13.46.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 13:46:00 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 5 Nov 2018 22:45:48 +0100 Message-Id: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 Cc: Marek Vasut Subject: [U-Boot] [PATCH V3 1/4] mmc: tmio: Switch to clock framework X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Switch the driver to using clk_get_rate()/clk_set_rate() instead of caching the mclk frequency in it's private data. This is required on the SDHI variant of the controller, where the upstream mclk need to be adjusted when using UHS modes. Platforms which do not support clock framework or do not support it in eg. SPL default to 100 MHz clock. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- V2: - Fix build on certain platforms using SPL without clock framework V3: - Turn clk_get_rate into a callback and fill it as needed on both renesas and socionext platforms --- drivers/mmc/renesas-sdhi.c | 21 +++++++++++++-------- drivers/mmc/tmio-common.c | 17 ++++++++++++++--- drivers/mmc/tmio-common.h | 5 ++++- drivers/mmc/uniphier-sd.c | 30 ++++++++++++++++++++---------- 4 files changed, 51 insertions(+), 22 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index e7f96f8bf2..f4283d055f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -358,15 +358,21 @@ static const struct udevice_id renesas_sdhi_match[] = { { /* sentinel */ } }; +static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) +{ + return clk_get_rate(&priv->clk); +} + static int renesas_sdhi_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); u32 quirks = dev_get_driver_data(dev); struct fdt_resource reg_res; - struct clk clk; DECLARE_GLOBAL_DATA_PTR; int ret; + priv->clk_get_rate = renesas_sdhi_clk_get_rate; + if (quirks == RENESAS_GEN2_QUIRKS) { ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", 0, ®_res); @@ -380,22 +386,21 @@ static int renesas_sdhi_probe(struct udevice *dev) quirks |= TMIO_SD_CAP_16BIT; } - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { dev_err(dev, "failed to get host clock\n"); return ret; } /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { + ret = clk_set_rate(&priv->clk, 200000000); + if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; + clk_free(&priv->clk); + return ret; } - ret = clk_enable(&clk); - clk_free(&clk); + ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable host clock\n"); return ret; diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 0eca83a0f4..3ba2f07460 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -555,16 +555,24 @@ static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); } +static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv) +{ + return priv->clk_get_rate(priv); +} + static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc) { unsigned int divisor; u32 val, tmp; + ulong mclk; if (!mmc->clock) return; - divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); + mclk = tmio_sd_clk_get_rate(priv); + + divisor = DIV_ROUND_UP(mclk, mmc->clock); if (divisor <= 1) val = (priv->caps & TMIO_SD_CAP_RCAR) ? @@ -708,6 +716,7 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) struct tmio_sd_priv *priv = dev_get_priv(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); fdt_addr_t base; + ulong mclk; int ret; base = devfdt_get_addr(dev); @@ -750,10 +759,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) tmio_sd_host_init(priv); + mclk = tmio_sd_clk_get_rate(priv); + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; - plat->cfg.f_min = priv->mclk / + plat->cfg.f_min = mclk / (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); - plat->cfg.f_max = priv->mclk; + plat->cfg.f_max = mclk; plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ upriv->mmc = &plat->mmc; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 792b1ba5ae..6591c61c3c 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -117,7 +117,6 @@ struct tmio_sd_plat { struct tmio_sd_priv { void __iomem *regbase; - unsigned long mclk; unsigned int version; u32 caps; #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ @@ -133,6 +132,10 @@ struct tmio_sd_priv { #ifdef CONFIG_DM_REGULATOR struct udevice *vqmmc_dev; #endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif + ulong (*clk_get_rate)(struct tmio_sd_priv *); }; int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 813c28494c..6539880ab5 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -31,35 +31,45 @@ static const struct udevice_id uniphier_sd_match[] = { { /* sentinel */ } }; +static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv) +{ +#if CONFIG_IS_ENABLED(CLK) + return clk_get_rate(&priv->clk); +#elif CONFIG_SPL_BUILD + return 100000000; +#else + return 0; +#endif +} + static int uniphier_sd_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); + + priv->clk_get_rate = uniphier_sd_clk_get_rate; + #ifndef CONFIG_SPL_BUILD - struct clk clk; int ret; - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { dev_err(dev, "failed to get host clock\n"); return ret; } /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { + ret = clk_set_rate(&priv->clk, ULONG_MAX); + if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; + clk_free(&priv->clk); + return ret; } - ret = clk_enable(&clk); - clk_free(&clk); + ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable host clock\n"); return ret; } -#else - priv->mclk = 100000000; #endif return tmio_sd_probe(dev, 0); From patchwork Mon Nov 5 21:45:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 993412 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Pqoxcx5+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42pmTt4W2Dz9sDC for ; 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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id 78-v6sm25596250wma.38.2018.11.05.13.46.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 13:46:01 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 5 Nov 2018 22:45:49 +0100 Message-Id: <20181105214551.12163-2-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> References: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH V3 2/4] mmc: tmio: Do not set divider to 1 in DDR mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The TMIO core has a quirk where divider == 1 must not be set in DDR modes. Handle this by setting divider to 2, as suggested in the documentation. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/tmio-common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 3ba2f07460..424b60ce52 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -574,6 +574,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, divisor = DIV_ROUND_UP(mclk, mmc->clock); + /* Do not set divider to 0xff in DDR mode */ + if (mmc->ddr_mode && (divisor == 1)) + divisor = 2; + if (divisor <= 1) val = (priv->caps & TMIO_SD_CAP_RCAR) ? TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; From patchwork Mon Nov 5 21:45:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 993414 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kX8LdUah"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42pmWn70Tdz9sDC for ; Tue, 6 Nov 2018 08:48:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5D346C222E2; Mon, 5 Nov 2018 21:46:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 759BFC226AB; Mon, 5 Nov 2018 21:46:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 33B3BC22600; Mon, 5 Nov 2018 21:46:09 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id 1EEBEC22126 for ; Mon, 5 Nov 2018 21:46:05 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id u13-v6so9568116wmc.4 for ; Mon, 05 Nov 2018 13:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yV8IlX6qhxVDhFZZ2IyC0otvo0GwQBuMxgBlFZscv0A=; b=kX8LdUahJNu24xUVOwj2o6NqBwhffASPDJ+fcUiCDkpG2WNPN3KF04SdTv49DizmZ5 vtyhgFo7JSSAfNEciEWse82HTeNDb9g/fIqcHSzaWNj9YcyGJKYf4snHstbXkeNAJIai lGyH6fLxx4Vk6ClELmwK6P63S21oDJnWWe2ucJvOVzihIk2W7q+BRtGu+vSHTr4XcYgf kCMS4FpufL1pVzMvMlRCeUPhstlmVCEgUWdz2IAf0F8nZmze2J2Qs9/KdR90nMrkc1j/ uRFAmYRkKVIHLu7iOsQNNO7jRa0iZ4JxrZ6oq2SDpELsN+iicedw0M7wrLFAM5mYw4II XGNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yV8IlX6qhxVDhFZZ2IyC0otvo0GwQBuMxgBlFZscv0A=; b=fZ1ZdAwl6QpJzP7mCXpxJU6B89vSBErYcrf1s1mPc2fJ3jJ0nAHpe9RM/mNfE39btT RXnWzqSjIR2iPMziOikWUKNECMLXEob7YM0HziUBFb/3nLtBwbvIj0Q1YUvXn5CsgGCf z4ItWnMq5covoJL2fqX/Z6RT8lvC3eSr9B9l0XwdOQdVVu1ZNxKl3OmEB9qpc4/3KLO6 jfxbeUzU5tzYRZ0ScMS9/YbzCm2aHk9RjZQovvv1UDXuZ3XIJbfSIdYwOpwJNTF1fjN7 g3gvqiyCFEXjJIGxpAfsPm3t6JevaVIcS4syAfG9iRxUKhjBr+9KZU1nbRohLVbjJevA rOjA== X-Gm-Message-State: AGRZ1gKTaA9UEDIhfUmnNQaeD2+waya0kIMhdqSs7/180jvdqjVfm/I2 kDa4JKOzcQNPUyXi1HG4OjkfcW0t X-Google-Smtp-Source: AJdET5e5gGonuyN1cD+5+9+QsoIBLhT7uETFU/r5FQkuYeHEjrl9PcekV6R8LFX/VnorSPcZ87kDXQ== X-Received: by 2002:a1c:154a:: with SMTP id 71-v6mr7127058wmv.83.1541454364346; Mon, 05 Nov 2018 13:46:04 -0800 (PST) Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz. [86.49.110.70]) by smtp.gmail.com with ESMTPSA id 78-v6sm25596250wma.38.2018.11.05.13.46.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 13:46:03 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 5 Nov 2018 22:45:50 +0100 Message-Id: <20181105214551.12163-3-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> References: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH V3 3/4] mmc: tmio: Keep generating clock when clock are enabled X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The TMIO core has a feature where it can automatically disable clock output when the bus is not in use. While this is useful, it also interferes with switching the bus to 1.8V and other background tasks of the SD/MMC cards, which require clock to be enabled. This patch respects the mmc->clk_disable and only disables the clock when the MMC core requests it. Otherwise the clock are continuously generated on the bus. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/tmio-common.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 424b60ce52..fad2816ca5 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -612,10 +612,16 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; - tmp |= val | TMIO_SD_CLKCTL_OFFEN; + tmp |= val; tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); - tmp |= TMIO_SD_CLKCTL_SCLKEN; + if (!mmc->clk_disable) { + tmp &= ~TMIO_SD_CLKCTL_OFFEN; + tmp |= TMIO_SD_CLKCTL_SCLKEN; + } else { + tmp |= TMIO_SD_CLKCTL_OFFEN; + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + } tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); udelay(1000); From patchwork Mon Nov 5 21:45:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 993413 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Xa9uu/88"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42pmVj3sNbz9sDC for ; Tue, 6 Nov 2018 08:47:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3C33FC21FF8; Mon, 5 Nov 2018 21:46:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AA5C4C22601; Mon, 5 Nov 2018 21:46:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B217BC22255; Mon, 5 Nov 2018 21:46:10 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id 93892C222E0 for ; Mon, 5 Nov 2018 21:46:06 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id x12-v6so11196182wrw.8 for ; Mon, 05 Nov 2018 13:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aQug6o3kCiEpKLzG4h4Uy/8XzknMjuwCidu0hPhmZtc=; b=Xa9uu/882g1SoxE6n4qsmLdBiqxfEJB9VAuo+iFK3tPq7vv3w5ZYe4OM0ngt+a30Ls LR1PocP6etaxYLODF3vKKm/Y4IDVgAH7/WDEbkL5khatOJbpXnl8u+lpOAU16QmWP9MM jwVJEaoygs0kaJOXijMP9tU8Z7uJ0+jE0bnR2j2EuQee8TcmsMDYFD3zOaUfkyXREV6a 2Yby9lAbW+hNquRwRTskWYA7aa1bTjPQBkBqMP/QW7/WMAcVMepYeiYKyVkMW81GNcJC H4DkqWvHbXPyV1tzmydVa3A4+rPKc1+jhRrP+swd/nAYll2dVCv0MCnDGvvTWTour5qt VG9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aQug6o3kCiEpKLzG4h4Uy/8XzknMjuwCidu0hPhmZtc=; b=bR6ZqGtQD/M1TfcWA1HfsvzoJw9Ce1CSLm45grUDw+bdDxBg/LNUMdZ3wc5BXubonB cWEoPLygaUUaiEWVCdzfI9GOdLU0yut660a1e7PfazLlIelLQpCE3ebmEjR0N7GqjA4O j08eU9AntCnoMetujnwOt5qH491T2nSMESBrWKBMo5RUXbg9UpQU5V4AzCPK6dWq8bGZ xhIwmPLZwrN/f8+jemp9XkD3iR/nym5F81QEWE6i69ZNtg7AKq6KKDcc3yKDf46LQT9F Uh3dtWNCm6bR0rB0mVKd/CoqafnOT5e3amHhv1KyqyWkXKaPv8I2XfreB1bQ9UJmmOGz ExrA== X-Gm-Message-State: AGRZ1gJj7qecXHHTOOG+IAs+0GxfX3NDVoJpOf69lRiOg341gbCpPF2L kP4e9pPXBHSDHxreW3lMnJQbEnzu X-Google-Smtp-Source: AJdET5ehU3Ws5Ikw/4wzjkHE1coLCGdaapXY5P2yWO5K8Rz240BVOsA34J0Qo8IldN2gi8kwFUT0bw== X-Received: by 2002:adf:a78a:: with SMTP id j10-v6mr14296456wrc.286.1541454365801; Mon, 05 Nov 2018 13:46:05 -0800 (PST) Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz. [86.49.110.70]) by smtp.gmail.com with ESMTPSA id 78-v6sm25596250wma.38.2018.11.05.13.46.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 13:46:04 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 5 Nov 2018 22:45:51 +0100 Message-Id: <20181105214551.12163-4-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> References: <20181105214551.12163-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH V3 4/4] mmc: tmio: sdhi: Switch CPG settings in UHS modes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Switch CPG settings when transitioning between HS200/HS400/SDR104 and regular modes. This is required for the SCC block to operate correctly. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/renesas-sdhi.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index f4283d055f..fd2a361a6d 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -289,9 +289,35 @@ out: } #endif +static void renesas_sdhi_set_clk(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + u32 tmp; + + if (!mmc->clock) + return; + + /* Stop the clock before changing its rate to avoid a glitch signal */ + tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + + if ((mmc->selected_mode == UHS_SDR104) || + (mmc->selected_mode == MMC_HS_200)) { + clk_set_rate(&priv->clk, 400000000); + } else { + clk_set_rate(&priv->clk, 200000000); + } +} + static int renesas_sdhi_set_ios(struct udevice *dev) { - int ret = tmio_sd_set_ios(dev); + int ret; + + renesas_sdhi_set_clk(dev); + + ret = tmio_sd_set_ios(dev); mdelay(10);