From patchwork Fri Oct 26 11:16:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 989553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="M5D30Hpr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hM0l4dCLz9sDr for ; Fri, 26 Oct 2018 22:17:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727593AbeJZTx1 (ORCPT ); Fri, 26 Oct 2018 15:53:27 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:36312 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727502AbeJZTx0 (ORCPT ); Fri, 26 Oct 2018 15:53:26 -0400 Received: by mail-wr1-f65.google.com with SMTP id y16so948175wrw.3; Fri, 26 Oct 2018 04:16:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UzI7QItBboJycH/HpslvTFG94WVjeSBxpsz6zXZa7wE=; b=M5D30HprenHJK/ckhe7p0gHlRpkigXk2QIUfgYl0OD7y0Yljv0vqeSAB+jkuu6coMx zD1y2f3GjYPoBnidp1pr2g2etACqgr3rnhd8GwLIhUcVgmtWwT7imeDZHvuaUbb5V49Z UHyF3TiDqxtaSPSPYmpTA7VKdz7YgU7WyfG1FFuVF8FSBHi0PObynPCiwpyhWOg/wWY7 EgU8xV5/ZYlY2PWO58RD7wBa1nbJRGbAWujtn0i6iARr18WR6ddPppzejkoKZQHroeqt jJeac8iTZdOduzi0Z0n5ZfhJzv82RozYt/E+FH0vZ5tig98m+bkMWF7gEe18OaE4ikod 69DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UzI7QItBboJycH/HpslvTFG94WVjeSBxpsz6zXZa7wE=; b=aDm64JF0jP60HJrc4RZO6CVm5cgIEnzAwrgMHjyGvCJQl7bmaWdGs54vYdYKs+5JYP MXGN1Yc2L5vJoIoyW4NkukG+GmsDVLO6XX791SWM1ilAzHN1sIJlpGDrSgfdQXo38rOr zYn9N5fyZi+UXDYdrTRGBsY/1wVWjY4hefLHCkenNEz/b27NsKju/jFCngBiUozyrQwg hkL3lL1cAdHi1QLwaIvt2uHXqjt6UnIE9XpfQIHOr3QuHnsL6wqpFCrU6x9IGjGvQncr FydEVtIfk1gda7JSYKQoS171vNrN9s5KdTTi4NaN1AduFqbnxsR8uNs2B7DPt0GN0De6 5iYA== X-Gm-Message-State: AGRZ1gK/WKO1w6mj91j6JsXjRJyjCyAtvGf5Mlgx4RoLbuLh3jRKakgi 0j3zb1zBNX1woAOfKhqvrrI= X-Google-Smtp-Source: AJdET5cdQ/3a1bsJOFPGEEIX2i/kqhKCshjOa85p5giWBZN1TxTH9euVtLC4lDAq4MzoNmSnwpEakw== X-Received: by 2002:adf:fa92:: with SMTP id h18-v6mr5369795wrr.74.1540552603274; Fri, 26 Oct 2018 04:16:43 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id t66-v6sm3224263wmt.5.2018.10.26.04.16.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:42 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/9] mailbox: Support blocking transfers in atomic context Date: Fri, 26 Oct 2018 13:16:30 +0200 Message-Id: <20181026111638.10759-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The mailbox framework supports blocking transfers via completions for clients that can sleep. In order to support blocking transfers in cases where the transmission is not permitted to sleep, add a new ->flush() callback that controller drivers can implement to busy loop until the transmission has been completed. This will automatically be called when available and interrupts are disabled for clients that request blocking transfers. Signed-off-by: Thierry Reding --- drivers/mailbox/mailbox.c | 8 ++++++++ include/linux/mailbox_controller.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 674b35f402f5..0eaf21259874 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -267,6 +267,14 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg) unsigned long wait; int ret; + if (irqs_disabled() && chan->mbox->ops->flush) { + ret = chan->mbox->ops->flush(chan, chan->cl->tx_tout); + if (ret < 0) + tx_tick(chan, ret); + + return ret; + } + if (!chan->cl->tx_tout) /* wait forever */ wait = msecs_to_jiffies(3600000); else diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 74deadb42d76..2a07d93f781a 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -24,6 +24,9 @@ struct mbox_chan; * transmission of data is reported by the controller via * mbox_chan_txdone (if it has some TX ACK irq). It must not * sleep. + * @flush: Called when a client requests transmissions to be blocking but + * the context doesn't allow sleeping. Typically the controller + * will implement a busy loop waiting for the data to flush out. * @startup: Called when a client requests the chan. The controller * could ask clients for additional parameters of communication * to be provided via client's chan_data. This call may @@ -46,6 +49,7 @@ struct mbox_chan; */ struct mbox_chan_ops { int (*send_data)(struct mbox_chan *chan, void *data); + int (*flush)(struct mbox_chan *chan, unsigned long timeout); int (*startup)(struct mbox_chan *chan); void (*shutdown)(struct mbox_chan *chan); bool (*last_tx_done)(struct mbox_chan *chan); From patchwork Fri Oct 26 11:16:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 989542 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qKdzsUU/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hLzj4YjVz9sDn for ; Fri, 26 Oct 2018 22:16:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727659AbeJZTx3 (ORCPT ); Fri, 26 Oct 2018 15:53:29 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:44273 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726903AbeJZTx2 (ORCPT ); Fri, 26 Oct 2018 15:53:28 -0400 Received: by mail-wr1-f67.google.com with SMTP id d17-v6so643417wre.11; Fri, 26 Oct 2018 04:16:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JZ4YTuB3It2WTh2s9CHheVKlVJx+N83OyNKjw3ja39k=; b=qKdzsUU/RJzo/YihJKzjnaYZs1j56JJnmVTkJ347iJ4ahLQyqmhB20iPdle6aS4/2X bJ/GoC/sqDnKbxsElbErRLeLGk5y6Ee2PDSUheTNfi3Ew4Tvyr7wZ7Tryq+G+b1oIgyM 6zTSeUFOa+jpglUe5zpUGBsJurxdSjfUOXP6nGsac4k79Yu3XnfkNgJ5amdB2rARiWt8 CH6LQyUoxj3i/uJKophCaIQXKKd/14yIMg3XTZSdJYeM0xNNw7g9yNgF85S3mq4pTzrC ChygJv6MiDEZRPqSXM85fXy74QtYsAPFI27PVcPUTiwR3/t5y37mP/NSolImrkCS6r70 aD1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JZ4YTuB3It2WTh2s9CHheVKlVJx+N83OyNKjw3ja39k=; b=cplGJxmlSZwqQc0T00K8LBw9AP97uiOjN+Izf8vSes9MOspDDWkDWYnO2LXQrEJjgM qclkFXohcZpC2ZFV/i2hjBKRkgXW/Ifgf7c59uQ25QdbwR8wwEUZ9BTQwSiuIIglBoTP ICjRPjoZGVWDbs/Tv4GtS4srcKsMA+ew1ZLpivEgEH2v3YcV/DO75EusCRRd27NRg7Op lO3hQ13wrih0hQGx6iRcAqbzg2pePJTKBBTs+8j/lc1MWQT4TnI2+5tO1I5ZyiLAhVry t1MpT2FSH1Af/XvH5wtGsV3QtPxyzQoP1K/lhchoknG5xN/QaqM3nNRKFHpeeoICy4mL rMqA== X-Gm-Message-State: AGRZ1gLc9rvlP94jKj0DNIuThZp84XJticclmQ/MQG904cXto7ip2J1a wLVsodIpfsCcmtFo3C5iRX5niYJs X-Google-Smtp-Source: AJdET5dOu+C/2dVlN45lD3RawGcPQNlPD2ESVgv3qCJ8a5Gyv548/8qmAwvU/Zp6DnzMjgxLQFrqPA== X-Received: by 2002:a05:6000:8:: with SMTP id h8mr5255014wrx.103.1540552604877; Fri, 26 Oct 2018 04:16:44 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id q190-v6sm5994451wmg.40.2018.10.26.04.16.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:44 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/9] mailbox: Allow multiple controllers per device Date: Fri, 26 Oct 2018 13:16:31 +0200 Message-Id: <20181026111638.10759-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Look through the whole controller list when mapping device tree phandles to controllers instead of stopping at the first one. Each controller is intended to only contain one kind of mailbox, but some devices (like Tegra HSP) implement multiple kinds and use the same device tree node for all of them. As such, we need to allow multiple mbox_controllers per device tree node. Signed-off-by: Mikko Perttunen --- drivers/mailbox/mailbox.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 0eaf21259874..f34820bcf33c 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -335,7 +335,8 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) list_for_each_entry(mbox, &mbox_cons, node) if (mbox->dev->of_node == spec.np) { chan = mbox->of_xlate(mbox, &spec); - break; + if (!IS_ERR(chan)) + break; } of_node_put(spec.np); From patchwork Fri Oct 26 11:16:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 989543 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="R/ZvAVbK"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hLzl6Kh5z9sMx for ; Fri, 26 Oct 2018 22:16:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727684AbeJZTxa (ORCPT ); Fri, 26 Oct 2018 15:53:30 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:43868 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727502AbeJZTx3 (ORCPT ); Fri, 26 Oct 2018 15:53:29 -0400 Received: by mail-wr1-f65.google.com with SMTP id t10-v6so926260wrn.10; Fri, 26 Oct 2018 04:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X0uobgskPDvtt66nH74oPn5cyeTQ7D3Fue2q+TPC/RI=; b=R/ZvAVbKKjzEyXKDcuIoPSUbZlb64PmJP5Naps83k0gxN57CvefYm+1qquIfwTS8i2 W8H9gANo9kO4V6O67WOpkm9QvfAgBnShl9VBaxuOybFMskaWAVwX1dt5jtJxv8nJVEJN zl3qmmBp6kyVVqOYJ4gRexm6PdU/foMWzR5RPLy/guAFTThanJlUxxHyw51ZyghIBUVX Uo5tLZcv15ZWmQE6IFgEwkd9rXy02p3aoaQpO+A77ZoHdUK0s6R0+wUABrV2UYKBQPBs 6npaCTrqv1ROOcp47qcLFpdowTI7gP7pF+nJ/CwjMsVu3o+5jkZYcsMbRuAM+0ltHowN 7/Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X0uobgskPDvtt66nH74oPn5cyeTQ7D3Fue2q+TPC/RI=; b=GX2/uBkNhaMgHG2xwv5aSkxQ2wtiE+TZlp5gZpETVPs8CB7p0puakme80BUzOdlUvQ rEfOYr8RP1/pDsOb45VO4Euato579phEoMh1g+bkcunBQLr7uZkBgVPps7xvPjTVNKlI lc97FSlfJlk3be93jUzUthBHRCjURZ+dS0pMwGTmPT2ykOl0suPiVXozHFM4vQLdatOY Fz3HJJM4zNZkCOURUUNnILI53CY42n7lxFId00a5clVLIYniV/ge6Xxh40vNnVdqGec3 pqqCMPzKx6PLCMKBG+ZfY8SPINu1lf1OCOZRMAe6BMb98JF9XtcFIUtclKzvb2bJlG6+ qV6w== X-Gm-Message-State: AGRZ1gIv31d7ex0OhYFmYawRRkhUk9w04ATSGYz7GDmVw591HVBe4k8M yrpCHmRW64ACpv/Y9c6Qcgo= X-Google-Smtp-Source: AJdET5eOHFyQj8UmAXpplwL1Em0ZaVpUifoVxqZ9A5CL92MTbsFiA7WAxsrESAcB6En11O7Acd2jWg== X-Received: by 2002:adf:b6a8:: with SMTP id j40-v6mr4971221wre.55.1540552606624; Fri, 26 Oct 2018 04:16:46 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id j6-v6sm5348687wmd.29.2018.10.26.04.16.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:46 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/9] dt-bindings: tegra186-hsp: Add shared interrupts Date: Fri, 26 Oct 2018 13:16:32 +0200 Message-Id: <20181026111638.10759-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen HSP interrupts can be routed through exposed "shared interrupts". These interrupts can be mapped to various internal interrupt lines. Add interrupt properties for shared interrupts to the tegra186-hsp device tree bindings. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Reviewed-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt index b99d25fc2f26..620c249363ca 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -15,12 +15,15 @@ Required properties: Array of strings. one of: - "nvidia,tegra186-hsp" + - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" - reg : Offset and length of the register set for the device. - interrupt-names Array of strings. Contains a list of names for the interrupts described by the interrupt property. May contain the following entries, in any order: - "doorbell" + - "sharedN", where 'N' is a number from zero up to the number of + external interrupts supported by the HSP instance minus one. Users of this binding MUST look up entries in the interrupt property by name, using this interrupt-names property to do so. - interrupts From patchwork Fri Oct 26 11:16:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 989550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kWGcJCGv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hM0N1JTrz9sDF for ; Fri, 26 Oct 2018 22:17:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727726AbeJZTxe (ORCPT ); Fri, 26 Oct 2018 15:53:34 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:38630 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727666AbeJZTxd (ORCPT ); Fri, 26 Oct 2018 15:53:33 -0400 Received: by mail-wr1-f67.google.com with SMTP id d10-v6so950644wrs.5; Fri, 26 Oct 2018 04:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KZybGOtSAemy1CjzjcNF/ZknXxngxz/81lJVUnTVdE8=; b=kWGcJCGv3xOwk11103zPArswoi0cPmdmbZm1ViSXHChh9Qo5T/Z6SeKBDbXrR9d4AP nclyKjUSu4gfYYaD1Yj71yT6rjtmmZgdolSPItDRJaE8XUQpb19b9YJe+hQsSDxJXZom /D8QC4b9iSyyvX3Zl/3CPRgL6WdMUrXW+FV5ksGyCcs5zItg2KcUgX1F6oyp1lGMhclk GucwGwCEsEyem7dAMJ9D+maE/eK5UNEg473PMUswjMqJa/jnOmYcInmkJhJdt5ht81/j JJbkmWA2afTe6bX2LP61ita9AicvCNAhJwqClFbi9lVAq9XGMjWEmbDWuqbLeo5qgqXr NGRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KZybGOtSAemy1CjzjcNF/ZknXxngxz/81lJVUnTVdE8=; b=KZVx4SmlS4VR4Ueb47l8rEs8lV+WtiDQi8Tw/k78OqesH2JBZkqG8XCfvZEAGHRHDr PYUZxTdZ4poJjIpdoTguv82dkTgQbCbf8QXodfHerJ5YBODbt4vvj5XrC8Dtz2zPE9zD O4Xtq77iQRdLOjPezn9c7B5Zrm7dyhWaFKOP6rmXGFYNkcCnsdTN6c5eKcWcnPYVPM4H wE367lYJQn71ys4Yb2Sn2W23C7HZVHLQi4fpD99wG7zpQbCnxg5QuvHil5cZNz9LMrnH KA0CfmbmxHXXjVYZA/2LB9VusggqQ6IqTPzeclU0EOejwLK/gvV84xN9DBnwZef9ghT6 maAQ== X-Gm-Message-State: AGRZ1gJf0IxlkwBtiKPU0LFaljfZsqzFoP+91wigmq0MpGgGo6D4cQtC eRc9m7ATYo0h5bxvCNUAajw= X-Google-Smtp-Source: AJdET5dNejX/Bib3KP2Bb8i07vSUL2/JbOcZt0e9nw+F4rdAmrtfjtA0Z+82T+pKuyNeYEXle+9QMg== X-Received: by 2002:a5d:488a:: with SMTP id g10-v6mr5428331wrq.0.1540552608459; Fri, 26 Oct 2018 04:16:48 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id c2-v6sm8553496wrt.77.2018.10.26.04.16.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:47 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/9] mailbox: tegra-hsp: Add support for shared mailboxes Date: Fri, 26 Oct 2018 13:16:33 +0200 Message-Id: <20181026111638.10759-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra HSP block supports 'shared mailboxes' that are simple 32-bit registers consisting of a FULL bit in MSB position and 31 bits of data. The hardware can be configured to trigger interrupts when a mailbox is empty or full. Add support for these shared mailboxes to the HSP driver. The initial use for the mailboxes is the Tegra Combined UART. For this purpose, we use interrupts to receive data, and spinning to wait for the transmit mailbox to be emptied to minimize unnecessary overhead. Based on work by Mikko Perttunen . Signed-off-by: Thierry Reding --- drivers/mailbox/tegra-hsp.c | 476 +++++++++++++++++++++++++++++++----- 1 file changed, 415 insertions(+), 61 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 0cde356c11ab..d070c8e38375 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -11,6 +11,7 @@ * more details. */ +#include #include #include #include @@ -21,6 +22,17 @@ #include +#include "mailbox.h" + +#define HSP_INT_IE(x) (0x100 + ((x) * 4)) +#define HSP_INT_IV 0x300 +#define HSP_INT_IR 0x304 + +#define HSP_INT_EMPTY_SHIFT 0 +#define HSP_INT_EMPTY_MASK 0xff +#define HSP_INT_FULL_SHIFT 8 +#define HSP_INT_FULL_MASK 0xff + #define HSP_INT_DIMENSIONING 0x380 #define HSP_nSM_SHIFT 0 #define HSP_nSS_SHIFT 4 @@ -34,6 +46,11 @@ #define HSP_DB_RAW 0x8 #define HSP_DB_PENDING 0xc +#define HSP_SM_SHRD_MBOX 0x0 +#define HSP_SM_SHRD_MBOX_FULL BIT(31) +#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 +#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 + #define HSP_DB_CCPLEX 1 #define HSP_DB_BPMP 3 #define HSP_DB_MAX 7 @@ -55,6 +72,12 @@ struct tegra_hsp_doorbell { unsigned int index; }; +struct tegra_hsp_mailbox { + struct tegra_hsp_channel channel; + unsigned int index; + bool sending; +}; + struct tegra_hsp_db_map { const char *name; unsigned int master; @@ -66,10 +89,13 @@ struct tegra_hsp_soc { }; struct tegra_hsp { + struct device *dev; const struct tegra_hsp_soc *soc; - struct mbox_controller mbox; + struct mbox_controller mbox_db; + struct mbox_controller mbox_sm; void __iomem *regs; - unsigned int irq; + unsigned int doorbell_irq; + unsigned int *shared_irqs; unsigned int num_sm; unsigned int num_as; unsigned int num_ss; @@ -78,14 +104,9 @@ struct tegra_hsp { spinlock_t lock; struct list_head doorbells; + struct tegra_hsp_mailbox *mailboxes; }; -static inline struct tegra_hsp * -to_tegra_hsp(struct mbox_controller *mbox) -{ - return container_of(mbox, struct tegra_hsp, mbox); -} - static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) { return readl(hsp->regs + offset); @@ -158,7 +179,7 @@ static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) spin_lock(&hsp->lock); - for_each_set_bit(master, &value, hsp->mbox.num_chans) { + for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { struct tegra_hsp_doorbell *db; db = __tegra_hsp_doorbell_get(hsp, master); @@ -182,6 +203,84 @@ static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) return IRQ_HANDLED; } +static irqreturn_t tegra_hsp_shared_full_irq(int irq, void *data) +{ + struct tegra_hsp *hsp = data; + unsigned long bit, mask; + u32 status, value; + void *msg; + + status = tegra_hsp_readl(hsp, HSP_INT_IR); + + /* only interested in FULL interrupts */ + mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; + + if (!mask) + return IRQ_NONE; + + for_each_set_bit(bit, &mask, hsp->num_sm) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; + + if (!mb->sending) { + value = tegra_hsp_channel_readl(&mb->channel, + HSP_SM_SHRD_MBOX); + value &= ~HSP_SM_SHRD_MBOX_FULL; + msg = (void *)(unsigned long)value; + mbox_chan_received_data(mb->channel.chan, msg); + + /* + * Need to clear all bits here since some producers, + * such as TCU, depend on fields in the register + * getting cleared by the consumer. + * + * The mailbox API doesn't give the consumers a way + * of doing that explicitly, so we have to make sure + * we cover all possible cases. + */ + tegra_hsp_channel_writel(&mb->channel, 0x0, + HSP_SM_SHRD_MBOX); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t tegra_hsp_shared_empty_irq(int irq, void *data) +{ + struct tegra_hsp *hsp = data; + unsigned long bit, mask; + u32 status, value; + + status = tegra_hsp_readl(hsp, HSP_INT_IR); + + /* only interested in EMPTY interrupts */ + mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; + + if (!mask) + return IRQ_NONE; + + for_each_set_bit(bit, &mask, hsp->num_sm) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; + + if (mb->sending) { + /* + * Disable EMPTY interrupts until data is sent + * with the next message. These interrupts are + * level-triggered, so if we kept them enabled + * they would constantly trigger until we next + * write data into the message. + */ + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + + mbox_chan_txdone(mb->channel.chan, 0); + } + } + + return IRQ_HANDLED; +} + static struct tegra_hsp_channel * tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, unsigned int master, unsigned int index) @@ -194,7 +293,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, if (!db) return ERR_PTR(-ENOMEM); - offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) << 16; + offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; offset += index * 0x100; db->channel.regs = hsp->regs + offset; @@ -235,8 +334,8 @@ static int tegra_hsp_doorbell_startup(struct mbox_chan *chan) unsigned long flags; u32 value; - if (db->master >= hsp->mbox.num_chans) { - dev_err(hsp->mbox.dev, + if (db->master >= chan->mbox->num_chans) { + dev_err(chan->mbox->dev, "invalid master ID %u for HSP channel\n", db->master); return -EINVAL; @@ -281,46 +380,147 @@ static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan) spin_unlock_irqrestore(&hsp->lock, flags); } -static const struct mbox_chan_ops tegra_hsp_doorbell_ops = { +static const struct mbox_chan_ops tegra_hsp_db_ops = { .send_data = tegra_hsp_doorbell_send_data, .startup = tegra_hsp_doorbell_startup, .shutdown = tegra_hsp_doorbell_shutdown, }; -static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox, +static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp *hsp = mb->channel.hsp; + u32 value; + + mb->sending = true; + + /* copy data and mark mailbox full */ + value = (u32)(unsigned long)data; + value |= HSP_SM_SHRD_MBOX_FULL; + + tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX); + + if (!irqs_disabled()) { + /* enable EMPTY interrupt for the shared mailbox */ + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + } + + return 0; +} + +static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, + unsigned long timeout) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + u32 value; + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_before(jiffies, timeout)) { + value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); + if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { + mbox_chan_txdone(chan, 0); + return 0; + } + + udelay(1); + } + + return -ETIME; +} + +static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + struct tegra_hsp *hsp = mb->channel.hsp; + u32 value; + + chan->txdone_method = TXDONE_BY_IRQ; + + /* + * Shared mailboxes start out as consumers by default. FULL interrupts + * are coalesced at shared interrupt 0, while EMPTY interrupts will be + * coalesced at shared interrupt 1. + * + * Keep EMPTY interrupts disabled at startup and only enable them when + * the mailbox is actually full. This is required because the FULL and + * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts + * enabled all the time would cause an interrupt storm while mailboxes + * are idle. + */ + + value = tegra_hsp_readl(hsp, HSP_INT_IE(0)); + value |= BIT(HSP_INT_FULL_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(0)); + + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + + tegra_hsp_channel_writel(ch, 0x1, HSP_SM_SHRD_MBOX_FULL_INT_IE); + tegra_hsp_channel_writel(ch, 0x1, HSP_SM_SHRD_MBOX_EMPTY_INT_IE); + + return 0; +} + +static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + struct tegra_hsp *hsp = mb->channel.hsp; + u32 value; + + tegra_hsp_channel_writel(ch, 0x0, HSP_SM_SHRD_MBOX_EMPTY_INT_IE); + tegra_hsp_channel_writel(ch, 0x0, HSP_SM_SHRD_MBOX_FULL_INT_IE); + + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + + value = tegra_hsp_readl(hsp, HSP_INT_IE(0)); + value &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(0)); +} + +static const struct mbox_chan_ops tegra_hsp_sm_ops = { + .send_data = tegra_hsp_mailbox_send_data, + .flush = tegra_hsp_mailbox_flush, + .startup = tegra_hsp_mailbox_startup, + .shutdown = tegra_hsp_mailbox_shutdown, +}; + +static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox, const struct of_phandle_args *args) { + struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db); + unsigned int type = args->args[0], master = args->args[1]; struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV); - struct tegra_hsp *hsp = to_tegra_hsp(mbox); - unsigned int type = args->args[0]; - unsigned int master = args->args[1]; struct tegra_hsp_doorbell *db; struct mbox_chan *chan; unsigned long flags; unsigned int i; - switch (type) { - case TEGRA_HSP_MBOX_TYPE_DB: - db = tegra_hsp_doorbell_get(hsp, master); - if (db) - channel = &db->channel; + if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq) + return ERR_PTR(-ENODEV); - break; - - default: - break; - } + db = tegra_hsp_doorbell_get(hsp, master); + if (db) + channel = &db->channel; if (IS_ERR(channel)) return ERR_CAST(channel); spin_lock_irqsave(&hsp->lock, flags); - for (i = 0; i < hsp->mbox.num_chans; i++) { - chan = &hsp->mbox.chans[i]; + for (i = 0; i < mbox->num_chans; i++) { + chan = &mbox->chans[i]; if (!chan->con_priv) { - chan->con_priv = channel; channel->chan = chan; + chan->con_priv = db; break; } @@ -332,6 +532,19 @@ static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox, return chan ?: ERR_PTR(-EBUSY); } +static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *args) +{ + struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm); + unsigned int type = args->args[0], index = args->args[1]; + + if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs || + index >= hsp->num_sm) + return ERR_PTR(-ENODEV); + + return hsp->mailboxes[index].channel.chan; +} + static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp) { struct tegra_hsp_doorbell *db, *tmp; @@ -364,10 +577,72 @@ static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp) return 0; } +static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev) +{ + int i; + + hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), + GFP_KERNEL); + if (!hsp->mailboxes) + return -ENOMEM; + + for (i = 0; i < hsp->num_sm; i++) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; + + mb->index = i; + mb->sending = false; + + mb->channel.hsp = hsp; + mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; + mb->channel.chan = &hsp->mbox_sm.chans[i]; + mb->channel.chan->con_priv = mb; + } + + return 0; +} + +static int tegra_hsp_request_shared_irqs(struct tegra_hsp *hsp) +{ + int err; + + if (hsp->shared_irqs[0] > 0) { + err = devm_request_irq(hsp->dev, hsp->shared_irqs[0], + tegra_hsp_shared_full_irq, 0, + dev_name(hsp->dev), hsp); + if (err < 0) { + dev_err(hsp->dev, + "failed to request full interrupt: %d\n", + err); + return err; + } + + dev_dbg(hsp->dev, "full interrupt requested: %u\n", + hsp->shared_irqs[0]); + } + + if (hsp->shared_irqs[1] > 0) { + err = devm_request_irq(hsp->dev, hsp->shared_irqs[1], + tegra_hsp_shared_empty_irq, 0, + dev_name(hsp->dev), hsp); + if (err < 0) { + dev_err(hsp->dev, + "failed to request empty interrupt: %d\n", + err); + return err; + } + + dev_dbg(hsp->dev, "empty interrupt requested: %u\n", + hsp->shared_irqs[1]); + } + + return 0; +} + static int tegra_hsp_probe(struct platform_device *pdev) { struct tegra_hsp *hsp; struct resource *res; + unsigned int i; u32 value; int err; @@ -375,6 +650,7 @@ static int tegra_hsp_probe(struct platform_device *pdev) if (!hsp) return -ENOMEM; + hsp->dev = &pdev->dev; hsp->soc = of_device_get_match_data(&pdev->dev); INIT_LIST_HEAD(&hsp->doorbells); spin_lock_init(&hsp->lock); @@ -392,58 +668,136 @@ static int tegra_hsp_probe(struct platform_device *pdev) hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; err = platform_get_irq_byname(pdev, "doorbell"); - if (err < 0) { - dev_err(&pdev->dev, "failed to get doorbell IRQ: %d\n", err); - return err; + if (err >= 0) + hsp->doorbell_irq = err; + + if (hsp->num_si > 0) { + unsigned int count = 0; + + hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si, + sizeof(*hsp->shared_irqs), + GFP_KERNEL); + if (!hsp->shared_irqs) + return -ENOMEM; + + for (i = 0; i < hsp->num_si; i++) { + char *name; + + name = kasprintf(GFP_KERNEL, "shared%u", i); + if (!name) + return -ENOMEM; + + err = platform_get_irq_byname(pdev, name); + if (err >= 0) { + hsp->shared_irqs[i] = err; + count++; + } + + kfree(name); + } + + if (count == 0) { + devm_kfree(&pdev->dev, hsp->shared_irqs); + hsp->shared_irqs = NULL; + } } - hsp->irq = err; + /* setup the doorbell controller */ + hsp->mbox_db.of_xlate = tegra_hsp_db_xlate; + hsp->mbox_db.num_chans = 32; + hsp->mbox_db.dev = &pdev->dev; + hsp->mbox_db.ops = &tegra_hsp_db_ops; - hsp->mbox.of_xlate = of_tegra_hsp_xlate; - hsp->mbox.num_chans = 32; - hsp->mbox.dev = &pdev->dev; - hsp->mbox.txdone_irq = false; - hsp->mbox.txdone_poll = false; - hsp->mbox.ops = &tegra_hsp_doorbell_ops; + hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, + sizeof(*hsp->mbox_db.chans), + GFP_KERNEL); + if (!hsp->mbox_db.chans) + return -ENOMEM; - hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans, - sizeof(*hsp->mbox.chans), - GFP_KERNEL); - if (!hsp->mbox.chans) + if (hsp->doorbell_irq) { + err = tegra_hsp_add_doorbells(hsp); + if (err < 0) { + dev_err(&pdev->dev, "failed to add doorbells: %d\n", + err); + return err; + } + } + + err = mbox_controller_register(&hsp->mbox_db); + if (err < 0) { + dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n", err); + goto remove_doorbells; + } + + /* setup the shared mailbox controller */ + hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate; + hsp->mbox_sm.num_chans = hsp->num_sm; + hsp->mbox_sm.dev = &pdev->dev; + hsp->mbox_sm.ops = &tegra_hsp_sm_ops; + + hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, + sizeof(*hsp->mbox_sm.chans), + GFP_KERNEL); + if (!hsp->mbox_sm.chans) return -ENOMEM; - err = tegra_hsp_add_doorbells(hsp); + if (hsp->shared_irqs) { + err = tegra_hsp_add_mailboxes(hsp, &pdev->dev); + if (err < 0) { + dev_err(&pdev->dev, "failed to add mailboxes: %d\n", + err); + goto unregister_mbox_db; + } + } + + err = mbox_controller_register(&hsp->mbox_sm); if (err < 0) { - dev_err(&pdev->dev, "failed to add doorbells: %d\n", err); - return err; + dev_err(&pdev->dev, "failed to register shared mailbox: %d\n", err); + goto unregister_mbox_db; } platform_set_drvdata(pdev, hsp); - err = mbox_controller_register(&hsp->mbox); - if (err) { - dev_err(&pdev->dev, "failed to register mailbox: %d\n", err); - tegra_hsp_remove_doorbells(hsp); - return err; + if (hsp->doorbell_irq) { + err = devm_request_irq(&pdev->dev, hsp->doorbell_irq, + tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND, + dev_name(&pdev->dev), hsp); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request doorbell IRQ#%u: %d\n", + hsp->doorbell_irq, err); + goto unregister_mbox_sm; + } } - err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq, - IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", - hsp->irq, err); - return err; + if (hsp->shared_irqs) { + err = tegra_hsp_request_shared_irqs(hsp); + if (err < 0) + goto unregister_mbox_sm; } return 0; + +unregister_mbox_sm: + mbox_controller_unregister(&hsp->mbox_sm); +unregister_mbox_db: + mbox_controller_unregister(&hsp->mbox_db); +remove_doorbells: + if (hsp->doorbell_irq) + tegra_hsp_remove_doorbells(hsp); + + return err; } static int tegra_hsp_remove(struct platform_device *pdev) { struct tegra_hsp *hsp = platform_get_drvdata(pdev); - mbox_controller_unregister(&hsp->mbox); - tegra_hsp_remove_doorbells(hsp); + mbox_controller_unregister(&hsp->mbox_sm); + mbox_controller_unregister(&hsp->mbox_db); + + if (hsp->doorbell_irq) + tegra_hsp_remove_doorbells(hsp); return 0; } From patchwork Fri Oct 26 11:16:34 2018 Content-Type: text/plain; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id a2-v6sm1743870wmf.12.2018.10.26.04.16.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:49 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/9] mailbox: tegra-hsp: Add suspend/resume support Date: Fri, 26 Oct 2018 13:16:34 +0200 Message-Id: <20181026111638.10759-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Upon resuming from a system sleep state, the interrupts for all active shared mailboxes need to be reenabled, otherwise they will not work. Signed-off-by: Thierry Reding --- drivers/mailbox/tegra-hsp.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index d070c8e38375..043f7173af8f 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -802,6 +803,23 @@ static int tegra_hsp_remove(struct platform_device *pdev) return 0; } +static int tegra_hsp_resume(struct device *dev) +{ + struct tegra_hsp *hsp = dev_get_drvdata(dev); + unsigned int i; + + for (i = 0; i < hsp->num_sm; i++) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; + + if (mb->channel.chan->cl) + tegra_hsp_mailbox_startup(mb->channel.chan); + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume); + static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, }, { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, }, @@ -821,6 +839,7 @@ static struct platform_driver tegra_hsp_driver = { .driver = { .name = "tegra-hsp", .of_match_table = tegra_hsp_match, + .pm = &tegra_hsp_pm_ops, }, .probe = tegra_hsp_probe, .remove = tegra_hsp_remove, From patchwork Fri Oct 26 11:16:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 989549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aOaCqJPC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hM0L2VlQz9sMr for ; Fri, 26 Oct 2018 22:17:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727740AbeJZTxg (ORCPT ); Fri, 26 Oct 2018 15:53:36 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:40476 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727686AbeJZTxf (ORCPT ); Fri, 26 Oct 2018 15:53:35 -0400 Received: by mail-wr1-f66.google.com with SMTP id i17-v6so894257wre.7; Fri, 26 Oct 2018 04:16:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bv2YS9N2LMSq+eP7/rHzcd3tzw14G3HT9MLQqCkcqxs=; b=aOaCqJPCGVp6biml68UFwxuyvI+vV5FOZZ9YvLneAXLD3cTpEqsIcXR9oXWV09YiTj vqF5fWYtDj0ojyED8oXpHLVixOmfOvk/gi9tQuG+GDEV60La2Nni/v7PbchhQB5rN4Rw XxkE/4B5xYpNUJEDyOEJUoWp3zEg+QluuJKcJ1HlchHCgIz/vX7dDhl+6w/+90fBYmPf YmE/sUqgf69e42T/0z+XBrhv8p+Viijx69obABzCOamCUGa010l8XcS6xA9hLfSrjKEw AdzSd8CVp+UC9o1XtiM2QYQVi+/S7wlFG0iBRl0WkxRb/i4JfcM3m2foKWIDR9tLKHE9 fj/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bv2YS9N2LMSq+eP7/rHzcd3tzw14G3HT9MLQqCkcqxs=; b=Tx/vuaoUSPZArVz7bG2kqrp/wWnGxSxpZ8vv9W7lb2MdXtyk/T2xAhRPK3G+7977NR zljvpEwP+j7LmP24lDhIO80JoTsZohCpXdhzL1QdBGlgSiHGvzAXKNDafdI6R8WwUSWf auq8Q4e+AL7bc7CGfbGLEbooo66z9iejEvaontGVdeL56sO7jzGm4eW/tUZyT8+wOoYk N9TJPWwIb6TKi1RaVGfc3LGaKmJfSRD3CKFfqr7Ii6oJQvYv1t5hFDBSlCPLcZ5pDtik j7FwpE0o2Q62NHZeGnfFPfgyFlLy3LACNvLelx4UdWWglNEK4kJuzwWrP04HLQ0dAElr 5PSA== X-Gm-Message-State: AGRZ1gKARgJdppFNTLEpZ+b5F3eezs7q8z/rD4GdiCbrjY2tH4HGkKz3 VDuq7pvBk6jDs2ac8ak2Ogk= X-Google-Smtp-Source: AJdET5fj5JDtKFHfOlvsvu+3Rg/yxA+sIh6V70YGAkJL0z8XAfMtJolktKTlXJMi+Z1rigNBv+vaGQ== X-Received: by 2002:a5d:434c:: with SMTP id u12-v6mr5191375wrr.306.1540552611767; Fri, 26 Oct 2018 04:16:51 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id q77-v6sm5757398wmd.33.2018.10.26.04.16.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:51 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/9] dt-bindings: serial: Add bindings for nvidia, tegra194-tcu Date: Fri, 26 Oct 2018 13:16:35 +0200 Message-Id: <20181026111638.10759-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Add bindings for the Tegra Combined UART device used to talk to the UART console on Tegra194 systems. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt new file mode 100644 index 000000000000..a8becf6efd2a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt @@ -0,0 +1,35 @@ +NVIDIA Tegra Combined UART (TCU) + +The TCU is a system for sharing a hardware UART instance among multiple +systems within the Tegra SoC. It is implemented through a mailbox- +based protocol where each "virtual UART" has a pair of mailboxes, one +for transmitting and one for receiving, that is used to communicate +with the hardware implementing the TCU. + +Required properties: +- name : Should be tcu +- compatible + Array of strings + One of: + - "nvidia,tegra194-tcu" +- mbox-names: + "rx" - Mailbox for receiving data from hardware UART + "tx" - Mailbox for transmitting data to hardware UART +- mboxes: Mailboxes corresponding to the mbox-names. + +This node is a mailbox consumer. See the following files for details of +the mailbox subsystem, and the specifiers implemented by the relevant +provider(s): + +- .../mailbox/mailbox.txt +- .../mailbox/nvidia,tegra186-hsp.txt + +Example bindings: +----------------- + +tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; +}; From patchwork Fri Oct 26 11:16:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 989546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RY9+BIsr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hM0916p5z9sN6 for ; Fri, 26 Oct 2018 22:17:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727759AbeJZTxj (ORCPT ); Fri, 26 Oct 2018 15:53:39 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:42944 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727666AbeJZTxh (ORCPT ); Fri, 26 Oct 2018 15:53:37 -0400 Received: by mail-wr1-f66.google.com with SMTP id y15-v6so929619wru.9; Fri, 26 Oct 2018 04:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t0SsqNzZTENUg3cef2avj+k6dlilGRNUZUBNqnDuQY8=; b=RY9+BIsrumY8ePdidBrujhUl2GfBZrj+XUj/pshWioPizS435NzMLIm+bSMPsF3Rnc Pugj6QgPDzReqgvBkwXILinJFp05pjDxAx+U2uHiTMFXqZSBou++Zr//7oE9ytgQciFd bl1F/fhuJQJ4F/kLJ6IAmuQdOBIHFKmDx3ptNjB24+OGUsCpVBobHxLswleumQpbcKq4 NyhOGtQhSSLTiqPNp30/gnOF7GYt3eZPb3gDJVgmlymf9wbF5ckqlFreuiiE1cpmAhHv SiwA+kC2TIGPvjEo3z3xgQ3J91ZU9WCGypva8J5t60setY5FiwhfnsP3gOyEvC+PUHqz Avhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t0SsqNzZTENUg3cef2avj+k6dlilGRNUZUBNqnDuQY8=; b=WmZSswf1L62NkpvkrleIMXtzbZLbfeyK/AnE+4j8L41OqeJHQ/ltQOBxzCzM9qQDtn jAqf7jCIGTz4AiUYmmwgBYjhmyYHPggxl5QaKYKYFc638rKxfYFWnCQfWWWbNbpCAD1t ttqvKzB1noZrcykuB91rrWGLE9gagIUgW+hS+AwFf5AHx7yJpvtTdX1+TquczDiI+KGt BF0bn8QMD8MBfckE7fOnngXwLQsO3tMmnav7xwt1K78CTUOT5uutSVGH+hFfzqua806/ WIIfqkQvrQb2Lzt1dC80y6HGedXXZY7OxFIcIqpkt/v2Lksg+BNkTvNH5SiTv9lc6Ab+ JJ7g== X-Gm-Message-State: AGRZ1gL0/Rb4Utg7DYl5jwYLNncYtpO75sMkwscPREKUs+dCCwbcbEkF TB2ahLrKzwtJqjSeGLxAGL0= X-Google-Smtp-Source: AJdET5feOeZcPaKS2eIVrNMlwRa/X0gvfisQPWEgQsufsxoRWfud4mZc3DzMzfEtDNnDhF0JRVLxeg== X-Received: by 2002:a5d:620b:: with SMTP id y11-v6mr5216349wru.105.1540552613320; Fri, 26 Oct 2018 04:16:53 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id z185-v6sm6601402wmz.47.2018.10.26.04.16.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:52 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/9] serial: Add Tegra Combined UART driver Date: Fri, 26 Oct 2018 13:16:36 +0200 Message-Id: <20181026111638.10759-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows multiplexing multiple "virtual UARTs" into a single hardware serial port. The TCU is the primary serial port on Tegra194 devices. Add a TCU driver utilizing the mailbox framework, as the used mailboxes are part of Tegra HSP blocks that are already controlled by the Tegra HSP mailbox driver. Based on work by Mikko Perttunen . Signed-off-by: Thierry Reding Acked-by: Greg Kroah-Hartman --- drivers/tty/serial/Kconfig | 22 +++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/tegra-tcu.c | 299 +++++++++++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 4 files changed, 325 insertions(+) create mode 100644 drivers/tty/serial/tegra-tcu.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 32886c304641..785306388aa4 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -323,6 +323,28 @@ config SERIAL_TEGRA are enabled). This driver uses the APB DMA to achieve higher baudrate and better performance. +config SERIAL_TEGRA_TCU + tristate "NVIDIA Tegra Combined UART" + depends on ARCH_TEGRA && TEGRA_HSP_MBOX + select SERIAL_CORE + help + Support for the mailbox-based TCU (Tegra Combined UART) serial port. + TCU is a virtual serial port that allows multiplexing multiple data + streams into a single hardware serial port. + +config SERIAL_TEGRA_TCU_CONSOLE + bool "Support for console on a Tegra TCU serial port" + depends on SERIAL_TEGRA_TCU=y + select SERIAL_CORE_CONSOLE + default y + ---help--- + If you say Y here, it will be possible to use a the Tegra TCU as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + If unsure, say Y. + config SERIAL_MAX3100 tristate "MAX3100 support" depends on SPI diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index daac675612df..4ad82231ff8a 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o +obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o obj-$(CONFIG_SERIAL_ARC) += arc_uart.o diff --git a/drivers/tty/serial/tegra-tcu.c b/drivers/tty/serial/tegra-tcu.c new file mode 100644 index 000000000000..1d360cd03b18 --- /dev/null +++ b/drivers/tty/serial/tegra-tcu.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TCU_MBOX_BYTE(i, x) ((x) << (i * 8)) +#define TCU_MBOX_BYTE_V(x, i) (((x) >> (i * 8)) & 0xff) +#define TCU_MBOX_NUM_BYTES(x) ((x) << 24) +#define TCU_MBOX_NUM_BYTES_V(x) (((x) >> 24) & 0x3) + +struct tegra_tcu { + struct uart_driver driver; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + struct console console; +#endif + struct uart_port port; + + struct mbox_client tx_client, rx_client; + struct mbox_chan *tx, *rx; +}; + +static unsigned int tegra_tcu_uart_tx_empty(struct uart_port *port) +{ + return TIOCSER_TEMT; +} + +static void tegra_tcu_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int tegra_tcu_uart_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static void tegra_tcu_uart_stop_tx(struct uart_port *port) +{ +} + +static void tegra_tcu_write_one(struct tegra_tcu *tcu, u32 value, + unsigned int count) +{ + void *msg; + + value |= TCU_MBOX_NUM_BYTES(count); + msg = (void *)(unsigned long)value; + mbox_send_message(tcu->tx, msg); +} + +static void tegra_tcu_write(struct tegra_tcu *tcu, const char *s, + unsigned int count) +{ + unsigned int written = 0, i = 0; + bool insert_nl = false; + u32 value = 0; + + while (i < count) { + if (insert_nl) { + value |= TCU_MBOX_BYTE(written++, '\n'); + insert_nl = false; + i++; + } else if (s[i] == '\n') { + value |= TCU_MBOX_BYTE(written++, '\r'); + insert_nl = true; + } else { + value |= TCU_MBOX_BYTE(written++, s[i++]); + } + + if (written == 3) { + tegra_tcu_write_one(tcu, value, 3); + value = written = 0; + } + } + + if (written) + tegra_tcu_write_one(tcu, value, written); +} + +static void tegra_tcu_uart_start_tx(struct uart_port *port) +{ + struct tegra_tcu *tcu = port->private_data; + struct circ_buf *xmit = &port->state->xmit; + unsigned long count; + + for (;;) { + count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + if (!count) + break; + + tegra_tcu_write(tcu, &xmit->buf[xmit->tail], count); + xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); + } + + uart_write_wakeup(port); +} + +static void tegra_tcu_uart_stop_rx(struct uart_port *port) +{ +} + +static void tegra_tcu_uart_break_ctl(struct uart_port *port, int ctl) +{ +} + +static int tegra_tcu_uart_startup(struct uart_port *port) +{ + return 0; +} + +static void tegra_tcu_uart_shutdown(struct uart_port *port) +{ +} + +static void tegra_tcu_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +{ +} + +static const struct uart_ops tegra_tcu_uart_ops = { + .tx_empty = tegra_tcu_uart_tx_empty, + .set_mctrl = tegra_tcu_uart_set_mctrl, + .get_mctrl = tegra_tcu_uart_get_mctrl, + .stop_tx = tegra_tcu_uart_stop_tx, + .start_tx = tegra_tcu_uart_start_tx, + .stop_rx = tegra_tcu_uart_stop_rx, + .break_ctl = tegra_tcu_uart_break_ctl, + .startup = tegra_tcu_uart_startup, + .shutdown = tegra_tcu_uart_shutdown, + .set_termios = tegra_tcu_uart_set_termios, +}; + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) +static void tegra_tcu_console_write(struct console *cons, const char *s, + unsigned int count) +{ + struct tegra_tcu *tcu = container_of(cons, struct tegra_tcu, console); + + tegra_tcu_write(tcu, s, count); +} + +static int tegra_tcu_console_setup(struct console *cons, char *options) +{ + return 0; +} +#endif + +static void tegra_tcu_receive(struct mbox_client *cl, void *msg) +{ + struct tegra_tcu *tcu = container_of(cl, struct tegra_tcu, rx_client); + struct tty_port *port = &tcu->port.state->port; + u32 value = (u32)(unsigned long)msg; + unsigned int num_bytes, i; + + num_bytes = TCU_MBOX_NUM_BYTES_V(value); + + for (i = 0; i < num_bytes; i++) + tty_insert_flip_char(port, TCU_MBOX_BYTE_V(value, i), + TTY_NORMAL); + + tty_flip_buffer_push(port); +} + +static int tegra_tcu_probe(struct platform_device *pdev) +{ + struct uart_port *port; + struct tegra_tcu *tcu; + int err; + + tcu = devm_kzalloc(&pdev->dev, sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->tx_client.dev = &pdev->dev; + tcu->tx_client.tx_block = true; + tcu->tx_client.tx_tout = 10000; + tcu->rx_client.dev = &pdev->dev; + tcu->rx_client.rx_callback = tegra_tcu_receive; + + tcu->tx = mbox_request_channel_byname(&tcu->tx_client, "tx"); + if (IS_ERR(tcu->tx)) { + err = PTR_ERR(tcu->tx); + dev_err(&pdev->dev, "failed to get tx mailbox: %d\n", err); + return err; + } + + tcu->rx = mbox_request_channel_byname(&tcu->rx_client, "rx"); + if (IS_ERR(tcu->rx)) { + err = PTR_ERR(tcu->rx); + dev_err(&pdev->dev, "failed to get rx mailbox: %d\n", err); + goto free_tx; + } + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + /* setup the console */ + strcpy(tcu->console.name, "ttyTCU"); + tcu->console.device = uart_console_device; + tcu->console.flags = CON_PRINTBUFFER | CON_ANYTIME; + tcu->console.index = -1; + tcu->console.write = tegra_tcu_console_write; + tcu->console.setup = tegra_tcu_console_setup; + tcu->console.data = &tcu->driver; +#endif + + /* setup the driver */ + tcu->driver.owner = THIS_MODULE; + tcu->driver.driver_name = "tegra-tcu"; + tcu->driver.dev_name = "ttyTCU"; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + tcu->driver.cons = &tcu->console; +#endif + tcu->driver.nr = 1; + + err = uart_register_driver(&tcu->driver); + if (err) { + dev_err(&pdev->dev, "failed to register UART driver: %d\n", + err); + goto free_rx; + } + + /* setup the port */ + port = &tcu->port; + spin_lock_init(&port->lock); + port->dev = &pdev->dev; + port->type = PORT_TEGRA_TCU; + port->ops = &tegra_tcu_uart_ops; + port->fifosize = 1; + port->iotype = UPIO_MEM; + port->flags = UPF_BOOT_AUTOCONF; + port->private_data = tcu; + + err = uart_add_one_port(&tcu->driver, port); + if (err) { + dev_err(&pdev->dev, "failed to add UART port: %d\n", err); + goto unregister_uart; + } + + platform_set_drvdata(pdev, tcu); +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + register_console(&tcu->console); +#endif + + return 0; + +unregister_uart: + uart_unregister_driver(&tcu->driver); +free_rx: + mbox_free_channel(tcu->rx); +free_tx: + mbox_free_channel(tcu->tx); + + return err; +} + +static int tegra_tcu_remove(struct platform_device *pdev) +{ + struct tegra_tcu *tcu = platform_get_drvdata(pdev); + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + unregister_console(&tcu->console); +#endif + uart_remove_one_port(&tcu->driver, &tcu->port); + uart_unregister_driver(&tcu->driver); + mbox_free_channel(tcu->rx); + mbox_free_channel(tcu->tx); + + return 0; +} + +static const struct of_device_id tegra_tcu_match[] = { + { .compatible = "nvidia,tegra194-tcu" }, + { } +}; + +static struct platform_driver tegra_tcu_driver = { + .driver = { + .name = "tegra-tcu", + .of_match_table = tegra_tcu_match, + }, + .probe = tegra_tcu_probe, + .remove = tegra_tcu_remove, +}; +module_platform_driver(tegra_tcu_driver); + +MODULE_AUTHOR("Mikko Perttunen "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("NVIDIA Tegra Combined UART driver"); diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index dce5f9dae121..69883c32cb98 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -79,6 +79,9 @@ /* Nuvoton UART */ #define PORT_NPCM 40 +/* NVIDIA Tegra Combined UART */ +#define PORT_TEGRA_TCU 41 + /* Intel EG20 */ #define PORT_PCH_8LINE 44 #define PORT_PCH_2LINE 45 From patchwork Fri Oct 26 11:16:37 2018 Content-Type: text/plain; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id y195-v6sm4485038wme.22.2018.10.26.04.16.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:54 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/9] arm64: tegra: Add nodes for TCU on Tegra194 Date: Fri, 26 Oct 2018 13:16:37 +0200 Message-Id: <20181026111638.10759-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 ++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..521d13be0457 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -340,10 +340,35 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x03c00000 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + reg = <0x0c150000 0xa0000>; + interrupts = , + , + , + ; + /* + * Shared interrupt 0 is routed only to AON/SPE, so + * we only have 4 shared interrupts for the CCPLEX. + */ + interrupt-names = "shared1", "shared2", "shared3", "shared4"; #mbox-cells = <2>; }; @@ -531,6 +556,13 @@ method = "smc"; }; + tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = X-Patchwork-Id: 989544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aT+X5+5n"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42hM054WBwz9sDF for ; Fri, 26 Oct 2018 22:17:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727778AbeJZTxl (ORCPT ); Fri, 26 Oct 2018 15:53:41 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:34199 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727758AbeJZTxk (ORCPT ); Fri, 26 Oct 2018 15:53:40 -0400 Received: by mail-wm1-f68.google.com with SMTP id f1-v6so3976304wmg.1; Fri, 26 Oct 2018 04:16:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QGIL//nMYgHHZ4GYaDWliMktQ6b/Y8DmGZjHhB9Vabs=; b=aT+X5+5n+Khef+VodO4SNQNxSz1lZ1cCq8xACFcpM/UNyM1170cbq7vSve6aHR2iYv NuJFGQ/kmuDTt8TUePTHfjPMriDBageC/dh8yAo9voZs9nU6J+EPqScXuKw1FXIiQosp ErjjGk6wMm2TiSUzsc1UmM3KQskuV2MMnuQcWbzObPLUNuQrBmjhL2Ib8IZ+lL+okXPD X/LkyqJjtKlAsGgaCkn0yAwVE0nXRw3EddQR1uuNSYrxO4HH8GgwIy1wu2tbetXVBY9x dOe7hOlh6DXkfIOpM4ri0R2YvMhtLz+CCaz4LEQ5b4gNPLBWqaKBlZ2151SFVkTaqi8N vn0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QGIL//nMYgHHZ4GYaDWliMktQ6b/Y8DmGZjHhB9Vabs=; b=Y8yCk2o8hfE0fCrv5CMJfBuB1l3+QRNU5DMY1tqHwUnBPUhzr/hCVVZWLYf9L6q9da EhppJD/YmU/VjXq10I7Otj/66yMWp3p5aD7J+VqRcXynFklpg0EHs7nNuvnu530cSTTx Xxd02lsuA912pqufKaTvCsYvONYsnnyz2Q6unFGhJrp/lFFaH+ZVkxTbBks/sxiGKZk8 Zlbgy84GiQhj1fs6f7et6TNtkvAUnvUuWecXtYOEEXBCmMJ+7x9DmExElaNlam9swWYI RNgHnKxdzpSGQjIkdpIYEFyOixtXvrPbUxbPjS+7osYUGStvD2Tr4B9Q4EQCskCiVaFF dxXg== X-Gm-Message-State: AGRZ1gLaOb9q7vI2g5jJsD4uWDqgr7bH2pjFBAjLSpFoZFh0XqgF8Pov gHPXS+fYC5xvd8GP3ibPTXU= X-Google-Smtp-Source: AJdET5eUk5FWj/86ftupZB1zWrF/f79b3bdaiBZplckhB5viEx5odnwOl8Z2rPmv8lC07wOxxrdwkg== X-Received: by 2002:a1c:890b:: with SMTP id l11-v6mr2855358wmd.151.1540552616866; Fri, 26 Oct 2018 04:16:56 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id c2-v6sm8553896wrt.77.2018.10.26.04.16.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:56 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/9] arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888 Date: Fri, 26 Oct 2018 13:16:38 +0200 Message-Id: <20181026111638.10759-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen The Tegra Combined UART is the proper primary serial port on P2888, so use it. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 57d3f00464ce..fcbe2a88f8db 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -10,7 +10,7 @@ aliases { sdhci0 = "/cbb/sdhci@3460000"; sdhci1 = "/cbb/sdhci@3400000"; - serial0 = &uartb; + serial0 = &tcu; i2c0 = "/bpmp/i2c"; i2c1 = "/cbb/i2c@3160000"; i2c2 = "/cbb/i2c@c240000";