From patchwork Tue Oct 23 16:12:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 988263 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="MQ2Wig8y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42fdh64ltCz9sBk for ; Wed, 24 Oct 2018 03:12:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728180AbeJXAgS (ORCPT ); Tue, 23 Oct 2018 20:36:18 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:44914 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726970AbeJXAgS (ORCPT ); Tue, 23 Oct 2018 20:36:18 -0400 Received: by mail-pf1-f196.google.com with SMTP id r9-v6so905692pff.11 for ; Tue, 23 Oct 2018 09:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=1i2lznVyglXGUJdFbyOeaEkfvd6J8yKfE652P5VFc1U=; b=MQ2Wig8y8nsZc8ub8dy2kA61PJ5KOBypJ+sIhKmOvBfNE6cDiR3D0X1/rTel7pg3wT 99lXS1kyLWteGQWnQyr36DMEIl4J42/7WTN651LPxRQf3gpxLpyertp6l2H9M8FjXHDA DRrFUDA3bukw6atwYxAsuWzZzWVbbvMl0PYpQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=1i2lznVyglXGUJdFbyOeaEkfvd6J8yKfE652P5VFc1U=; b=FUsSyLZuBK0grv9HRhLJJcWWCH7vIaUmh7CjY0PmO5DJej5LTGUMijJJNLpR8pJqq+ FsVCJyFOnZqGMVG4tcedieqO23U/GAC3ry+odDc+cyn1SlXo/ni99X9vyCLx679KLfrY 3wUY0gPVWR0W+0JIperexiEzA7Lro+JR4JAD0SUqOQ9ZKHVqbQA6MU9MiwBvgNJd4hZe YmTqQIdusVnaPMKz3joFbD6Qhu6FOfbPw+vJXvO7Yq9zUcyYPEVIGm62TkddI+EblFsz k5ixtg6e7KBo5bQ/0g17dkrvxLJeZV2pI1EaK1XmpRz/Xc8Ykx3IazGRqaUIvH9++7xZ rn+g== X-Gm-Message-State: AGRZ1gLj/vP3W2uiohFBBZ7VKymRbLhLzfBEMcQbeIcMsplZF19k6gwz qevMpMUSWfSY7fzTsvCIQx55XFe632Q= X-Google-Smtp-Source: AJdET5ei1Xh0Jr57Y+8ahXuHjX6PvN6g8BqGc0gI9s0LlKHMFabDUapOsDuZyA4D6J8QFTQgYMIF6Q== X-Received: by 2002:a63:314c:: with SMTP id x73mr7782810pgx.323.1540311136170; Tue, 23 Oct 2018 09:12:16 -0700 (PDT) Received: from localhost.localdomain ([27.7.51.1]) by smtp.gmail.com with ESMTPSA id u21-v6sm2771449pfa.176.2018.10.23.09.12.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Oct 2018 09:12:15 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Jagan Teki Subject: [PATCH] arm64: dts: allwinner: a64: Add device node for Mali-400 GPU Date: Tue, 23 Oct 2018 21:42:03 +0530 Message-Id: <20181023161203.2956-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Allwinner A64 has Mali-400MP2. All interrupt lines are mentioned in the manual so used the same. Used 408MHz as assigned clock rate used by BSP, so used the same as well. Signed-off-by: Jagan Teki --- Note: - Modules was able to load it on 4.19. .../bindings/gpu/arm,mali-utgard.txt | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 63cd91176a68..a0ee62a5b221 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -11,6 +11,7 @@ Required properties: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + allwinner,sun8i-h3-mali + + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index f82e6b165d57..2db3aa151902 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -812,6 +812,31 @@ }; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <408000000>; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>,