From patchwork Fri Oct 19 17:15:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan O'Donovan X-Patchwork-Id: 986941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=emutex.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42cCV02sCQz9sjG for ; Sat, 20 Oct 2018 04:25:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728005AbeJTBcI (ORCPT ); Fri, 19 Oct 2018 21:32:08 -0400 Received: from mr41.theemaillaundry.net ([109.169.43.45]:38086 "EHLO mr41.theemaillaundry.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727741AbeJTBcH (ORCPT ); Fri, 19 Oct 2018 21:32:07 -0400 Received: from mr40.theemaillaundry.net (mr40.theemaillaundry.net [109.169.43.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mr41.theemaillaundry.net (Postfix) with ESMTPS id 10A9A204B8; Fri, 19 Oct 2018 18:16:06 +0100 (IST) Received: from mr30.theemaillaundry.net (mr30.theemaillaundry.net [78.46.72.43]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mr40.theemaillaundry.net (Postfix) with ESMTPS id 802703FE25; Fri, 19 Oct 2018 18:16:04 +0100 (IST) Received: from localhost (localhost [127.0.0.1]) by mr30.theemaillaundry.net (Postfix) with ESMTP id 00BB7240867; Fri, 19 Oct 2018 18:16:03 +0100 (IST) X-Amavis-Modified: Mail body modified (using disclaimer) - mr30.theemaillaundry.net X-Virus-Scanned: amavisd-new at theemaillaundry.net Received: from mr30.theemaillaundry.net ([127.0.0.1]) by localhost (mr30.theemaillaundry.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XQZAOPiixlD5; Fri, 19 Oct 2018 18:16:01 +0100 (IST) Received: from statler.emutex.com (unknown [92.51.199.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mr30.theemaillaundry.net (Postfix) with ESMTPS id 76D28240ED8; Fri, 19 Oct 2018 18:16:00 +0100 (IST) Received: from [10.10.68.81] (helo=dan-Latitude-E5450.emutex.com) by statler.emutex.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.84) (envelope-from ) id 1gDYNS-0005CM-SE; Fri, 19 Oct 2018 18:15:59 +0100 From: Dan O'Donovan To: linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Mika Westerberg , Heikki Krogerus , Lee Jones , Linus Walleij , Jacek Anaszewski , Pavel Machek , linux-gpio@vger.kernel.org, linux-leds@vger.kernel.org, Carlos Iglesias , Javier Arteaga , Dan O'Donovan Subject: [PATCH v2 1/3] mfd: upboard: Add UP2 platform controller driver Date: Fri, 19 Oct 2018 18:15:32 +0100 Message-Id: <1539969334-24577-2-git-send-email-dan@emutex.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539969334-24577-1-git-send-email-dan@emutex.com> References: <20180421085009.28773-1-javier@emutex.com> <1539969334-24577-1-git-send-email-dan@emutex.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Javier Arteaga UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It features a MAX 10 FPGA that routes lines from both SoC and on-board devices to two I/O headers: +------------------------+ | 40-pin RPi-like header | +------| (HAT) | | +------------------------+ +-------+ +--------+ | | | | +------------------------+ | SoC |----| FPGA |-----| Custom UP2 pin header | | | | | | (EXHAT) | +-------+ +--------+ +------------------------+ | +------* On-board devices: LED, VLS... This is intended to enable vendor-specific applications to customize I/O header pinout, as well as include low-latency functionality. It also performs voltage level translation between the SoC (1.8V) and HAT header (3.3V). Out of the box, this block implements a platform controller with a GPIO-bitbanged control interface. It's enumerated by ACPI and provides registers to control: - Configuration of all FPGA-routed header lines. These can be driven SoC-to-header, header-to-SoC or set in high impedance. - On-board LEDs and enable lines for other platform devices. Add core support for this platform controller as a MFD device, exposing these registers as a regmap. Acked-by: Linus Walleij Signed-off-by: Javier Arteaga Signed-off-by: Dan O'Donovan --- drivers/mfd/Kconfig | 17 +++ drivers/mfd/Makefile | 1 + drivers/mfd/upboard.c | 344 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/upboard.h | 44 ++++++ 4 files changed, 406 insertions(+) create mode 100644 drivers/mfd/upboard.c create mode 100644 include/linux/mfd/upboard.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 11841f4..4f91474 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1855,6 +1855,23 @@ config MFD_STM32_TIMERS for PWM and IIO Timer. This driver allow to share the registers between the others drivers. +config MFD_UPBOARD + tristate "UP Squared" + depends on ACPI + depends on GPIOLIB + select MFD_CORE + select REGMAP + help + If you say yes here you get support for the platform controller + of the UP Squared single-board computer. + + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the + functionality of the device. + + This driver can also be built as a module. If so, the module + will be called "upboard". + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 5856a94..470f667 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -241,3 +241,4 @@ obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o +obj-$(CONFIG_MFD_UPBOARD) += upboard.o diff --git a/drivers/mfd/upboard.c b/drivers/mfd/upboard.c new file mode 100644 index 0000000..6b3522a --- /dev/null +++ b/drivers/mfd/upboard.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// UP Board platform controller driver +// +// Copyright (c) 2018, Emutex Ltd. +// +// Author: Javier Arteaga +// + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UPBOARD_FW_BUILD_SHIFT 12 +#define UPBOARD_FW_MAJOR_SHIFT 8 +#define UPBOARD_FW_MINOR_SHIFT 4 +#define UPBOARD_FW_PATCH_SHIFT 0 + +#define UPBOARD_FW_BUILD(id) (((id) >> UPBOARD_FW_BUILD_SHIFT) & 0x0f) +#define UPBOARD_FW_MAJOR(id) (((id) >> UPBOARD_FW_MAJOR_SHIFT) & 0x0f) +#define UPBOARD_FW_MINOR(id) (((id) >> UPBOARD_FW_MINOR_SHIFT) & 0x0f) +#define UPBOARD_FW_PATCH(id) (((id) >> UPBOARD_FW_PATCH_SHIFT) & 0x0f) + +#define AAEON_MANUFACTURER_ID 0x01 +#define SUPPORTED_FW_MAJOR 0x0 + +/* MSb of 8-bit address is an R/W flag */ +#define UPBOARD_ADDRESS_SIZE 8 +#define UPBOARD_READ_FLAG BIT(7) + +enum upboard_id { + UPBOARD_ID_UP2 = 0, +}; + +struct upboard_ddata { + struct gpio_desc *clear_gpio; + struct gpio_desc *strobe_gpio; + struct gpio_desc *datain_gpio; + struct gpio_desc *dataout_gpio; + const struct regmap_config *regmapconf; + const struct mfd_cell *cells; + size_t ncells; +}; + +/* + * UP boards include a platform controller with a proprietary GPIO-bitbanged + * control interface to access its configuration registers. + * + * The following macros and functions implement the read/write handlers for + * that interface, to provide a regmap-based abstraction for the controller. + */ + +#define set_clear(u, x) gpiod_set_value((u)->clear_gpio, (x)) +#define set_strobe(u, x) gpiod_set_value((u)->strobe_gpio, (x)) +#define set_datain(u, x) gpiod_set_value((u)->datain_gpio, (x)) +#define get_dataout(u) gpiod_get_value((u)->dataout_gpio) + +static void __reg_io_start(const struct upboard_ddata * const ddata) +{ + /* + * CLEAR signal must be pulsed low before any register access. + * This resets internal counters in the controller and marks + * the start of a new register access. + */ + set_clear(ddata, 0); + set_clear(ddata, 1); +} + +static void __reg_io_end(const struct upboard_ddata * const ddata) +{ + /* + * STROBE signal must be cycled again to mark the end of a register + * access. Partial register accesses are discarded harmlessly + * by the controller if this final strobe cycle is not sent + */ + set_strobe(ddata, 0); + set_strobe(ddata, 1); +} + +static void __reg_io_write(const struct upboard_ddata * const ddata, + unsigned int size, unsigned int val) +{ + int i; + + /* + * DATAIN is latched on each rising edge of the STROBE signal. + * Data (register address or value) is sent MSb first. + */ + for (i = size - 1; i >= 0; i--) { + set_strobe(ddata, 0); + set_datain(ddata, (val >> i) & 0x1); + set_strobe(ddata, 1); + } +} + +static void __reg_io_read(const struct upboard_ddata * const ddata, + unsigned int size, unsigned int *val) +{ + int i; + + /* + * DATAOUT is latched on on each rising edge of the STROBE signal. + * Data (register value) is received MSb first. + */ + *val = 0; + for (i = size - 1; i >= 0; i--) { + set_strobe(ddata, 0); + set_strobe(ddata, 1); + *val |= get_dataout(ddata) << i; + } +} + +static int upboard_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + const struct upboard_ddata * const ddata = context; + + __reg_io_start(ddata); + __reg_io_write(ddata, UPBOARD_ADDRESS_SIZE, reg | UPBOARD_READ_FLAG); + __reg_io_read(ddata, UPBOARD_REGISTER_SIZE, val); + __reg_io_end(ddata); + + return 0; +} + +static int upboard_reg_write(void *context, unsigned int reg, unsigned int val) +{ + const struct upboard_ddata * const ddata = context; + + __reg_io_start(ddata); + __reg_io_write(ddata, UPBOARD_ADDRESS_SIZE, reg); + __reg_io_write(ddata, UPBOARD_REGISTER_SIZE, val); + __reg_io_end(ddata); + + return 0; +} + +/* UP Squared */ + +static const struct regmap_range upboard_up2_readable_ranges[] = { + regmap_reg_range(UPBOARD_REG_PLATFORM_ID, UPBOARD_REG_FIRMWARE_ID), + regmap_reg_range(UPBOARD_REG_FUNC_EN0, UPBOARD_REG_FUNC_EN1), + regmap_reg_range(UPBOARD_REG_GPIO_EN0, UPBOARD_REG_GPIO_EN2), + regmap_reg_range(UPBOARD_REG_GPIO_DIR0, UPBOARD_REG_GPIO_DIR2), +}; + +static const struct regmap_range upboard_up2_writable_ranges[] = { + regmap_reg_range(UPBOARD_REG_FUNC_EN0, UPBOARD_REG_FUNC_EN1), + regmap_reg_range(UPBOARD_REG_GPIO_EN0, UPBOARD_REG_GPIO_EN2), + regmap_reg_range(UPBOARD_REG_GPIO_DIR0, UPBOARD_REG_GPIO_DIR2), +}; + +static const struct regmap_access_table upboard_up2_readable_table = { + .yes_ranges = upboard_up2_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(upboard_up2_readable_ranges), +}; + +static const struct regmap_access_table upboard_up2_writable_table = { + .yes_ranges = upboard_up2_writable_ranges, + .n_yes_ranges = ARRAY_SIZE(upboard_up2_writable_ranges), +}; + +static const struct regmap_config upboard_up2_regmap_config = { + .reg_bits = UPBOARD_ADDRESS_SIZE, + .val_bits = UPBOARD_REGISTER_SIZE, + .max_register = UPBOARD_REG_MAX, + .reg_read = upboard_reg_read, + .reg_write = upboard_reg_write, + .fast_io = false, + .cache_type = REGCACHE_RBTREE, + .rd_table = &upboard_up2_readable_table, + .wr_table = &upboard_up2_writable_table, +}; + +static const struct mfd_cell upboard_up2_mfd_cells[] = { + { + .name = "upboard-led", + .id = 0, + }, + { + .name = "upboard-led", + .id = 1, + }, + { + .name = "upboard-led", + .id = 2, + }, + { + .name = "upboard-led", + .id = 3, + }, + { + .name = "upboard-pinctrl" + }, +}; + +static int upboard_init_gpio(struct device *dev) +{ + struct upboard_ddata *ddata = dev_get_drvdata(dev); + struct gpio_desc *enable_gpio; + + ddata->clear_gpio = devm_gpiod_get(dev, "clear", GPIOD_OUT_LOW); + if (IS_ERR(ddata->clear_gpio)) + return PTR_ERR(ddata->clear_gpio); + + ddata->strobe_gpio = devm_gpiod_get(dev, "strobe", GPIOD_OUT_LOW); + if (IS_ERR(ddata->strobe_gpio)) + return PTR_ERR(ddata->strobe_gpio); + + ddata->datain_gpio = devm_gpiod_get(dev, "datain", GPIOD_OUT_LOW); + if (IS_ERR(ddata->datain_gpio)) + return PTR_ERR(ddata->datain_gpio); + + ddata->dataout_gpio = devm_gpiod_get(dev, "dataout", GPIOD_IN); + if (IS_ERR(ddata->dataout_gpio)) + return PTR_ERR(ddata->dataout_gpio); + + /* External I/O signals are gated by ENABLE - ensure this is high */ + enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(enable_gpio)) + return PTR_ERR(enable_gpio); + + return 0; +} + +static int upboard_check_supported(struct device *dev, struct regmap *regmap) +{ + uint8_t manufacturer_id, build, major, minor, patch; + unsigned int platform_id, firmware_id; + int ret; + + ret = regmap_read(regmap, UPBOARD_REG_PLATFORM_ID, &platform_id); + if (ret) + return ret; + + manufacturer_id = platform_id & 0xff; + if (manufacturer_id != AAEON_MANUFACTURER_ID) { + dev_err(dev, + "unsupported FPGA firmware from manufacturer 0x%02x", + manufacturer_id); + return -ENODEV; + } + + ret = regmap_read(regmap, UPBOARD_REG_FIRMWARE_ID, &firmware_id); + if (ret) + return ret; + + build = UPBOARD_FW_BUILD(firmware_id); + major = UPBOARD_FW_MAJOR(firmware_id); + minor = UPBOARD_FW_MINOR(firmware_id); + patch = UPBOARD_FW_PATCH(firmware_id); + if (major != SUPPORTED_FW_MAJOR) { + dev_err(dev, "unsupported FPGA firmware v%u.%u.%u.%u", + major, minor, patch, build); + return -ENODEV; + } + + dev_dbg(dev, "supported FPGA firmware v%u.%u.%u.%u", + major, minor, patch, build); + return 0; +} + +static const struct acpi_device_id upboard_acpi_match[] = { + { "AANT0F01", (kernel_ulong_t)UPBOARD_ID_UP2 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, upboard_acpi_match); + +static int upboard_match_device(struct device *dev) +{ + struct upboard_ddata *ddata = dev_get_drvdata(dev); + const struct acpi_device_id *id; + + id = acpi_match_device(upboard_acpi_match, dev); + if (!id) + return -ENODEV; + + switch (id->driver_data) { + case UPBOARD_ID_UP2: + ddata->regmapconf = &upboard_up2_regmap_config; + ddata->cells = upboard_up2_mfd_cells; + ddata->ncells = ARRAY_SIZE(upboard_up2_mfd_cells); + break; + default: + dev_err(dev, "unsupported ID %lu\n", id->driver_data); + return -EINVAL; + } + + return 0; +} + +static int upboard_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct upboard_ddata *ddata; + struct regmap *regmap; + int ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + dev_set_drvdata(dev, ddata); + + ret = upboard_match_device(dev); + if (ret) + return ret; + + regmap = devm_regmap_init(dev, NULL, ddata, ddata->regmapconf); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = upboard_init_gpio(dev); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to init GPIOs: %d", ret); + return ret; + } + + ret = upboard_check_supported(dev, regmap); + if (ret) + return ret; + + return devm_mfd_add_devices(dev, 0, ddata->cells, ddata->ncells, + NULL, 0, NULL); +} + +static struct platform_driver upboard_driver = { + .probe = upboard_probe, + .driver = { + .name = "upboard", + .acpi_match_table = upboard_acpi_match, + }, +}; + +module_platform_driver(upboard_driver); + +MODULE_AUTHOR("Javier Arteaga "); +MODULE_DESCRIPTION("UP Board platform controller driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/upboard.h b/include/linux/mfd/upboard.h new file mode 100644 index 0000000..63e677f --- /dev/null +++ b/include/linux/mfd/upboard.h @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// UP Board MFD driver interface +// +// Copyright (c) 2018, Emutex Ltd. +// +// Author: Javier Arteaga +// + +#ifndef __LINUX_MFD_UPBOARD_H +#define __LINUX_MFD_UPBOARD_H + +#define UPBOARD_REGISTER_SIZE 16 + +/** + * enum upboard_reg - addresses for 16-bit controller registers + * + * @UPBOARD_REG_PLATFORM_ID: [RO] BOARD_ID | MANUFACTURER_ID + * @UPBOARD_REG_FIRMWARE_ID: [RO] BUILD | MAJOR | MINOR | PATCH + * @UPBOARD_REG_FUNC_EN0: [RW] Toggles for board functions (bank 0) + * @UPBOARD_REG_FUNC_EN1: [RW] Toggles for board functions (bank 1) + * @UPBOARD_REG_GPIO_EN0: [RW] Hi-Z (0) / enabled (1) GPIO (bank 0) + * @UPBOARD_REG_GPIO_EN1: [RW] Hi-Z (0) / enabled (1) GPIO (bank 1) + * @UPBOARD_REG_GPIO_EN2: [RW] Hi-Z (0) / enabled (1) GPIO (bank 2) + * @UPBOARD_REG_GPIO_DIR0: [RW] SoC- (0) / FPGA- (1) driven GPIO (bank 0) + * @UPBOARD_REG_GPIO_DIR1: [RW] SoC- (0) / FPGA- (1) driven GPIO (bank 1) + * @UPBOARD_REG_GPIO_DIR2: [RW] SoC- (0) / FPGA- (1) driven GPIO (bank 2) + * @UPBOARD_REG_MAX: one past the last valid address + */ +enum upboard_reg { + UPBOARD_REG_PLATFORM_ID = 0x10, + UPBOARD_REG_FIRMWARE_ID = 0x11, + UPBOARD_REG_FUNC_EN0 = 0x20, + UPBOARD_REG_FUNC_EN1 = 0x21, + UPBOARD_REG_GPIO_EN0 = 0x30, + UPBOARD_REG_GPIO_EN1 = 0x31, + UPBOARD_REG_GPIO_EN2 = 0x32, + UPBOARD_REG_GPIO_DIR0 = 0x40, + UPBOARD_REG_GPIO_DIR1 = 0x41, + UPBOARD_REG_GPIO_DIR2 = 0x42, + UPBOARD_REG_MAX, +}; + +#endif /* __LINUX_MFD_UPBOARD_H */ From patchwork Fri Oct 19 17:15:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan O'Donovan X-Patchwork-Id: 986942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=emutex.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42cCV76n7zz9sDK for ; Sat, 20 Oct 2018 04:25:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727875AbeJTBcF (ORCPT ); Fri, 19 Oct 2018 21:32:05 -0400 Received: from mr41.theemaillaundry.net ([109.169.43.45]:38084 "EHLO mr41.theemaillaundry.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727589AbeJTBcF (ORCPT ); Fri, 19 Oct 2018 21:32:05 -0400 X-Greylist: delayed 539 seconds by postgrey-1.27 at vger.kernel.org; Fri, 19 Oct 2018 21:32:03 EDT Received: from mr40.theemaillaundry.net (mr40.theemaillaundry.net [109.169.43.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mr41.theemaillaundry.net (Postfix) with ESMTPS id 1E0AD204BA; Fri, 19 Oct 2018 18:16:06 +0100 (IST) Received: from mr30.theemaillaundry.net (mr30.theemaillaundry.net [78.46.72.43]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mr40.theemaillaundry.net (Postfix) with ESMTPS id 7BED73FE19; Fri, 19 Oct 2018 18:16:04 +0100 (IST) Received: from localhost (localhost [127.0.0.1]) by mr30.theemaillaundry.net (Postfix) with ESMTP id 96CA92416CA; Fri, 19 Oct 2018 18:16:02 +0100 (IST) X-Amavis-Modified: Mail body modified (using disclaimer) - mr30.theemaillaundry.net X-Virus-Scanned: amavisd-new at theemaillaundry.net Received: from mr30.theemaillaundry.net ([127.0.0.1]) by localhost (mr30.theemaillaundry.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M_MtmGFBGKEi; Fri, 19 Oct 2018 18:16:01 +0100 (IST) Received: from statler.emutex.com (unknown [92.51.199.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mr30.theemaillaundry.net (Postfix) with ESMTPS id 801872414F6; Fri, 19 Oct 2018 18:16:01 +0100 (IST) Received: from [10.10.68.81] (helo=dan-Latitude-E5450.emutex.com) by statler.emutex.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.84) (envelope-from ) id 1gDYNT-0005CM-LS; Fri, 19 Oct 2018 18:16:01 +0100 From: Dan O'Donovan To: linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Mika Westerberg , Heikki Krogerus , Lee Jones , Linus Walleij , Jacek Anaszewski , Pavel Machek , linux-gpio@vger.kernel.org, linux-leds@vger.kernel.org, Carlos Iglesias , Javier Arteaga , Dan O'Donovan Subject: [PATCH v2 2/3] leds: upboard: Add LED support Date: Fri, 19 Oct 2018 18:15:33 +0100 Message-Id: <1539969334-24577-3-git-send-email-dan@emutex.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539969334-24577-1-git-send-email-dan@emutex.com> References: <20180421085009.28773-1-javier@emutex.com> <1539969334-24577-1-git-send-email-dan@emutex.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Javier Arteaga Allow userspace to use the on-board LEDs as "upboard::". Acked-by: Pavel Machek Signed-off-by: Javier Arteaga Signed-off-by: Dan O'Donovan --- drivers/leds/Kconfig | 10 +++++ drivers/leds/Makefile | 1 + drivers/leds/leds-upboard.c | 104 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/leds/leds-upboard.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 44097a3..0ed8857 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -756,6 +756,16 @@ config LEDS_NIC78BX To compile this driver as a module, choose M here: the module will be called leds-nic78bx. +config LEDS_UPBOARD + tristate "LED support for the UP Squared" + depends on LEDS_CLASS + depends on MFD_UPBOARD + help + This option enables support for the LEDs on the UP Squared board. + + This driver can also be built as a module. If so, the module + will be called leds-upboard. + comment "LED Triggers" source "drivers/leds/trigger/Kconfig" diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 420b5d2..c85f18f 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o obj-$(CONFIG_LEDS_LM3601X) += leds-lm3601x.o +obj-$(CONFIG_LEDS_UPBOARD) += leds-upboard.o # LED SPI Drivers obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff --git a/drivers/leds/leds-upboard.c b/drivers/leds/leds-upboard.c new file mode 100644 index 0000000..34a6973 --- /dev/null +++ b/drivers/leds/leds-upboard.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// UP Board LED driver +// +// Copyright (c) 2018, Emutex Ltd. +// +// Author: Javier Arteaga +// + +#include +#include +#include +#include +#include +#include +#include + +#define to_upboard_led(cdev) container_of(cdev, struct upboard_led, cdev) + +static const char * const upboard_led_names[] = { + "upboard:blue:", + "upboard:yellow:", + "upboard:green:", + "upboard:red:", +}; + +struct upboard_led { + struct regmap_field *field; + struct led_classdev cdev; +}; + +static enum led_brightness upboard_led_brightness_get(struct led_classdev *cdev) +{ + struct upboard_led *led = to_upboard_led(cdev); + int brightness = 0; + + regmap_field_read(led->field, &brightness); + + return brightness; +} + +static void upboard_led_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + struct upboard_led *led = to_upboard_led(cdev); + + regmap_field_write(led->field, brightness); +} + +static int upboard_led_probe(struct platform_device *pdev) +{ + unsigned int led_index = pdev->id; + struct device *dev = &pdev->dev; + struct acpi_device *adev; + struct upboard_led *led; + struct regmap *regmap; + struct reg_field conf = { + .reg = UPBOARD_REG_FUNC_EN0, + .lsb = led_index, + .msb = led_index, + }; + + adev = ACPI_COMPANION(dev); + if (!adev || strcmp(acpi_device_hid(adev), "AANT0F01")) + return -ENODEV; + + if (led_index >= ARRAY_SIZE(upboard_led_names)) + return -EINVAL; + + if (!dev->parent) + return -EINVAL; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -EINVAL; + + led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL); + if (!led) + return -ENOMEM; + + led->field = devm_regmap_field_alloc(dev, regmap, conf); + if (IS_ERR(led->field)) + return PTR_ERR(led->field); + + led->cdev.max_brightness = 1; + led->cdev.brightness_get = upboard_led_brightness_get; + led->cdev.brightness_set = upboard_led_brightness_set; + led->cdev.name = upboard_led_names[led_index]; + + return devm_led_classdev_register(dev, &led->cdev); +} + +static struct platform_driver upboard_led_driver = { + .driver = { + .name = "upboard-led", + }, +}; + +module_platform_driver_probe(upboard_led_driver, upboard_led_probe); + +MODULE_ALIAS("platform:upboard-led"); +MODULE_AUTHOR("Javier Arteaga "); +MODULE_DESCRIPTION("UP Board LED driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Oct 19 17:15:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan O'Donovan X-Patchwork-Id: 986933 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=emutex.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42cCPh6RJ6z9sDb for ; Sat, 20 Oct 2018 04:21:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727508AbeJTB21 (ORCPT ); Fri, 19 Oct 2018 21:28:27 -0400 Received: from mr33.theemaillaundry.net ([176.9.125.106]:33346 "EHLO mr33.theemaillaundry.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727474AbeJTB20 (ORCPT ); Fri, 19 Oct 2018 21:28:26 -0400 X-Greylist: delayed 317 seconds by postgrey-1.27 at vger.kernel.org; Fri, 19 Oct 2018 21:28:22 EDT Received: from localhost (localhost [127.0.0.1]) by mr33.theemaillaundry.net (Postfix) with ESMTP id 6BBCA51C1CE9; Fri, 19 Oct 2018 18:16:05 +0100 (IST) X-Amavis-Modified: Mail body modified (using disclaimer) - mr33.theemaillaundry.net X-Virus-Scanned: amavisd-new at theemaillaundry.net Received: from mr33.theemaillaundry.net ([127.0.0.1]) by localhost (mr33.theemaillaundry.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XoR9WaBJmkAu; Fri, 19 Oct 2018 18:16:02 +0100 (IST) Received: from statler.emutex.com (unknown [92.51.199.138]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mr33.theemaillaundry.net (Postfix) with ESMTPS id 8739151C10BA; Fri, 19 Oct 2018 18:16:02 +0100 (IST) Received: from [10.10.68.81] (helo=dan-Latitude-E5450.emutex.com) by statler.emutex.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.84) (envelope-from ) id 1gDYNV-0005CM-AQ; Fri, 19 Oct 2018 18:16:01 +0100 From: Dan O'Donovan To: linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Mika Westerberg , Heikki Krogerus , Lee Jones , Linus Walleij , Jacek Anaszewski , Pavel Machek , linux-gpio@vger.kernel.org, linux-leds@vger.kernel.org, Carlos Iglesias , Javier Arteaga , Dan O'Donovan Subject: [PATCH v2 3/3] pinctrl: upboard: Add UP2 pinctrl and gpio driver Date: Fri, 19 Oct 2018 18:15:34 +0100 Message-Id: <1539969334-24577-4-git-send-email-dan@emutex.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539969334-24577-1-git-send-email-dan@emutex.com> References: <20180421085009.28773-1-javier@emutex.com> <1539969334-24577-1-git-send-email-dan@emutex.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Javier Arteaga The UP2 board features a Raspberry Pi compatible pin header (HAT) and a board-specific expansion connector (EXHAT). Both expose assorted functions from either the SoC (such as GPIO, I2C, SPI, UART...) or other on-board devices (ADC, FPGA IP blocks...). These lines are routed through an on-board FPGA. The platform controller in its stock firmware provides register fields to change: - Line enable (FPGA pins enabled / high impedance) - Line direction (SoC driven / FPGA driven) To enable using SoC GPIOs on the pin header, this arrangement requires both configuring the platform controller, and updating the SoC pad registers in sync. Add a frontend pinctrl/GPIO driver that registers a new set of GPIO lines for the header pins. When these are requested, the driver propagates this request to the backend SoC pinctrl/GPIO driver by grabbing a GPIO descriptor for the matching SoC GPIO line. The needed mapping for this is retrieved via ACPI properties. Signed-off-by: Javier Arteaga Signed-off-by: Dan O'Donovan --- drivers/pinctrl/Kconfig | 13 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-upboard.c | 519 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 533 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-upboard.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e86752b..c65438f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -338,6 +338,19 @@ config PINCTRL_OCELOT select GENERIC_PINMUX_FUNCTIONS select REGMAP_MMIO +config PINCTRL_UPBOARD + tristate "UP Squared pinctrl and GPIO driver" + depends on ACPI + depends on MFD_UPBOARD + select PINMUX + help + Pinctrl driver for the pin headers on the UP Squared board. It + handles pin control for lines routed through the on-board FPGA and + propagates changes to the SoC pinctrl to keep them in sync. + + This driver can also be built as a module. If so, the module will be + called pinctrl-upboard. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 46ef9bd..cfe59b7 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o +obj-$(CONFIG_PINCTRL_UPBOARD) += pinctrl-upboard.o obj-y += actions/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ diff --git a/drivers/pinctrl/pinctrl-upboard.c b/drivers/pinctrl/pinctrl-upboard.c new file mode 100644 index 0000000..b74383b --- /dev/null +++ b/drivers/pinctrl/pinctrl-upboard.c @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// UP Board pin controller driver +// +// Copyright (c) 2018, Emutex Ltd. +// +// Authors: Javier Arteaga +// Dan O'Donovan +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" + +struct upboard_pin { + struct regmap_field *func_en; + struct regmap_field *gpio_en; + struct regmap_field *gpio_dir; +}; + +struct upboard_pinctrl { + struct pinctrl_dev *pctldev; + struct gpio_chip chip; + unsigned int nsoc_gpios; + struct gpio_desc **soc_gpios; +}; + +enum upboard_func0_enables { + UPBOARD_I2C0_EN = 8, + UPBOARD_I2C1_EN = 9, +}; + +static const struct reg_field upboard_i2c0_reg = + REG_FIELD(UPBOARD_REG_FUNC_EN0, UPBOARD_I2C0_EN, UPBOARD_I2C0_EN); + +static const struct reg_field upboard_i2c1_reg = + REG_FIELD(UPBOARD_REG_FUNC_EN0, UPBOARD_I2C1_EN, UPBOARD_I2C1_EN); + +#define UPBOARD_BIT_TO_PIN(r, bit) \ + ((r) * UPBOARD_REGISTER_SIZE + (bit)) + +/* + * UP Squared data + */ + +#define UPBOARD_UP2_BIT_TO_PIN(r, id) (UPBOARD_BIT_TO_PIN(r, UPBOARD_UP2_##id)) + +#define UPBOARD_UP2_PIN_ANON(r, bit) \ + { \ + .number = UPBOARD_BIT_TO_PIN(r, bit), \ + } + +#define UPBOARD_UP2_PIN_NAME(r, id) \ + { \ + .number = UPBOARD_UP2_BIT_TO_PIN(r, id), \ + .name = #id, \ + } + +#define UPBOARD_UP2_PIN_FUNC(r, id, data) \ + { \ + .number = UPBOARD_UP2_BIT_TO_PIN(r, id), \ + .name = #id, \ + .drv_data = (void *)(data), \ + } + +enum upboard_up2_reg0_bit { + UPBOARD_UP2_UART1_TXD, + UPBOARD_UP2_UART1_RXD, + UPBOARD_UP2_UART1_RTS, + UPBOARD_UP2_UART1_CTS, + UPBOARD_UP2_GPIO3, + UPBOARD_UP2_GPIO5, + UPBOARD_UP2_GPIO6, + UPBOARD_UP2_GPIO11, + UPBOARD_UP2_EXHAT_LVDS1n, + UPBOARD_UP2_EXHAT_LVDS1p, + UPBOARD_UP2_SPI2_TXD, + UPBOARD_UP2_SPI2_RXD, + UPBOARD_UP2_SPI2_FS1, + UPBOARD_UP2_SPI2_FS0, + UPBOARD_UP2_SPI2_CLK, + UPBOARD_UP2_SPI1_TXD, +}; + +enum upboard_up2_reg1_bit { + UPBOARD_UP2_SPI1_RXD, + UPBOARD_UP2_SPI1_FS1, + UPBOARD_UP2_SPI1_FS0, + UPBOARD_UP2_SPI1_CLK, + UPBOARD_UP2_BIT20, + UPBOARD_UP2_BIT21, + UPBOARD_UP2_BIT22, + UPBOARD_UP2_BIT23, + UPBOARD_UP2_PWM1, + UPBOARD_UP2_PWM0, + UPBOARD_UP2_EXHAT_LVDS0n, + UPBOARD_UP2_EXHAT_LVDS0p, + UPBOARD_UP2_I2C0_SCL, + UPBOARD_UP2_I2C0_SDA, + UPBOARD_UP2_I2C1_SCL, + UPBOARD_UP2_I2C1_SDA, +}; + +enum upboard_up2_reg2_bit { + UPBOARD_UP2_EXHAT_LVDS3n, + UPBOARD_UP2_EXHAT_LVDS3p, + UPBOARD_UP2_EXHAT_LVDS4n, + UPBOARD_UP2_EXHAT_LVDS4p, + UPBOARD_UP2_EXHAT_LVDS5n, + UPBOARD_UP2_EXHAT_LVDS5p, + UPBOARD_UP2_I2S_SDO, + UPBOARD_UP2_I2S_SDI, + UPBOARD_UP2_I2S_WS_SYNC, + UPBOARD_UP2_I2S_BCLK, + UPBOARD_UP2_EXHAT_LVDS6n, + UPBOARD_UP2_EXHAT_LVDS6p, + UPBOARD_UP2_EXHAT_LVDS7n, + UPBOARD_UP2_EXHAT_LVDS7p, + UPBOARD_UP2_EXHAT_LVDS2n, + UPBOARD_UP2_EXHAT_LVDS2p, +}; + +static struct pinctrl_pin_desc upboard_up2_pins[] = { + UPBOARD_UP2_PIN_NAME(0, UART1_TXD), + UPBOARD_UP2_PIN_NAME(0, UART1_RXD), + UPBOARD_UP2_PIN_NAME(0, UART1_RTS), + UPBOARD_UP2_PIN_NAME(0, UART1_CTS), + UPBOARD_UP2_PIN_NAME(0, GPIO3), + UPBOARD_UP2_PIN_NAME(0, GPIO5), + UPBOARD_UP2_PIN_NAME(0, GPIO6), + UPBOARD_UP2_PIN_NAME(0, GPIO11), + UPBOARD_UP2_PIN_NAME(0, EXHAT_LVDS1n), + UPBOARD_UP2_PIN_NAME(0, EXHAT_LVDS1p), + UPBOARD_UP2_PIN_NAME(0, SPI2_TXD), + UPBOARD_UP2_PIN_NAME(0, SPI2_RXD), + UPBOARD_UP2_PIN_NAME(0, SPI2_FS1), + UPBOARD_UP2_PIN_NAME(0, SPI2_FS0), + UPBOARD_UP2_PIN_NAME(0, SPI2_CLK), + UPBOARD_UP2_PIN_NAME(0, SPI1_TXD), + UPBOARD_UP2_PIN_NAME(1, SPI1_RXD), + UPBOARD_UP2_PIN_NAME(1, SPI1_FS1), + UPBOARD_UP2_PIN_NAME(1, SPI1_FS0), + UPBOARD_UP2_PIN_NAME(1, SPI1_CLK), + UPBOARD_UP2_PIN_ANON(1, 4), + UPBOARD_UP2_PIN_ANON(1, 5), + UPBOARD_UP2_PIN_ANON(1, 6), + UPBOARD_UP2_PIN_ANON(1, 7), + UPBOARD_UP2_PIN_NAME(1, PWM1), + UPBOARD_UP2_PIN_NAME(1, PWM0), + UPBOARD_UP2_PIN_NAME(1, EXHAT_LVDS0n), + UPBOARD_UP2_PIN_NAME(1, EXHAT_LVDS0p), + UPBOARD_UP2_PIN_FUNC(1, I2C0_SCL, &upboard_i2c0_reg), + UPBOARD_UP2_PIN_FUNC(1, I2C0_SDA, &upboard_i2c0_reg), + UPBOARD_UP2_PIN_FUNC(1, I2C1_SCL, &upboard_i2c1_reg), + UPBOARD_UP2_PIN_FUNC(1, I2C1_SDA, &upboard_i2c1_reg), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS3n), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS3p), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS4n), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS4p), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS5n), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS5p), + UPBOARD_UP2_PIN_NAME(2, I2S_SDO), + UPBOARD_UP2_PIN_NAME(2, I2S_SDI), + UPBOARD_UP2_PIN_NAME(2, I2S_WS_SYNC), + UPBOARD_UP2_PIN_NAME(2, I2S_BCLK), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS6n), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS6p), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS7n), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS7p), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS2n), + UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS2p), +}; + +static int upboard_get_functions_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static int upboard_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int *num_groups) +{ + *groups = NULL; + *num_groups = 0; + return 0; +} + +static const char *upboard_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return NULL; +} + +static int upboard_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group) +{ + return 0; +} + +static int upboard_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + const struct pin_desc * const pd = pin_desc_get(pctldev, pin); + const struct upboard_pin *p; + int ret; + + if (!pd) + return -EINVAL; + p = pd->drv_data; + + /* if this pin has an associated function bit, disable it first */ + if (p->func_en) { + ret = regmap_field_write(p->func_en, 0); + if (ret) + return ret; + } + + if (p->gpio_en) { + ret = regmap_field_write(p->gpio_en, 1); + if (ret) + return ret; + } + + return 0; +} + +static int upboard_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + const struct pin_desc * const pd = pin_desc_get(pctldev, pin); + const struct upboard_pin *p; + + if (!pd) + return -EINVAL; + p = pd->drv_data; + + return regmap_field_write(p->gpio_dir, input); +} + +static const struct pinmux_ops upboard_pinmux_ops = { + .get_functions_count = upboard_get_functions_count, + .get_function_groups = upboard_get_function_groups, + .get_function_name = upboard_get_function_name, + .set_mux = upboard_set_mux, + .gpio_request_enable = upboard_gpio_request_enable, + .gpio_set_direction = upboard_gpio_set_direction, +}; + +static int upboard_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *upboard_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return NULL; +} + +static const struct pinctrl_ops upboard_pinctrl_ops = { + .get_groups_count = upboard_get_groups_count, + .get_group_name = upboard_get_group_name, +}; + +static struct pinctrl_desc upboard_up2_pinctrl_desc = { + .pins = upboard_up2_pins, + .npins = ARRAY_SIZE(upboard_up2_pins), + .pctlops = &upboard_pinctrl_ops, + .pmxops = &upboard_pinmux_ops, + .owner = THIS_MODULE, +}; + +static struct gpio_desc *upboard_offset_to_soc_gpio(struct gpio_chip *gc, + unsigned int offset) +{ + struct upboard_pinctrl *pctrl = + container_of(gc, struct upboard_pinctrl, chip); + + if (offset + 1 > pctrl->nsoc_gpios || !pctrl->soc_gpios[offset]) + return ERR_PTR(-ENODEV); + + return pctrl->soc_gpios[offset]; +} + +static int upboard_gpio_request(struct gpio_chip *gc, unsigned int offset) +{ + struct upboard_pinctrl *pctrl = + container_of(gc, struct upboard_pinctrl, chip); + struct gpio_desc *desc; + int ret; + + ret = pinctrl_gpio_request(gc->base + offset); + if (ret) + return ret; + + desc = devm_gpiod_get_index(gc->parent, "external", offset, GPIOD_ASIS); + if (IS_ERR(desc)) + return PTR_ERR(desc); + + pctrl->soc_gpios[offset] = desc; + return 0; +} + +static void upboard_gpio_free(struct gpio_chip *gc, unsigned int offset) +{ + struct upboard_pinctrl *pctrl = + container_of(gc, struct upboard_pinctrl, chip); + + if (offset + 1 > pctrl->nsoc_gpios || !pctrl->soc_gpios[offset]) + return; + + devm_gpiod_put(gc->parent, pctrl->soc_gpios[offset]); + pctrl->soc_gpios[offset] = NULL; + + pinctrl_gpio_free(gc->base + offset); +} + +static int upboard_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + struct gpio_desc *desc = upboard_offset_to_soc_gpio(gc, offset); + + if (IS_ERR(desc)) + return PTR_ERR(desc); + + return gpiod_get_direction(desc); +} + +static int upboard_gpio_direction_input(struct gpio_chip *gc, + unsigned int offset) +{ + struct gpio_desc *desc = upboard_offset_to_soc_gpio(gc, offset); + int ret; + + if (IS_ERR(desc)) + return PTR_ERR(desc); + + ret = gpiod_direction_input(desc); + if (ret) + return ret; + + return pinctrl_gpio_direction_input(gc->base + offset); +} + +static int upboard_gpio_direction_output(struct gpio_chip *gc, + unsigned int offset, int value) +{ + struct gpio_desc *desc = upboard_offset_to_soc_gpio(gc, offset); + int ret; + + if (IS_ERR(desc)) + return PTR_ERR(desc); + + ret = pinctrl_gpio_direction_output(gc->base + offset); + if (ret) + return ret; + + return gpiod_direction_output(desc, value); +} + +static int upboard_gpio_get_value(struct gpio_chip *gc, unsigned int offset) +{ + struct gpio_desc *desc = upboard_offset_to_soc_gpio(gc, offset); + + if (IS_ERR(desc)) + return PTR_ERR(desc); + + return gpiod_get_value(desc); +} + +static void upboard_gpio_set_value(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct gpio_desc *desc = upboard_offset_to_soc_gpio(gc, offset); + + if (IS_ERR(desc)) + return; + + gpiod_set_value(desc, value); +} + +static struct gpio_chip upboard_gpio_chip = { + .label = "UP pin controller", + .owner = THIS_MODULE, + .request = upboard_gpio_request, + .free = upboard_gpio_free, + .get_direction = upboard_gpio_get_direction, + .direction_input = upboard_gpio_direction_input, + .direction_output = upboard_gpio_direction_output, + .get = upboard_gpio_get_value, + .set = upboard_gpio_set_value, + .base = -1, +}; + +static struct regmap_field *upboard_field_alloc(struct device *dev, + struct regmap *regmap, + unsigned int base, + unsigned int number) +{ + const unsigned int reg = number / UPBOARD_REGISTER_SIZE; + const unsigned int bit = number % UPBOARD_REGISTER_SIZE; + const struct reg_field field = { + .reg = base + reg, + .msb = bit, + .lsb = bit, + }; + + return devm_regmap_field_alloc(dev, regmap, field); +} + +static int upboard_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pinctrl_desc *pctldesc; + struct upboard_pinctrl *pctrl; + struct upboard_pin *pins; + struct acpi_device *adev; + struct regmap *regmap; + unsigned int i; + int ret; + + adev = ACPI_COMPANION(dev); + if (!adev || strcmp(acpi_device_hid(adev), "AANT0F01")) + return -ENODEV; + + if (!dev->parent) + return -EINVAL; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -EINVAL; + + pctldesc = &upboard_up2_pinctrl_desc; + pctldesc->name = dev_name(dev); + + pins = devm_kzalloc(dev, sizeof(*pins) * pctldesc->npins, GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctldesc->npins; i++) { + struct upboard_pin *pin = &pins[i]; + const struct pinctrl_pin_desc *pd = &pctldesc->pins[i]; + + pin->func_en = NULL; + if (pd->drv_data) { + struct reg_field *field = pd->drv_data; + + pin->func_en = devm_regmap_field_alloc(dev, regmap, + *field); + if (IS_ERR(pin->func_en)) + return PTR_ERR(pin->func_en); + } + + pin->gpio_en = upboard_field_alloc(dev, regmap, + UPBOARD_REG_GPIO_EN0, i); + if (IS_ERR(pin->gpio_en)) + return PTR_ERR(pin->gpio_en); + + pin->gpio_dir = upboard_field_alloc(dev, regmap, + UPBOARD_REG_GPIO_DIR0, i); + if (IS_ERR(pin->gpio_dir)) + return PTR_ERR(pin->gpio_dir); + + ((struct pinctrl_pin_desc *)pd)->drv_data = pin; + } + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->chip = upboard_gpio_chip; + pctrl->chip.parent = dev; + pctrl->chip.ngpio = pctldesc->npins; + + pctrl->nsoc_gpios = gpiod_count(dev, "external"); + pctrl->soc_gpios = devm_kzalloc(dev, + pctrl->nsoc_gpios * sizeof(*pctrl->soc_gpios), + GFP_KERNEL); + if (!pctrl->soc_gpios) + return -ENOMEM; + + pctrl->pctldev = devm_pinctrl_register(dev, pctldesc, pctrl); + if (IS_ERR(pctrl->pctldev)) + return PTR_ERR(pctrl->pctldev); + + ret = devm_gpiochip_add_data(dev, &pctrl->chip, &pctrl->chip); + if (ret) + return ret; + + return gpiochip_add_pin_range(&pctrl->chip, pctldesc->name, 0, 0, + pctldesc->npins); +} + +static struct platform_driver upboard_pinctrl_driver = { + .driver = { + .name = "upboard-pinctrl", + }, +}; + +module_platform_driver_probe(upboard_pinctrl_driver, upboard_pinctrl_probe); + +MODULE_ALIAS("platform:upboard-pinctrl"); +MODULE_AUTHOR("Javier Arteaga "); +MODULE_AUTHOR("Dan O'Donovan "); +MODULE_DESCRIPTION("UP Board pin control and GPIO driver"); +MODULE_LICENSE("GPL v2");