From patchwork Fri Oct 19 01:56:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 986467 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="FA7rgWfJ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42bpvN6RYPz9s8J for ; Fri, 19 Oct 2018 12:57:20 +1100 (AEDT) Received: from localhost ([::1]:46223 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK2Q-0006We-AJ for incoming@patchwork.ozlabs.org; Thu, 18 Oct 2018 21:57:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK1m-0006Uv-Ji for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDK1i-0003wE-Gn for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:38 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40372) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDK1i-0003kU-4R for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:34 -0400 Received: by mail-pg1-x541.google.com with SMTP id n31-v6so15052474pgm.7 for ; Thu, 18 Oct 2018 18:56:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2rYUpwFMdqLRhJkf9zenkRS6T7M+r4Z28gefTS144y4=; b=FA7rgWfJWMV9lrY8pcOU1tPFjd00znnfF8V+Miz5D4u9zAWjYby6BuRshoRmXXG4O/ q4UyofYNJcxC9nIfqXLmQK/P/M2jb2n1rlmLNLAVmplCkNZBdEFfEp/n9LqwKn68SUxr QRGCW9B7O0X33vYYeuJw2JHg7DicfQwk/aEHQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2rYUpwFMdqLRhJkf9zenkRS6T7M+r4Z28gefTS144y4=; b=BzHuRZdc1PwCvM6GciCpvi8wLd918hUh0hFNbC7drpwIiCJHbXvXWAiYj7wAhkTG03 CCRW9Y9XufpbJXOnmOsscPtcSsIdYVkQNEVrICLYE7e4g5YSsKjITQDARCNkr8q+kDkA a8LcnNVkT5EX4Ct2iEhwsDV5VS28pzank71RpmGkhG++SO1t3yp4oQpjs0tJJtxQg8f2 oVzn2RMQZt58RPN5yUamG9Eoky8OKnryMHAZ3dOnlM6weNhy6XutiC3W9VtSc1g1mhoh LYZBjl5I2iJ2/NEREBlZ5h4tx/OrJRTjM1W5nv06iSz1I2a/0ZqBcIJtrdJ8+kITOk5g xvzg== X-Gm-Message-State: ABuFfoh9NvTYOwJYEmlc5esjuLPKEZBBYkdd5WPjvn1FDBrCMMz7I6ZR uTqvwRvshxU9T33sQNFjOEXCJYSlv6c= X-Google-Smtp-Source: ACcGV60Hxz3CmFqGGd19bTtJiFbHFqq30EwdigUyutLcfZgP1FjKAs65K6OfozuJ1iYEw9hRyBa5dA== X-Received: by 2002:a63:f050:: with SMTP id s16-v6mr30761350pgj.403.1539914181558; Thu, 18 Oct 2018 18:56:21 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id p62-v6sm33170892pfp.111.2018.10.18.18.56.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 18:56:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 18:56:15 -0700 Message-Id: <20181019015617.22583-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019015617.22583-1-richard.henderson@linaro.org> References: <20181019015617.22583-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 1/3] target/arm: Remove writefn from TTBR0_EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The EL3 version of this register does not include an ASID, and so the tlb_flush performed by vmsa_ttbr_write is not needed. Reviewed-by: Aaron Lindsay Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e3946562aa..24bbde4f76 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4214,7 +4214,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .access = PL3_RW, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, From patchwork Fri Oct 19 01:56:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 986468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="XmIHtobm"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42bpvP518tz9sCQ for ; Fri, 19 Oct 2018 12:57:21 +1100 (AEDT) Received: from localhost ([::1]:46222 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK2R-0006Wa-7E for incoming@patchwork.ozlabs.org; Thu, 18 Oct 2018 21:57:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK1m-0006Us-Ij for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDK1j-0003y7-C9 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:38 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:42196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDK1i-0003lc-Pt for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:35 -0400 Received: by mail-pl1-x641.google.com with SMTP id c8-v6so15121173plo.9 for ; Thu, 18 Oct 2018 18:56:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7EO8aWpIPQTssuS56XDHtv1ElZWc/DQfneu/cFYaDcY=; b=XmIHtobmPVmEkpp3HdrI0QZGyITwgJMIauW6Mb6nXq9/DNvW8Bge0NJh6Nn5BmGka/ VzC8DlUHs73fBrb5UrKY9bZkogHm8z2jvqG7oz+jw54EbW30bVUej7MyuYKcuEFHW8FL kQCa7Ld3U2vZnGaJgSJXhtNnea4aga82jl0uM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7EO8aWpIPQTssuS56XDHtv1ElZWc/DQfneu/cFYaDcY=; b=aF7aMBaHLb1itX/r0lKNYXzDtDzc6J6xAHxOZf9HzrnP/8kJJaHAqRx9TV92UlZU6+ vt3GXsmmRL82TWVRq7cQduZlGuJ4/SRCuad1uJe9QNqURN/4u2nE7cyw16Qe6N51c0mz 3niYZWHOBoOMIyIQ4N7FulfXjZ5/stFEpijlRDET9lraEWpI5c2+rcGJj48XgDhbH6zr C8Cw9Xf5yqX019MQp1NUwFspWpeUlrrdylJeGvP9tgGbbbd+oMk5RllPjhZPr8oBSrV4 rWxndbuUV9w8fS4JxA57AegoJ9ZXU2WYMnFvHK0ylFlXXNaRe8GE+zJn6Qu15nBJIMGJ zXqQ== X-Gm-Message-State: ABuFfohnd/wsOB2wL4WxWB9RaZ96V0hTNuqhVpzGNMl2AilJD8JmUkhA 4ZVGHGoR0PIzD+UGkuO1DsaZATUaNBc= X-Google-Smtp-Source: ACcGV626/i6ofKzCvr8tvlDUa26vml2NImJ0F4YyjwRDlhlqtjLijjiYqga6qUB1k+NI8oEtC543/w== X-Received: by 2002:a17:902:ac89:: with SMTP id h9-v6mr31354407plr.174.1539914183006; Thu, 18 Oct 2018 18:56:23 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id p62-v6sm33170892pfp.111.2018.10.18.18.56.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 18:56:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 18:56:16 -0700 Message-Id: <20181019015617.22583-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019015617.22583-1-richard.henderson@linaro.org> References: <20181019015617.22583-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 2/3] target/arm: Only flush tlb if ASID changes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since QEMU does not implement ASIDs, changes to the ASID must flush the tlb. However, if the ASID does not change there is no reason to flush. In testing a boot of the Ubuntu installer to the first menu, this reduces the number of flushes by 30%, or nearly 600k instances. Reviewed-by: Aaron Lindsay Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- target/arm/helper.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 24bbde4f76..ed70ac645e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2709,12 +2709,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* 64 bit accesses to the TTBRs can change the ASID and so we - * must flush the TLB. - */ - if (cpreg_field_is_64bit(ri)) { + /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ + if (cpreg_field_is_64bit(ri) && + extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { ARMCPU *cpu = arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); } raw_write(env, ri, value);