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To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:40 +0200 Message-Id: <20181016092252.11664-2-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12539428740579560217 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 01/13] net: ftgmac100: use the BIT() macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/net/ftgmac100.h | 154 ++++++++++++++++++++-------------------- 1 file changed, 77 insertions(+), 77 deletions(-) diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index ffbe1f3e3fa7..439b14d71e4b 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -70,48 +70,48 @@ struct ftgmac100 { /* * Interrupt status register & interrupt enable register */ -#define FTGMAC100_INT_RPKT_BUF (1 << 0) -#define FTGMAC100_INT_RPKT_FIFO (1 << 1) -#define FTGMAC100_INT_NO_RXBUF (1 << 2) -#define FTGMAC100_INT_RPKT_LOST (1 << 3) -#define FTGMAC100_INT_XPKT_ETH (1 << 4) -#define FTGMAC100_INT_XPKT_FIFO (1 << 5) -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) -#define FTGMAC100_INT_XPKT_LOST (1 << 7) -#define FTGMAC100_INT_AHB_ERR (1 << 8) -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) +#define FTGMAC100_INT_RPKT_BUF BIT(0) +#define FTGMAC100_INT_RPKT_FIFO BIT(1) +#define FTGMAC100_INT_NO_RXBUF BIT(2) +#define FTGMAC100_INT_RPKT_LOST BIT(3) +#define FTGMAC100_INT_XPKT_ETH BIT(4) +#define FTGMAC100_INT_XPKT_FIFO BIT(5) +#define FTGMAC100_INT_NO_NPTXBUF BIT(6) +#define FTGMAC100_INT_XPKT_LOST BIT(7) +#define FTGMAC100_INT_AHB_ERR BIT(8) +#define FTGMAC100_INT_PHYSTS_CHG BIT(9) +#define FTGMAC100_INT_NO_HPTXBUF BIT(10) /* * Interrupt timer control register */ #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15) /* * Automatic polling timer control register */ #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12) /* * DMA burst length and arbitration control register */ #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6) #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) -#define FTGMAC100_DBLAC_IFG_INC (1 << 23) +#define FTGMAC100_DBLAC_IFG_INC BIT(23) /* * DMA FIFO status register @@ -122,12 +122,12 @@ struct ftgmac100 { #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31) /* * Receive buffer size register @@ -137,26 +137,26 @@ struct ftgmac100 { /* * MAC control register */ -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) -#define FTGMAC100_MACCR_RM_VLAN (1 << 4) -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) -#define FTGMAC100_MACCR_LOOP_EN (1 << 6) -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) -#define FTGMAC100_MACCR_FULLDUP (1 << 8) -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) -#define FTGMAC100_MACCR_CRC_APD (1 << 10) -#define FTGMAC100_MACCR_RX_RUNT (1 << 12) -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) -#define FTGMAC100_MACCR_RX_ALL (1 << 14) -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) -#define FTGMAC100_MACCR_FAST_MODE (1 << 19) -#define FTGMAC100_MACCR_SW_RST (1 << 31) +#define FTGMAC100_MACCR_TXDMA_EN BIT(0) +#define FTGMAC100_MACCR_RXDMA_EN BIT(1) +#define FTGMAC100_MACCR_TXMAC_EN BIT(2) +#define FTGMAC100_MACCR_RXMAC_EN BIT(3) +#define FTGMAC100_MACCR_RM_VLAN BIT(4) +#define FTGMAC100_MACCR_HPTXR_EN BIT(5) +#define FTGMAC100_MACCR_LOOP_EN BIT(6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) +#define FTGMAC100_MACCR_FULLDUP BIT(8) +#define FTGMAC100_MACCR_GIGA_MODE BIT(9) +#define FTGMAC100_MACCR_CRC_APD BIT(10) +#define FTGMAC100_MACCR_RX_RUNT BIT(12) +#define FTGMAC100_MACCR_JUMBO_LF BIT(13) +#define FTGMAC100_MACCR_RX_ALL BIT(14) +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17) +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) +#define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_SW_RST BIT(31) /* * PHY control register @@ -165,8 +165,8 @@ struct ftgmac100 { #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) -#define FTGMAC100_PHYCR_MIIRD (1 << 26) -#define FTGMAC100_PHYCR_MIIWR (1 << 27) +#define FTGMAC100_PHYCR_MIIRD BIT(26) +#define FTGMAC100_PHYCR_MIIWR BIT(27) /* * PHY data register @@ -185,20 +185,20 @@ struct ftgmac100_txdes { } __attribute__ ((aligned(16))); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) -#define FTGMAC100_TXDES0_EDOTR (1 << 15) -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_TXDES0_LTS (1 << 28) -#define FTGMAC100_TXDES0_FTS (1 << 29) -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) +#define FTGMAC100_TXDES0_EDOTR BIT(15) +#define FTGMAC100_TXDES0_CRC_ERR BIT(19) +#define FTGMAC100_TXDES0_LTS BIT(28) +#define FTGMAC100_TXDES0_FTS BIT(29) +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31) #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) -#define FTGMAC100_TXDES1_LLC (1 << 22) -#define FTGMAC100_TXDES1_TX2FIC (1 << 30) -#define FTGMAC100_TXDES1_TXIC (1 << 31) +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) +#define FTGMAC100_TXDES1_LLC BIT(22) +#define FTGMAC100_TXDES1_TX2FIC BIT(30) +#define FTGMAC100_TXDES1_TXIC BIT(31) /* * Receive descriptor, aligned to 16 bytes @@ -211,20 +211,20 @@ struct ftgmac100_rxdes { } __attribute__ ((aligned(16))); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) -#define FTGMAC100_RXDES0_EDORR (1 << 15) -#define FTGMAC100_RXDES0_MULTICAST (1 << 16) -#define FTGMAC100_RXDES0_BROADCAST (1 << 17) -#define FTGMAC100_RXDES0_RX_ERR (1 << 18) -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_RXDES0_FTL (1 << 20) -#define FTGMAC100_RXDES0_RUNT (1 << 21) -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) -#define FTGMAC100_RXDES0_LRS (1 << 28) -#define FTGMAC100_RXDES0_FRS (1 << 29) -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) +#define FTGMAC100_RXDES0_EDORR BIT(15) +#define FTGMAC100_RXDES0_MULTICAST BIT(16) +#define FTGMAC100_RXDES0_BROADCAST BIT(17) +#define FTGMAC100_RXDES0_RX_ERR BIT(18) +#define FTGMAC100_RXDES0_CRC_ERR BIT(19) +#define FTGMAC100_RXDES0_FTL BIT(20) +#define FTGMAC100_RXDES0_RUNT BIT(21) +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) +#define FTGMAC100_RXDES0_LRS BIT(28) +#define FTGMAC100_RXDES0_FRS BIT(29) +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31) #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) @@ -232,11 +232,11 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) -#define FTGMAC100_RXDES1_LLC (1 << 22) -#define FTGMAC100_RXDES1_DF (1 << 23) -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) +#define FTGMAC100_RXDES1_LLC BIT(22) +#define FTGMAC100_RXDES1_DF BIT(23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) #endif /* __FTGMAC100_H */ From patchwork Tue Oct 16 09:22:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984621 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z91H30nsz9s8r for ; Tue, 16 Oct 2018 20:26:43 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 29B5BC21D72; Tue, 16 Oct 2018 09:26:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52C39C21DDC; Tue, 16 Oct 2018 09:23:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B3F8BC21E0B; Tue, 16 Oct 2018 09:23:40 +0000 (UTC) Received: from 6.mo173.mail-out.ovh.net (6.mo173.mail-out.ovh.net [46.105.43.93]) by lists.denx.de (Postfix) with ESMTPS id 8B63CC21D8E for ; Tue, 16 Oct 2018 09:23:26 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.143.189]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 61467DE925 for ; Tue, 16 Oct 2018 11:23:25 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id AA4474200A8; Tue, 16 Oct 2018 11:23:17 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:41 +0200 Message-Id: <20181016092252.11664-3-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12541399065706924825 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 02/13] net: ftgmac100: use the aligned() macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/net/ftgmac100.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index 439b14d71e4b..9a789e4d5bee 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -182,7 +182,7 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __attribute__ ((aligned(16))); +} __aligned(16); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) #define FTGMAC100_TXDES0_EDOTR BIT(15) @@ -208,7 +208,7 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __attribute__ ((aligned(16))); +} __aligned(16); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) #define FTGMAC100_RXDES0_EDORR BIT(15) From patchwork Tue Oct 16 09:22:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984628 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z95l0JvPz9s8r for ; Tue, 16 Oct 2018 20:30:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 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player731.ha.ovh.net (Postfix) with ESMTPSA id 023D84200AF; Tue, 16 Oct 2018 11:23:24 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:42 +0200 Message-Id: <20181016092252.11664-4-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12543650864901098265 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 03/13] net: ftgmac100: convert to driver model X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The driver is based on the previous one and the code is only adapted to fit the driver model. The support for the Faraday ftgmac100 controller is the same with MAC and MDIO bus support for RGMII/RMII modes. Configuration is updated to enable compile again. At this stage, the driver compiles but is not yet functional. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- It didn't seem necessary to remove the 'dev' argument from the ftgmac100_phy_init() and ftgmac100_phy_reset() function prototypes as the code is completely reworked in patch 5. include/netdev.h | 1 - drivers/net/ftgmac100.c | 223 +++++++++++++++++++++++----------------- drivers/net/Kconfig | 26 +++++ 3 files changed, 157 insertions(+), 93 deletions(-) diff --git a/include/netdev.h b/include/netdev.h index 55001625fb92..0a1a3a2d8da2 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr); int fec_initialize (bd_t *bis); int fecmxc_initialize(bd_t *bis); int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr); -int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); void gt6426x_eth_initialize(bd_t *bis); diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index c996f5f4a167..67a7c73503c5 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -7,15 +7,16 @@ * * (C) Copyright 2010 Andes Technology * Macpaul Lin + * + * Copyright (C) 2018, IBM Corporation. */ -#include -#include +#include +#include #include #include -#include +#include #include -#include #include "ftgmac100.h" @@ -28,7 +29,19 @@ /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ #define PKTBUFSTX 4 /* must be power of 2 */ +/** + * struct ftgmac100_data - private data for the FTGMAC100 driver + * + * @iobase: The base address of the hardware registers + * @txdes: The array of transmit descriptors + * @rxdes: The array of receive descriptors + * @tx_index: Transmit descriptor index in @txdes + * @rx_index: Receive descriptor index in @rxdes + * @phy_addr: The PHY interface address to use + */ struct ftgmac100_data { + struct ftgmac100 *iobase; + ulong txdes_dma; struct ftgmac100_txdes *txdes; ulong rxdes_dma; @@ -41,10 +54,10 @@ struct ftgmac100_data { /* * struct mii_bus functions */ -static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, - int regnum) +static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr, + int regnum) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100 *ftgmac100 = priv->iobase; int phycr; int i; @@ -76,10 +89,10 @@ static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, return -1; } -static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, - int regnum, u16 value) +static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr, + int regnum, u16 value) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100 *ftgmac100 = priv->iobase; int phycr; int data; int i; @@ -114,9 +127,10 @@ static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, return -1; } -int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) +int ftgmac100_phy_read(struct ftgmac100_data *priv, int addr, int reg, + u16 *value) { - *value = ftgmac100_mdiobus_read(dev , addr, reg); + *value = ftgmac100_mdiobus_read(priv, addr, reg); if (*value == -1) return -1; @@ -124,31 +138,31 @@ int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) return 0; } -int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) +int ftgmac100_phy_write(struct ftgmac100_data *priv, int addr, int reg, + u16 value) { - if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) + if (ftgmac100_mdiobus_write(priv, addr, reg, value) == -1) return -1; return 0; } -static int ftgmac100_phy_reset(struct eth_device *dev) +static int ftgmac100_phy_reset(struct ftgmac100_data *priv, struct udevice *dev) { - struct ftgmac100_data *priv = dev->priv; int i; u16 status, adv; adv = ADVERTISE_CSMA | ADVERTISE_ALL; - ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); + ftgmac100_phy_write(priv, priv->phy_addr, MII_ADVERTISE, adv); printf("%s: Starting autonegotiation...\n", dev->name); - ftgmac100_phy_write(dev, priv->phy_addr, - MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + ftgmac100_phy_write(priv, priv->phy_addr, + MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); for (i = 0; i < 100000 / 100; i++) { - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + ftgmac100_phy_read(priv, priv->phy_addr, MII_BMSR, &status); if (status & BMSR_ANEGCOMPLETE) break; @@ -166,19 +180,17 @@ static int ftgmac100_phy_reset(struct eth_device *dev) return 1; } -static int ftgmac100_phy_init(struct eth_device *dev) +static int ftgmac100_phy_init(struct ftgmac100_data *priv, struct udevice *dev) { - struct ftgmac100_data *priv = dev->priv; - int phy_addr; u16 phy_id, status, adv, lpa, stat_ge; int media, speed, duplex; int i; /* Check if the PHY is up to snuff... */ - for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); + ftgmac100_phy_read(priv, phy_addr, MII_PHYSID1, &phy_id); /* * When it is unable to found PHY, @@ -197,15 +209,15 @@ static int ftgmac100_phy_init(struct eth_device *dev) return 0; } - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + ftgmac100_phy_read(priv, priv->phy_addr, MII_BMSR, &status); if (!(status & BMSR_LSTATUS)) { /* Try to re-negotiate if we don't have link already. */ - ftgmac100_phy_reset(dev); + ftgmac100_phy_reset(priv, dev); for (i = 0; i < 100000 / 100; i++) { - ftgmac100_phy_read(dev, priv->phy_addr, - MII_BMSR, &status); + ftgmac100_phy_read(priv, priv->phy_addr, + MII_BMSR, &status); if (status & BMSR_LSTATUS) break; udelay(100); @@ -235,8 +247,8 @@ static int ftgmac100_phy_init(struct eth_device *dev) } #endif - ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); - ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); + ftgmac100_phy_read(priv, priv->phy_addr, MII_ADVERTISE, &adv); + ftgmac100_phy_read(priv, priv->phy_addr, MII_LPA, &lpa); media = mii_nway_result(lpa & adv); speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); @@ -248,21 +260,19 @@ static int ftgmac100_phy_init(struct eth_device *dev) return 1; } -static int ftgmac100_update_link_speed(struct eth_device *dev) +static int ftgmac100_update_link_speed(struct ftgmac100_data *priv) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - struct ftgmac100_data *priv = dev->priv; - + struct ftgmac100 *ftgmac100 = priv->iobase; unsigned short stat_fe; unsigned short stat_ge; unsigned int maccr; #ifdef CONFIG_FTGMAC100_EGIGA /* 1000 Base-T Status Register */ - ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); + ftgmac100_phy_read(priv, priv->phy_addr, MII_STAT1000, &stat_ge); #endif - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); + ftgmac100_phy_read(priv, priv->phy_addr, MII_BMSR, &stat_fe); if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ return 0; @@ -315,9 +325,9 @@ static int ftgmac100_update_link_speed(struct eth_device *dev) /* * Reset MAC */ -static void ftgmac100_reset(struct eth_device *dev) +static void ftgmac100_reset(struct ftgmac100_data *priv) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100 *ftgmac100 = priv->iobase; debug("%s()\n", __func__); @@ -330,10 +340,10 @@ static void ftgmac100_reset(struct eth_device *dev) /* * Set MAC address */ -static void ftgmac100_set_mac(struct eth_device *dev, - const unsigned char *mac) +static int ftgmac100_set_mac(struct ftgmac100_data *priv, + const unsigned char *mac) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100 *ftgmac100 = priv->iobase; unsigned int maddr = mac[0] << 8 | mac[1]; unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; @@ -341,31 +351,28 @@ static void ftgmac100_set_mac(struct eth_device *dev, writel(maddr, &ftgmac100->mac_madr); writel(laddr, &ftgmac100->mac_ladr); -} -static void ftgmac100_set_mac_from_env(struct eth_device *dev) -{ - eth_env_get_enetaddr("ethaddr", dev->enetaddr); - - ftgmac100_set_mac(dev, dev->enetaddr); + return 0; } /* * disable transmitter, receiver */ -static void ftgmac100_halt(struct eth_device *dev) +static void ftgmac100_stop(struct udevice *dev) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100 *ftgmac100 = priv->iobase; debug("%s()\n", __func__); writel(0, &ftgmac100->maccr); } -static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +static int ftgmac100_start(struct udevice *dev) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - struct ftgmac100_data *priv = dev->priv; + struct eth_pdata *plat = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *txdes; struct ftgmac100_rxdes *rxdes; unsigned int maccr; @@ -374,6 +381,8 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd) debug("%s()\n", __func__); + ftgmac100_reset(priv); + if (!priv->txdes) { txdes = dma_alloc_coherent( sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma); @@ -395,7 +404,7 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd) rxdes = priv->rxdes; /* set the ethernet address */ - ftgmac100_set_mac_from_env(dev); + ftgmac100_set_mac(priv, plat->enetaddr); /* disable all interrupts */ writel(0, &ftgmac100->ier); @@ -453,20 +462,34 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd) writel(maccr, &ftgmac100->maccr); - if (!ftgmac100_phy_init(dev)) { - if (!ftgmac100_update_link_speed(dev)) + if (!ftgmac100_phy_init(priv, dev)) { + if (!ftgmac100_update_link_speed(priv)) return -1; } return 0; } +static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; + + /* Release buffer to DMA */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + + /* Move to next descriptor */ + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + /* * Get a data block via Ethernet */ -static int ftgmac100_recv(struct eth_device *dev) +static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) { - struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100_rxdes *curr_des; unsigned short rxlen; @@ -505,10 +528,10 @@ static int ftgmac100_recv(struct eth_device *dev) /* * Send a data block via Ethernet */ -static int ftgmac100_send(struct eth_device *dev, void *packet, int length) +static int ftgmac100_send(struct udevice *dev, void *packet, int length) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { @@ -540,43 +563,59 @@ static int ftgmac100_send(struct eth_device *dev, void *packet, int length) return 0; } -int ftgmac100_initialize(bd_t *bd) +static int ftgmac100_write_hwaddr(struct udevice *dev) { - struct eth_device *dev; - struct ftgmac100_data *priv; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); - dev = malloc(sizeof *dev); - if (!dev) { - printf("%s(): failed to allocate dev\n", __func__); - goto out; - } - - /* Transmit and receive descriptors should align to 16 bytes */ - priv = memalign(16, sizeof(struct ftgmac100_data)); - if (!priv) { - printf("%s(): failed to allocate priv\n", __func__); - goto free_dev; - } - - memset(dev, 0, sizeof(*dev)); - memset(priv, 0, sizeof(*priv)); + return ftgmac100_set_mac(priv, pdata->enetaddr); +} - strcpy(dev->name, "FTGMAC100"); - dev->iobase = CONFIG_FTGMAC100_BASE; - dev->init = ftgmac100_init; - dev->halt = ftgmac100_halt; - dev->send = ftgmac100_send; - dev->recv = ftgmac100_recv; - dev->priv = priv; +static int ftgmac100_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); - eth_register(dev); + pdata->iobase = devfdt_get_addr(dev); + return 0; +} - ftgmac100_reset(dev); +static int ftgmac100_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); - return 1; + priv->iobase = (struct ftgmac100 *)pdata->iobase; + return 0; +} -free_dev: - free(dev); -out: +static int ftgmac100_remove(struct udevice *dev) +{ return 0; } + +static const struct eth_ops ftgmac100_ops = { + .start = ftgmac100_start, + .send = ftgmac100_send, + .recv = ftgmac100_recv, + .stop = ftgmac100_stop, + .free_pkt = ftgmac100_free_pkt, + .write_hwaddr = ftgmac100_write_hwaddr, +}; + +static const struct udevice_id ftgmac100_ids[] = { + { .compatible = "faraday,ftgmac100" }, + { } +}; + +U_BOOT_DRIVER(ftgmac100) = { + .name = "ftgmac100", + .id = UCLASS_ETH, + .of_match = ftgmac100_ids, + .ofdata_to_platdata = ftgmac100_ofdata_to_platdata, + .probe = ftgmac100_probe, + .remove = ftgmac100_remove, + .ops = &ftgmac100_ops, + .priv_auto_alloc_size = sizeof(struct ftgmac100_data), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5441da47d13e..3efdc5dc2fae 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -186,6 +186,32 @@ config FTMAC100 help This MAC is present in Andestech SoCs. +config FTGMAC100 + bool "Ftgmac100 Ethernet Support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Faraday's FTGMAC100 Gigabit SoC + Ethernet controller that can be found on Aspeed SoCs (which + include NCSI). + + It is fully compliant with IEEE 802.3 specification for + 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 + Mbps Ethernet and includes Reduced Media Independent + Interface (RMII) and Reduced Gigabit Media Independent + Interface (RGMII) interfaces. It adopts an AHB bus interface + and integrates a link list DMA engine with direct M-Bus + accesses for transmitting and receiving packets. It has + independent TX/RX fifos, supports half and full duplex (1000 + Mbps mode only supports full duplex), flow control for full + duplex and backpressure for half duplex. + + The FTGMAC100 also implements IP, TCP, UDP checksum offloads + and supports IEEE 802.1Q VLAN tag insertion and removal. It + offers high-priority transmit queue for QoS and CoS + applications. + + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on KIRKWOOD || ORION5X From patchwork Tue Oct 16 09:22:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984622 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z9290WVjz9s9G for ; Tue, 16 Oct 2018 20:27:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C3074C21DA2; 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Tue, 16 Oct 2018 11:23:32 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:43 +0200 Message-Id: <20181016092252.11664-5-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12545621190810503961 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 04/13] net: ftgmac100: use setbits_le32() in the reset method X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/net/ftgmac100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 67a7c73503c5..78cd9df62986 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -331,7 +331,7 @@ static void ftgmac100_reset(struct ftgmac100_data *priv) debug("%s()\n", __func__); - writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST); while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) ; From patchwork Tue Oct 16 09:22:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984626 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z94M02N0z9s8r for ; Tue, 16 Oct 2018 20:29:22 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B0457C21DFA; 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Tue, 16 Oct 2018 11:23:39 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:44 +0200 Message-Id: <20181016092252.11664-6-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12547591512669784857 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 05/13] net: ftgmac100: add MDIO bus and phylib support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement the MDIO bus read/write functions using the readl_poll_timeout() routine, initialize the bus and scan for the PHY. RGMII and RMII mode are supported. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- Changes since v3 : - improved ftgmac100_mdio_init() and ftgmac100_phy_init() prototypes drivers/net/ftgmac100.c | 380 +++++++++++++++++----------------------- 1 file changed, 160 insertions(+), 220 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 78cd9df62986..b6e6f6e5ec02 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "ftgmac100.h" @@ -29,6 +30,16 @@ /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ #define PKTBUFSTX 4 /* must be power of 2 */ +/* Timeout for a mdio read/write operation */ +#define FTGMAC100_MDIO_TIMEOUT_USEC 10000 + +/* + * MDC clock cycle threshold + * + * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34 + */ +#define MDC_CYCTHR 0x34 + /** * struct ftgmac100_data - private data for the FTGMAC100 driver * @@ -38,6 +49,10 @@ * @tx_index: Transmit descriptor index in @txdes * @rx_index: Receive descriptor index in @rxdes * @phy_addr: The PHY interface address to use + * @phydev: The PHY device backing the MAC + * @bus: The mdio bus + * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...) + * @max_speed: Maximum speed of Ethernet connection supported by MAC */ struct ftgmac100_data { struct ftgmac100 *iobase; @@ -48,234 +63,110 @@ struct ftgmac100_data { struct ftgmac100_rxdes *rxdes; int tx_index; int rx_index; - int phy_addr; + + u32 phy_addr; + struct phy_device *phydev; + struct mii_dev *bus; + u32 phy_mode; + u32 max_speed; }; /* * struct mii_bus functions */ -static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr, - int regnum) +static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr) { + struct ftgmac100_data *priv = bus->priv; struct ftgmac100 *ftgmac100 = priv->iobase; int phycr; - int i; - - phycr = readl(&ftgmac100->phycr); - - /* preserve MDC cycle threshold */ - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; - - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) - | FTGMAC100_PHYCR_REGAD(regnum) - | FTGMAC100_PHYCR_MIIRD; + int data; + int ret; + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | + FTGMAC100_PHYCR_PHYAD(phy_addr) | + FTGMAC100_PHYCR_REGAD(reg_addr) | + FTGMAC100_PHYCR_MIIRD; writel(phycr, &ftgmac100->phycr); - for (i = 0; i < 10; i++) { - phycr = readl(&ftgmac100->phycr); - - if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { - int data; - - data = readl(&ftgmac100->phydata); - return FTGMAC100_PHYDATA_MIIRDATA(data); - } - - mdelay(10); + ret = readl_poll_timeout(&ftgmac100->phycr, phycr, + !(phycr & FTGMAC100_PHYCR_MIIRD), + FTGMAC100_MDIO_TIMEOUT_USEC); + if (ret) { + pr_err("%s: mdio read failed (phy:%d reg:%x)\n", + priv->phydev->dev->name, phy_addr, reg_addr); + return ret; } - debug("mdio read timed out\n"); - return -1; + data = readl(&ftgmac100->phydata); + + return FTGMAC100_PHYDATA_MIIRDATA(data); } -static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr, - int regnum, u16 value) +static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr, u16 value) { + struct ftgmac100_data *priv = bus->priv; struct ftgmac100 *ftgmac100 = priv->iobase; int phycr; int data; - int i; - - phycr = readl(&ftgmac100->phycr); - - /* preserve MDC cycle threshold */ - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; - - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) - | FTGMAC100_PHYCR_REGAD(regnum) - | FTGMAC100_PHYCR_MIIWR; + int ret; + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | + FTGMAC100_PHYCR_PHYAD(phy_addr) | + FTGMAC100_PHYCR_REGAD(reg_addr) | + FTGMAC100_PHYCR_MIIWR; data = FTGMAC100_PHYDATA_MIIWDATA(value); writel(data, &ftgmac100->phydata); writel(phycr, &ftgmac100->phycr); - for (i = 0; i < 10; i++) { - phycr = readl(&ftgmac100->phycr); - - if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { - debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ - "phy_addr: %x\n", phy_addr); - return 0; - } - - mdelay(1); + ret = readl_poll_timeout(&ftgmac100->phycr, phycr, + !(phycr & FTGMAC100_PHYCR_MIIWR), + FTGMAC100_MDIO_TIMEOUT_USEC); + if (ret) { + pr_err("%s: mdio write failed (phy:%d reg:%x)\n", + priv->phydev->dev->name, phy_addr, reg_addr); } - debug("mdio write timed out\n"); - return -1; + return ret; } -int ftgmac100_phy_read(struct ftgmac100_data *priv, int addr, int reg, - u16 *value) +static int ftgmac100_mdio_init(struct udevice *dev) { - *value = ftgmac100_mdiobus_read(priv, addr, reg); - - if (*value == -1) - return -1; - - return 0; -} - -int ftgmac100_phy_write(struct ftgmac100_data *priv, int addr, int reg, - u16 value) -{ - if (ftgmac100_mdiobus_write(priv, addr, reg, value) == -1) - return -1; - - return 0; -} - -static int ftgmac100_phy_reset(struct ftgmac100_data *priv, struct udevice *dev) -{ - int i; - u16 status, adv; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - - ftgmac100_phy_write(priv, priv->phy_addr, MII_ADVERTISE, adv); - - printf("%s: Starting autonegotiation...\n", dev->name); - - ftgmac100_phy_write(priv, priv->phy_addr, - MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); - - for (i = 0; i < 100000 / 100; i++) { - ftgmac100_phy_read(priv, priv->phy_addr, MII_BMSR, &status); - - if (status & BMSR_ANEGCOMPLETE) - break; - mdelay(1); - } - - if (status & BMSR_ANEGCOMPLETE) { - printf("%s: Autonegotiation complete\n", dev->name); - } else { - printf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->name, status); - return 0; - } - - return 1; -} - -static int ftgmac100_phy_init(struct ftgmac100_data *priv, struct udevice *dev) -{ - int phy_addr; - u16 phy_id, status, adv, lpa, stat_ge; - int media, speed, duplex; - int i; - - /* Check if the PHY is up to snuff... */ - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - - ftgmac100_phy_read(priv, phy_addr, MII_PHYSID1, &phy_id); - - /* - * When it is unable to found PHY, - * the interface usually return 0xffff or 0x0000 - */ - if (phy_id != 0xffff && phy_id != 0x0) { - printf("%s: found PHY at 0x%02x\n", - dev->name, phy_addr); - priv->phy_addr = phy_addr; - break; - } - } - - if (phy_id == 0xffff || phy_id == 0x0) { - printf("%s: no PHY present\n", dev->name); - return 0; - } - - ftgmac100_phy_read(priv, priv->phy_addr, MII_BMSR, &status); - - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - ftgmac100_phy_reset(priv, dev); - - for (i = 0; i < 100000 / 100; i++) { - ftgmac100_phy_read(priv, priv->phy_addr, - MII_BMSR, &status); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - - if (!(status & BMSR_LSTATUS)) { - printf("%s: link down\n", dev->name); - return 0; - } - -#ifdef CONFIG_FTGMAC100_EGIGA - /* 1000 Base-T Status Register */ - ftgmac100_phy_read(dev, priv->phy_addr, - MII_STAT1000, &stat_ge); + struct ftgmac100_data *priv = dev_get_priv(dev); + struct mii_dev *bus; + int ret; - speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) - ? 1 : 0); + bus = mdio_alloc(); + if (!bus) + return -ENOMEM; - duplex = ((stat_ge & LPA_1000FULL) - ? 1 : 0); + bus->read = ftgmac100_mdio_read; + bus->write = ftgmac100_mdio_write; + bus->priv = priv; - if (speed) { /* Speed is 1000 */ - printf("%s: link up, 1000bps %s-duplex\n", - dev->name, duplex ? "full" : "half"); - return 0; + ret = mdio_register_seq(bus, dev->seq); + if (ret) { + free(bus); + return ret; } -#endif - - ftgmac100_phy_read(priv, priv->phy_addr, MII_ADVERTISE, &adv); - ftgmac100_phy_read(priv, priv->phy_addr, MII_LPA, &lpa); - - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - printf("%s: link up, %sMbps %s-duplex\n", - dev->name, speed ? "100" : "10", duplex ? "full" : "half"); + priv->bus = bus; - return 1; + return 0; } -static int ftgmac100_update_link_speed(struct ftgmac100_data *priv) +static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv) { struct ftgmac100 *ftgmac100 = priv->iobase; - unsigned short stat_fe; - unsigned short stat_ge; - unsigned int maccr; - -#ifdef CONFIG_FTGMAC100_EGIGA - /* 1000 Base-T Status Register */ - ftgmac100_phy_read(priv, priv->phy_addr, MII_STAT1000, &stat_ge); -#endif - - ftgmac100_phy_read(priv, priv->phy_addr, MII_BMSR, &stat_fe); + struct phy_device *phydev = priv->phydev; + u32 maccr; - if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ - return 0; + if (!phydev->link) { + dev_err(phydev->dev, "No link\n"); + return -EREMOTEIO; + } /* read MAC control register and clear related bits */ maccr = readl(&ftgmac100->maccr) & @@ -283,43 +174,42 @@ static int ftgmac100_update_link_speed(struct ftgmac100_data *priv) FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP); -#ifdef CONFIG_FTGMAC100_EGIGA - if (stat_ge & LPA_1000FULL) { - /* set gmac for 1000BaseTX and Full Duplex */ - maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; - } - - if (stat_ge & LPA_1000HALF) { - /* set gmac for 1000BaseTX and Half Duplex */ + if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000) maccr |= FTGMAC100_MACCR_GIGA_MODE; - } -#endif - - if (stat_fe & BMSR_100FULL) { - /* set MII for 100BaseTX and Full Duplex */ - maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; - } - - if (stat_fe & BMSR_10FULL) { - /* set MII for 10BaseT and Full Duplex */ - maccr |= FTGMAC100_MACCR_FULLDUP; - } - if (stat_fe & BMSR_100HALF) { - /* set MII for 100BaseTX and Half Duplex */ + if (phydev->speed == 100) maccr |= FTGMAC100_MACCR_FAST_MODE; - } - if (stat_fe & BMSR_10HALF) { - /* set MII for 10BaseT and Half Duplex */ - /* we have already clear these bits, do nothing */ - ; - } + if (phydev->duplex) + maccr |= FTGMAC100_MACCR_FULLDUP; /* update MII config into maccr */ writel(maccr, &ftgmac100->maccr); - return 1; + return 0; +} + +static int ftgmac100_phy_init(struct udevice *dev) +{ + struct ftgmac100_data *priv = dev_get_priv(dev); + struct phy_device *phydev; + int ret; + + phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); + if (!phydev) + return -ENODEV; + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + priv->phydev = phydev; + phy_config(phydev); + + return 0; } /* @@ -366,6 +256,8 @@ static void ftgmac100_stop(struct udevice *dev) debug("%s()\n", __func__); writel(0, &ftgmac100->maccr); + + phy_shutdown(priv->phydev); } static int ftgmac100_start(struct udevice *dev) @@ -373,10 +265,12 @@ static int ftgmac100_start(struct udevice *dev) struct eth_pdata *plat = dev_get_platdata(dev); struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; + struct phy_device *phydev = priv->phydev; struct ftgmac100_txdes *txdes; struct ftgmac100_rxdes *rxdes; unsigned int maccr; void *buf; + int ret; int i; debug("%s()\n", __func__); @@ -462,11 +356,21 @@ static int ftgmac100_start(struct udevice *dev) writel(maccr, &ftgmac100->maccr); - if (!ftgmac100_phy_init(priv, dev)) { - if (!ftgmac100_update_link_speed(priv)) - return -1; + ret = phy_startup(phydev); + if (ret) { + dev_err(phydev->dev, "Could not start PHY\n"); + return ret; } + ret = ftgmac100_phy_adjust_link(priv); + if (ret) { + dev_err(phydev->dev, "Could not adjust link\n"); + return ret; + } + + printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name, + phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr); + return 0; } @@ -574,8 +478,20 @@ static int ftgmac100_write_hwaddr(struct udevice *dev) static int ftgmac100_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; pdata->iobase = devfdt_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = dev_read_string(dev, "phy-mode"); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); + return -EINVAL; + } + + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); + return 0; } @@ -583,13 +499,37 @@ static int ftgmac100_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct ftgmac100_data *priv = dev_get_priv(dev); + int ret; priv->iobase = (struct ftgmac100 *)pdata->iobase; - return 0; + priv->phy_mode = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + priv->phy_addr = 0; + + ret = ftgmac100_mdio_init(dev); + if (ret) { + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); + goto out; + } + + ret = ftgmac100_phy_init(dev); + if (ret) { + dev_err(dev, "Failed to initialize PHY: %d\n", ret); + goto out; + } + +out: + return ret; } static int ftgmac100_remove(struct udevice *dev) { + struct ftgmac100_data *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + return 0; } From patchwork Tue Oct 16 09:22:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984627 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z95T4Cr6z9s9J for ; Tue, 16 Oct 2018 20:30:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 75E6BC21DD3; Tue, 16 Oct 2018 09:28:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 04E5FC21E52; Tue, 16 Oct 2018 09:24:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1A037C21E1A; Tue, 16 Oct 2018 09:24:00 +0000 (UTC) Received: from 2.mo2.mail-out.ovh.net (2.mo2.mail-out.ovh.net [188.165.53.149]) by lists.denx.de (Postfix) with ESMTPS id 9CE0CC21E08 for ; Tue, 16 Oct 2018 09:23:56 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.159.154]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 44C541676DB for ; Tue, 16 Oct 2018 11:23:54 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id E0B034200A8; Tue, 16 Oct 2018 11:23:46 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:45 +0200 Message-Id: <20181016092252.11664-7-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12549843312919218969 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 06/13] net: ftgmac100: convert the RX/TX descriptor arrays X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use simple arrays under the device priv structure to hold the RX and TX descriptors and handle memory coherency by invalidating or flushing the d-cache when required. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/net/ftgmac100.c | 141 ++++++++++++++++++---------------------- 1 file changed, 64 insertions(+), 77 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index b6e6f6e5ec02..bf8600814690 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -13,19 +13,17 @@ #include #include -#include #include #include -#include #include #include "ftgmac100.h" -#define ETH_ZLEN 60 -#define CFG_XBUF_SIZE 1536 +/* Min frame ethernet frame size without FCS */ +#define ETH_ZLEN 60 -/* RBSR - hw default init value is also 0x640 */ -#define RBSR_DEFAULT_VALUE 0x640 +/* Receive Buffer Size Register - HW default is 0x640 */ +#define FTGMAC100_RBSR_DEFAULT 0x640 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ #define PKTBUFSTX 4 /* must be power of 2 */ @@ -57,10 +55,8 @@ struct ftgmac100_data { struct ftgmac100 *iobase; - ulong txdes_dma; - struct ftgmac100_txdes *txdes; - ulong rxdes_dma; - struct ftgmac100_rxdes *rxdes; + struct ftgmac100_txdes txdes[PKTBUFSTX]; + struct ftgmac100_rxdes rxdes[PKTBUFSRX]; int tx_index; int rx_index; @@ -266,10 +262,8 @@ static int ftgmac100_start(struct udevice *dev) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct phy_device *phydev = priv->phydev; - struct ftgmac100_txdes *txdes; - struct ftgmac100_rxdes *rxdes; unsigned int maccr; - void *buf; + ulong start, end; int ret; int i; @@ -277,26 +271,6 @@ static int ftgmac100_start(struct udevice *dev) ftgmac100_reset(priv); - if (!priv->txdes) { - txdes = dma_alloc_coherent( - sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma); - if (!txdes) - panic("ftgmac100: out of memory\n"); - memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX); - priv->txdes = txdes; - } - txdes = priv->txdes; - - if (!priv->rxdes) { - rxdes = dma_alloc_coherent( - sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma); - if (!rxdes) - panic("ftgmac100: out of memory\n"); - memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX); - priv->rxdes = rxdes; - } - rxdes = priv->rxdes; - /* set the ethernet address */ ftgmac100_set_mac(priv, plat->enetaddr); @@ -307,42 +281,37 @@ static int ftgmac100_start(struct udevice *dev) priv->tx_index = 0; priv->rx_index = 0; - txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; - rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; - for (i = 0; i < PKTBUFSTX; i++) { - /* TXBUF_BADR */ - if (!txdes[i].txdes2) { - buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); - if (!buf) - panic("ftgmac100: out of memory\n"); - txdes[i].txdes3 = virt_to_phys(buf); - txdes[i].txdes2 = (uint)buf; - } - txdes[i].txdes1 = 0; + priv->txdes[i].txdes3 = 0; + priv->txdes[i].txdes0 = 0; } + priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + + start = (ulong)&priv->txdes[0]; + end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); for (i = 0; i < PKTBUFSRX; i++) { - /* RXBUF_BADR */ - if (!rxdes[i].rxdes2) { - buf = net_rx_packets[i]; - rxdes[i].rxdes3 = virt_to_phys(buf); - rxdes[i].rxdes2 = (uint)buf; - } - rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; + priv->rxdes[i].rxdes0 = 0; } + priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + + start = (ulong)&priv->rxdes[0]; + end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); /* transmit ring */ - writel(priv->txdes_dma, &ftgmac100->txr_badr); + writel((u32)priv->txdes, &ftgmac100->txr_badr); /* receive ring */ - writel(priv->rxdes_dma, &ftgmac100->rxr_badr); + writel((u32)priv->rxdes, &ftgmac100->rxr_badr); /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); /* config receive buffer size register */ - writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr); /* enable transmitter, receiver */ maccr = FTGMAC100_MACCR_TXMAC_EN | @@ -378,9 +347,13 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) { struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; + ulong des_start = (ulong)curr_des; + ulong des_end = des_start + + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); - /* Release buffer to DMA */ + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + flush_dcache_range(des_start, des_end); /* Move to next descriptor */ priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; @@ -394,20 +367,25 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) { struct ftgmac100_data *priv = dev_get_priv(dev); - struct ftgmac100_rxdes *curr_des; + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; unsigned short rxlen; + ulong des_start = (ulong)curr_des; + ulong des_end = des_start + + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + ulong data_start = curr_des->rxdes3; + ulong data_end; - curr_des = &priv->rxdes[priv->rx_index]; + invalidate_dcache_range(des_start, des_end); if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) - return -1; + return -EAGAIN; if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | FTGMAC100_RXDES0_CRC_ERR | FTGMAC100_RXDES0_FTL | FTGMAC100_RXDES0_RUNT | FTGMAC100_RXDES0_RX_ODD_NB)) { - return -1; + return -EAGAIN; } rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); @@ -415,18 +393,12 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) debug("%s(): RX buffer %d, %x received\n", __func__, priv->rx_index, rxlen); - /* invalidate d-cache */ - dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE); + /* Invalidate received data */ + data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); + *packetp = (uchar *)data_start; - /* pass the packet up to the protocol layers. */ - net_process_received_packet((void *)curr_des->rxdes2, rxlen); - - /* release buffer to DMA */ - curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; - - priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; - - return 0; + return rxlen; } /* @@ -437,31 +409,46 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + ulong des_start = (ulong)curr_des; + ulong des_end = des_start + + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + ulong data_start; + ulong data_end; + + invalidate_dcache_range(des_start, des_end); if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { - debug("%s(): no TX descriptor available\n", __func__); - return -1; + dev_err(dev, "no TX descriptor available\n"); + return -EPERM; } debug("%s(%x, %x)\n", __func__, (int)packet, length); length = (length < ETH_ZLEN) ? ETH_ZLEN : length; - memcpy((void *)curr_des->txdes2, (void *)packet, length); - dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE); + curr_des->txdes3 = (unsigned int)packet; + + /* Flush data to be sent */ + data_start = curr_des->txdes3; + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + flush_dcache_range(data_start, data_end); - /* only one descriptor on TXBUF */ + /* Only one segment on TXBUF */ curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | FTGMAC100_TXDES0_LTS | FTGMAC100_TXDES0_TXBUF_SIZE(length) | FTGMAC100_TXDES0_TXDMA_OWN ; - /* start transmit */ + /* Flush modified buffer descriptor */ + flush_dcache_range(des_start, des_end); + + /* Start transmit */ writel(1, &ftgmac100->txpd); debug("%s(): packet sent\n", __func__); + /* Move to next descriptor */ priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; return 0; From patchwork Tue Oct 16 09:22:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984635 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z99x0X1Yz9s8r for ; Tue, 16 Oct 2018 20:34:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CA9ABC21C50; Tue, 16 Oct 2018 09:28:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 09F44C21E15; Tue, 16 Oct 2018 09:25:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 237BEC21E30; Tue, 16 Oct 2018 09:25:06 +0000 (UTC) Received: from 9.mo6.mail-out.ovh.net (9.mo6.mail-out.ovh.net [87.98.171.146]) by lists.denx.de (Postfix) with ESMTPS id 0750FC21E3E for ; Tue, 16 Oct 2018 09:24:03 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.146.76]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 6558E189198 for ; Tue, 16 Oct 2018 11:24:01 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 3E11A4200B9; Tue, 16 Oct 2018 11:23:54 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:46 +0200 Message-Id: <20181016092252.11664-8-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12551813640467155737 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 07/13] net: ftgmac100: handle timeouts when transmitting X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley --- Changes since v3 : - introduced a ftgmac100_wait_for_txdone() function similar to the wait_for_bit_*() macros. drivers/net/ftgmac100.c | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index bf8600814690..9adfe109ebc2 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,9 @@ /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ #define PKTBUFSTX 4 /* must be power of 2 */ +/* Timeout for transmit */ +#define FTGMAC100_TX_TIMEOUT_MS 1000 + /* Timeout for a mdio read/write operation */ #define FTGMAC100_MDIO_TIMEOUT_USEC 10000 @@ -401,6 +405,41 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) return rxlen; } +/* + * The wait_for_bit_*() macros require a register value. This define a + * similar routine which loops on the in-memory transmit descriptor to + * wait for the MAC to clear the DMA_OWN bit. + */ +static int ftgmac100_wait_for_txdone(struct ftgmac100_txdes *txdes, + const unsigned int timeout_ms, + const bool breakable) +{ + ulong des_start = (ulong)txdes; + ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); + ulong start = get_timer(0); + + while (1) { + invalidate_dcache_range(des_start, des_end); + + if (!(txdes->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN)) + return 0; + + if (get_timer(start) > timeout_ms) + break; + + if (breakable && ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + WATCHDOG_RESET(); + } + + dev_err(dev, "transmit timeout\n"); + return -ETIMEDOUT; +} + /* * Send a data block via Ethernet */ @@ -414,6 +453,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); ulong data_start; ulong data_end; + int rc; invalidate_dcache_range(des_start, des_end); @@ -446,6 +486,10 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) /* Start transmit */ writel(1, &ftgmac100->txpd); + rc = ftgmac100_wait_for_txdone(curr_des, FTGMAC100_TX_TIMEOUT_MS, true); + if (rc) + return rc; + debug("%s(): packet sent\n", __func__); /* Move to next descriptor */ From patchwork Tue Oct 16 09:22:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984629 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z9673Rk0z9s8r for ; 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Tue, 16 Oct 2018 11:24:01 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:47 +0200 Message-Id: <20181016092252.11664-9-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12553783962152438553 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 08/13] net: ftgmac100: add clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/net/ftgmac100.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9adfe109ebc2..e1104a544748 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -11,6 +11,7 @@ * Copyright (C) 2018, IBM Corporation. */ +#include #include #include #include @@ -55,6 +56,7 @@ * @bus: The mdio bus * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...) * @max_speed: Maximum speed of Ethernet connection supported by MAC + * @clks: The bulk of clocks assigned to the device in the DT */ struct ftgmac100_data { struct ftgmac100 *iobase; @@ -69,6 +71,8 @@ struct ftgmac100_data { struct mii_dev *bus; u32 phy_mode; u32 max_speed; + + struct clk_bulk clks; }; /* @@ -509,6 +513,7 @@ static int ftgmac100_write_hwaddr(struct udevice *dev) static int ftgmac100_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); const char *phy_mode; pdata->iobase = devfdt_get_addr(dev); @@ -523,7 +528,7 @@ static int ftgmac100_ofdata_to_platdata(struct udevice *dev) pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); - return 0; + return clk_get_bulk(dev, &priv->clks); } static int ftgmac100_probe(struct udevice *dev) @@ -537,6 +542,10 @@ static int ftgmac100_probe(struct udevice *dev) priv->max_speed = pdata->max_speed; priv->phy_addr = 0; + ret = clk_enable_bulk(&priv->clks); + if (ret) + goto out; + ret = ftgmac100_mdio_init(dev); if (ret) { dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); @@ -550,6 +559,9 @@ static int ftgmac100_probe(struct udevice *dev) } out: + if (ret) + clk_release_bulk(&priv->clks); + return ret; } @@ -560,6 +572,7 @@ static int ftgmac100_remove(struct udevice *dev) free(priv->phydev); mdio_unregister(priv->bus); mdio_free(priv->bus); + clk_release_bulk(&priv->clks); return 0; } From patchwork Tue Oct 16 09:22:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984634 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z99Z1cRlz9s8r for ; Tue, 16 Oct 2018 20:33:54 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E46CCC21D8E; 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Tue, 16 Oct 2018 11:24:08 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:48 +0200 Message-Id: <20181016092252.11664-10-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12556035764114524953 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 09/13] aspeed: ast2500: fix missing break in D2PLL clock enablement X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Simon Glass Acked-by: Joe Hershberger --- drivers/clk/aspeed/clk_ast2500.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 526470051c5d..2182320f607f 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -411,6 +411,7 @@ static int ast2500_clk_enable(struct clk *clk) break; case PLL_D2PLL: ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); + break; default: return -ENOENT; } From patchwork Tue Oct 16 09:22:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984633 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z99R3Nljz9s8r for ; Tue, 16 Oct 2018 20:33:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2DD2CC21D8A; Tue, 16 Oct 2018 09:29:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BEEE3C21E42; Tue, 16 Oct 2018 09:25:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2129EC21DC1; Tue, 16 Oct 2018 09:25:56 +0000 (UTC) Received: from 2.mo3.mail-out.ovh.net (2.mo3.mail-out.ovh.net [46.105.75.36]) by lists.denx.de (Postfix) with ESMTPS id 4949EC21C50 for ; Tue, 16 Oct 2018 09:24:25 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.143.232]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id B7DB81DD5DC for ; Tue, 16 Oct 2018 11:24:23 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 4749A4200A5; Tue, 16 Oct 2018 11:24:16 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:49 +0200 Message-Id: <20181016092252.11664-11-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12558006087242582809 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 10/13] net: ftgmac100: Add support for the Aspeed SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits). Signed-off-by: Cédric Le Goater Reviewed-by: Simon Glass Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/net/ftgmac100.c | 31 +++++++++++++++++++++++++++---- configs/evb-ast2500_defconfig | 8 ++++++++ 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index e1104a544748..78abf8b984c0 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -43,6 +43,14 @@ */ #define MDC_CYCTHR 0x34 +/* + * ftgmac100 model variants + */ +enum ftgmac100_model { + FTGMAC100_MODEL_FARADAY, + FTGMAC100_MODEL_ASPEED, +}; + /** * struct ftgmac100_data - private data for the FTGMAC100 driver * @@ -57,6 +65,8 @@ * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...) * @max_speed: Maximum speed of Ethernet connection supported by MAC * @clks: The bulk of clocks assigned to the device in the DT + * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer + * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer */ struct ftgmac100_data { struct ftgmac100 *iobase; @@ -73,6 +83,10 @@ struct ftgmac100_data { u32 max_speed; struct clk_bulk clks; + + /* End of RX/TX ring buffer bits. Depend on model */ + u32 rxdes0_edorr_mask; + u32 txdes0_edotr_mask; }; /* @@ -293,7 +307,7 @@ static int ftgmac100_start(struct udevice *dev) priv->txdes[i].txdes3 = 0; priv->txdes[i].txdes0 = 0; } - priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask; start = (ulong)&priv->txdes[0]; end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); @@ -303,7 +317,7 @@ static int ftgmac100_start(struct udevice *dev) priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; priv->rxdes[i].rxdes0 = 0; } - priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; start = (ulong)&priv->rxdes[0]; end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); @@ -478,7 +492,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) flush_dcache_range(data_start, data_end); /* Only one segment on TXBUF */ - curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + curr_des->txdes0 &= priv->txdes0_edotr_mask; curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | FTGMAC100_TXDES0_LTS | FTGMAC100_TXDES0_TXBUF_SIZE(length) | @@ -528,6 +542,14 @@ static int ftgmac100_ofdata_to_platdata(struct udevice *dev) pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); + if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { + priv->rxdes0_edorr_mask = BIT(30); + priv->txdes0_edotr_mask = BIT(30); + } else { + priv->rxdes0_edorr_mask = BIT(15); + priv->txdes0_edotr_mask = BIT(15); + } + return clk_get_bulk(dev, &priv->clks); } @@ -587,7 +609,8 @@ static const struct eth_ops ftgmac100_ops = { }; static const struct udevice_id ftgmac100_ids[] = { - { .compatible = "faraday,ftgmac100" }, + { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, + { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, { } }; diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 88230f4a12db..32581f5ada54 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -25,3 +25,11 @@ CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y +CONFIG_NETDEVICES=y +CONFIG_PHY=y +CONFIG_DM_ETH=y +CONFIG_FTGMAC100=y +CONFIG_PHY_REALTEK=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y From patchwork Tue Oct 16 09:22:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984631 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z98j50dTz9s9G for ; Tue, 16 Oct 2018 20:33:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 46F99C21D8A; Tue, 16 Oct 2018 09:30:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DF1BDC21E62; Tue, 16 Oct 2018 09:26:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C6D3FC21DD7; Tue, 16 Oct 2018 09:26:05 +0000 (UTC) Received: from 6.mo173.mail-out.ovh.net (6.mo173.mail-out.ovh.net [46.105.43.93]) by lists.denx.de (Postfix) with ESMTPS id 59A3EC21E0B for ; Tue, 16 Oct 2018 09:24:31 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.160.232]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id F3623DA170 for ; Tue, 16 Oct 2018 11:24:30 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id A14644200C5; Tue, 16 Oct 2018 11:24:23 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:50 +0200 Message-Id: <20181016092252.11664-12-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12559976414567303961 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 11/13] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Simon Glass Acked-by: Joe Hershberger --- arch/arm/dts/ast2500.dtsi | 1949 ++++++++++++++++++++++--------------- 1 file changed, 1153 insertions(+), 796 deletions(-) diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 7e0ad3a41ac5..98359bf92425 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -11,6 +11,29 @@ #size-cells = <1>; interrupt-parent = <&vic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,12 +45,80 @@ }; }; + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0xc4 + 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-fmc"; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi1: flash-controller@1e630000 { + reg = < 0x1e630000 0xc4 + 0x30000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi2: flash-controller@1e631000 { + reg = < 0x1e631000 0xc4 + 0x38000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; @@ -37,18 +128,38 @@ }; mac0: ethernet@1e660000 { - compatible = "faraday,ftgmac100"; + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; interrupts = <2>; - no-hw-checksum; status = "disabled"; }; mac1: ethernet@1e680000 { - compatible = "faraday,ftgmac100"; + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; - no-hw-checksum; + status = "disabled"; + }; + + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = <5>; + status = "disabled"; + }; + + ehci1: usb@1e6a3000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a3000 0x100>; + interrupts = <13>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2500-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = <14>; + #ports = <2>; status = "disabled"; }; @@ -58,996 +169,1242 @@ #size-cells = <1>; ranges; - clk_clkin: clk_clkin@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock"; - reg = <0x1e6e2070 0x04>; - }; - syscon: syscon@1e6e2000 { compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,g5-pinctrl"; aspeed,external-nodes = <&gfx &lhc>; - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; + }; + }; - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; + rng: hwrng@1e6e2078 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2078 0x4>; + period = <1>; + quality = <100>; + }; - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + }; - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + #io-channel-cells = <1>; + status = "disabled"; + }; - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + interrupt-controller; + }; - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + }; - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; + wdt1: watchdog@1e785000 { + compatible = "aspeed,wdt"; + reg = <0x1e785000 0x1c>; + interrupts = <27>; + }; - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; + wdt2: watchdog@1e785020 { + compatible = "aspeed,wdt"; + reg = <0x1e785020 0x1c>; + interrupts = <27>; + status = "disabled"; + }; - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; + wdt3: watchdog@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785040 0x1c>; + status = "disabled"; + }; - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2500-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + status = "disabled"; + }; - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2500-lpc-bmc"; + reg = <0x0 0x80>; + }; - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; }; - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2500-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = <8>; + status = "disabled"; }; - pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; }; - pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; }; - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; + ibt: ibt@c0 { + compatible = "aspeed,ast2500-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; }; + }; + }; - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +}; - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; - pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; - pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; - pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; - pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; - pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; - pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; - pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + }; - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + }; - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; - pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + }; - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + }; - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + }; - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + }; - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + }; - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + }; - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + }; - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; - pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; - pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; - pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; - pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; - pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; - pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; - pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; - pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; - pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; - pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + }; - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; - pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; - pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; - pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; - pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + }; - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + }; - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + }; - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + }; - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + }; - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; - pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; - pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + }; - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + }; - }; - }; + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + }; - clk_hpll: clk_hpll@1e6e2024 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock"; - reg = <0x1e6e2024 0x4>; - clocks = <&clk_clkin>; - }; + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; - clk_ahb: clk_ahb@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_hpll>; - }; + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; - clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; + pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + }; - clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; - }; + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + }; - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - }; + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; - sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - interrupt-controller; - }; + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; - timer: timer@1e782000 { - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; - clocks = <&clk_apb>; - }; + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; - wdt1: wdt@1e785000 { - compatible = "aspeed,wdt"; - reg = <0x1e785000 0x1c>; - interrupts = <27>; - }; + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; - wdt2: wdt@1e785020 { - compatible = "aspeed,wdt"; - reg = <0x1e785020 0x1c>; - interrupts = <27>; - status = "disabled"; - }; + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; - wdt3: wdt@1e785040 { - compatible = "aspeed,wdt"; - reg = <0x1e785074 0x1c>; - status = "disabled"; - }; + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; - reg = <0x0 0x80>; - }; + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80 0x1e0>; + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; - reg-io-width = <4>; + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; - lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - }; - }; + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - }; + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_usb2ah_default: usb2ah_default { + function = "USB2AH"; + groups = "USB2AH"; + }; + + pinctrl_usb11bhid_default: usb11bhid_default { + function = "USB11BHID"; + groups = "USB11BHID"; + }; + + pinctrl_usb2bh_default: usb2bh_default { + function = "USB2BH"; + groups = "USB2BH"; + }; + + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; }; }; From patchwork Tue Oct 16 09:22:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984630 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z9890XkKz9s8r for ; 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Tue, 16 Oct 2018 11:24:30 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:51 +0200 Message-Id: <20181016092252.11664-13-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12562228211201903385 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 12/13] aspeed: Activate ethernet devices on the ast2500 Eval Board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Simon Glass Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- arch/arm/dts/ast2500-evb.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index 723941ac0bee..ebf44fd707f9 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -11,6 +11,11 @@ chosen { stdout-path = &uart5; }; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + }; }; &uart5 { @@ -36,3 +41,21 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>; +}; + +&mac1 { + status = "okay"; + + phy-mode = "rgmii"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>; +}; From patchwork Tue Oct 16 09:22:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984632 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z9951cq2z9s8r for ; Tue, 16 Oct 2018 20:33:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DBB15C21E0D; Tue, 16 Oct 2018 09:31:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 54830C21D9A; Tue, 16 Oct 2018 09:26:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CB883C21E75; Tue, 16 Oct 2018 09:26:05 +0000 (UTC) Received: from 4.mo173.mail-out.ovh.net (4.mo173.mail-out.ovh.net [46.105.34.219]) by lists.denx.de (Postfix) with ESMTPS id E208EC21E12 for ; Tue, 16 Oct 2018 09:24:45 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.159.20]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 8F15CD3197 for ; Tue, 16 Oct 2018 11:24:45 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 4CBE74200AB; Tue, 16 Oct 2018 11:24:38 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:52 +0200 Message-Id: <20181016092252.11664-14-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12564198539229694745 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 13/13] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The algorithm in the ast2500_calc_clock_config() routine suffers from integer rounding and the requested rate does not get the appropriate set of Numerator, Denumerator, Post Divider parameters. This is the case for the D2-PLL clock used by the MAC controllers in RGMII mode. The requested rated is 250MHz but a 251MHz is assigned. The easiest way to fix this problem is to introduce an array of clock settings defining the N, M, P parameters for well known frequencies used by the Aspeed SoC. Signed-off-by: Cédric Le Goater Reviewed-by: Simon Glass Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/clk/aspeed/clk_ast2500.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 2182320f607f..dbee13a18297 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk) return rate; } +struct ast2500_clock_config { + ulong input_rate; + ulong rate; + struct ast2500_div_config cfg; +}; + +static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { + { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, +}; + +static bool ast2500_get_clock_config_default(ulong input_rate, + ulong requested_rate, + struct ast2500_div_config *cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { + const struct ast2500_clock_config *default_cfg = + &ast2500_clock_config_defaults[i]; + if (default_cfg->input_rate == input_rate && + default_cfg->rate == requested_rate) { + *cfg = default_cfg->cfg; + return true; + } + } + + return false; +} + /* * @input_rate - the rate of input clock in Hz * @requested_rate - desired output rate in Hz @@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, ulong delta = rate_khz; ulong new_rate_khz = 0; + /* + * Look for a well known frequency first. + */ + if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) + return requested_rate; + for (; it.denum <= max_vals.denum; ++it.denum) { for (it.post_div = 0; it.post_div <= max_vals.post_div; ++it.post_div) { @@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) /* * The values and the meaning of the next three * parameters are undocumented. Taken from Aspeed SDK. + * + * TODO(clg@kaod.org): the SIP and SIC values depend on the + * Numerator value */ const u32 d2_pll_ext_param = 0x2c; const u32 d2_pll_sip = 0x11;