From patchwork Wed Oct 10 15:14:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 981947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-487265-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=vnet.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="c1xnMOhQ"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Vd1p5djvz9s3l for ; Thu, 11 Oct 2018 02:14:54 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=n8VrJ Qm9O9z16dF6Xl53179GFI8+Wd322QuxknpqpLrbKmBPx5NtReceCYV6NVSiKRhHl Bko4XGP6y35sxwA0T8W7MaOPVBT5VFPzwnb09tOxp1lGFc4PypDtAMqkxftx6rhE zOF51TPpvtqgv5efksGSUMfwW6ZChvVxstWtWE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; s=default; bh=IeMccnVikZY Uw2RDyDoiM2KsdG4=; b=c1xnMOhQKmBkn0SLANHPbzSW+2A6U4I6c24TUHLPUT9 syl4fV/vi5Xp/dL6nwqblbsW7HMy8eJ4pY0xIKYt3+GJ5JLkhsDpn35P+NCXbbiw U5RepoptFrT0oOB5z0k9G2nAizSVBNS6BP5qcAad6WeKVWLMfej9wFrafJnFVtUg = Received: (qmail 113492 invoked by alias); 10 Oct 2018 15:14:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 113373 invoked by uid 89); 10 Oct 2018 15:14:42 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=drops, combo X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 10 Oct 2018 15:14:37 +0000 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w9AF0KQ3015419 for ; Wed, 10 Oct 2018 11:14:36 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0b-001b2d01.pphosted.com with ESMTP id 2n1jh5mknn-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 10 Oct 2018 11:14:35 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 10 Oct 2018 11:14:33 -0400 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w9AFEWFf43712594 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Oct 2018 15:14:32 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 223CB112067; Wed, 10 Oct 2018 11:13:54 -0400 (EDT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D6200112063; Wed, 10 Oct 2018 11:13:53 -0400 (EDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 10 Oct 2018 11:13:53 -0400 (EDT) Subject: [PATCH, rs6000] testcases for vec_insert From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: Segher Boessenkool , David Edelsohn , Bill Schmidt Cc: GCC Patches Date: Wed, 10 Oct 2018 10:14:31 -0500 Mime-Version: 1.0 x-cbid: 18101015-0072-0000-0000-000003B29879 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009854; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000268; SDB=6.01100666; UDB=6.00569490; IPR=6.00880715; MB=3.00023696; MTD=3.00000008; XFM=3.00000015; UTC=2018-10-10 15:14:34 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18101015-0073-0000-0000-000049B5420A Message-Id: <1539184471.16697.57.camel@brimstone.rchland.ibm.com> X-IsSubscribed: yes Hi, Add some testcases for verification of vec_insert() codegen. The char,float,int,short tests are broken out into -p8 and -p9 variants due to codegen variations between the platforms. Tested across assorted power linux platforms. OK for trunk? Thanks -Will [testsuite] 2018-10-10 Will Schmidt * gcc.target/powerpc/fold-vec-insert-char-p8.c: New. * gcc.target/powerpc/fold-vec-insert-char-p9.c: New. * gcc.target/powerpc/fold-vec-insert-double.c: New. * gcc.target/powerpc/fold-vec-insert-float-p8.c: New. * gcc.target/powerpc/fold-vec-insert-float-p9.c: New. * gcc.target/powerpc/fold-vec-insert-int-p8.c: New. * gcc.target/powerpc/fold-vec-insert-int-p9.c: New. * gcc.target/powerpc/fold-vec-insert-longlong.c: New. * gcc.target/powerpc/fold-vec-insert-short-p8.c: New. * gcc.target/powerpc/fold-vec-insert-short-p9.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c new file mode 100644 index 0000000..1c634c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c @@ -0,0 +1,60 @@ +/* Verify that overloaded built-ins for vec_insert () with char + inputs produce the right codegen. */ + +/* The below contains vec_insert () calls with both variable and constant + values. Only the constant value calls are early-gimple folded, but all + are tested for coverage. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-maltivec -O2" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power8" } */ + +#include + +vector bool char testub_var (unsigned char x, vector bool char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector signed char testss_var (signed char x, vector signed char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector unsigned char testsu_var (signed char x, vector unsigned char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector unsigned char testuu_var (unsigned char x, vector unsigned char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector bool char testub_cst (unsigned char x, vector bool char v) +{ + return vec_insert (x, v, 12); +} +vector signed char testss_cst (signed char x, vector signed char v) +{ + return vec_insert (x, v, 12); +} +vector unsigned char testsu_cst (signed char x, vector unsigned char v) +{ + return vec_insert (x, v, 12); +} +vector unsigned char testuu_cst (unsigned char x, vector unsigned char v) +{ + return vec_insert (x, v, 12); +} + +/* one store per _var test */ +/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 4 } } */ +/* one store-byte per test */ +/* { dg-final { scan-assembler-times {\mstb\M} 8 } } */ +/* one load per test */ +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 } } */ + +/* one lvebx per _cst test.*/ +/* { dg-final { scan-assembler-times {\mlvebx\M} 4 } } */ +/* one vperm per _cst test.*/ +/* { dg-final { scan-assembler-times {\mvperm\M} 4 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c new file mode 100644 index 0000000..4fb43e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c @@ -0,0 +1,57 @@ +/* Verify that overloaded built-ins for vec_insert () with char + inputs produce the right codegen. */ + +/* The below contains vec_insert () calls with both variable and constant + values. Only the constant value calls are early-gimple folded, but all + are tested for coverage. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-maltivec -O2" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power9" } */ + +#include + +vector bool char testub_var (unsigned char x, vector bool char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector signed char testss_var (signed char x, vector signed char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector unsigned char testsu_var (signed char x, vector unsigned char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector unsigned char testuu_var (unsigned char x, vector unsigned char v, signed int i) +{ + return vec_insert (x, v, i); +} +vector bool char testub_cst (unsigned char x, vector bool char v) +{ + return vec_insert (x, v, 12); +} +vector signed char testss_cst (signed char x, vector signed char v) +{ + return vec_insert (x, v, 12); +} +vector unsigned char testsu_cst (signed char x, vector unsigned char v) +{ + return vec_insert (x, v, 12); +} +vector unsigned char testuu_cst (unsigned char x, vector unsigned char v) +{ + return vec_insert (x, v, 12); +} + +/* load immediate, add, store, stb, load variable test. */ +/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstb\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mlvebx\M|\mlxv\M|\mlvx\M} 4 } } */ + +/* an insert and a move per constant test. */ +/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mvinsertb\M} 4 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c new file mode 100644 index 0000000..a042c31 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c @@ -0,0 +1,29 @@ +/* Verify that overloaded built-ins for vec_insert with + double inputs produce the right codegen. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector double +testd_var (double d, vector double vd, signed int si) +{ + return vec_insert (d, vd, si); +} + +vector double +testd_cst (double d, vector double vd) +{ + return vec_insert (d, vd, 1); +} +/* The number of xxpermdi instructions varies between + P7,P8,P9, ensure at least one hit. */ +/* { dg-final { scan-assembler {\mxxpermdi\M} } } */ + +/* { dg-final { scan-assembler-times {\mrldic\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstfdx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c new file mode 100644 index 0000000..8c1088e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c @@ -0,0 +1,31 @@ +/* Verify that overloaded built-ins for vec_insert with float + inputs produce the right codegen. Power8 variant. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power8" } */ + +#include + +vector float +testf_var (float f, vector float vf, signed int i) +{ + return vec_insert (f, vf, i); +} + +vector float +testf_cst (float f, vector float vf) +{ + return vec_insert (f, vf, 12); +} + +/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 1 } } */ +/* cst tests has stfs instead of stfsx. */ +/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M|\mlxvw4x\M} 2 } } */ + +/* cst test has a lvewx,vperm combo */ +/* { dg-final { scan-assembler-times {\mlvewx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvperm\M} 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c new file mode 100644 index 0000000..78ecad46 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c @@ -0,0 +1,31 @@ +/* Verify that overloaded built-ins for vec_insert with float + inputs produce the right codegen. Power9 variant. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power9" } */ + +#include + +vector float +testf_var (float f, vector float vf, signed int i) +{ + return vec_insert (f, vf, i); +} + +vector float +testf_cst (float f, vector float vf) +{ + return vec_insert (f, vf, 12); +} + +/* var test has a load and store. */ +/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstfsx\M} 1 } } */ + +/* cst test have a xscvdpspn,xxextractuw,xxinsertw combo */ +/* { dg-final { scan-assembler-times {\mxscvdpspn\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxxextractuw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxxinsertw\M} 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c new file mode 100644 index 0000000..228a290 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c @@ -0,0 +1,58 @@ +/* Verify that overloaded built-ins for vec_insert() with int + inputs produce the right codegen. Power8 variant. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power8" } */ + +#include + +vector bool int +testbi_var(unsigned int x, vector bool int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector signed int +testsi_var(signed int x, vector signed int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned int +testui1_var(signed int x, vector unsigned int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned int +testui2_var(unsigned int x, vector unsigned int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector bool int +testbi_cst(unsigned int x, vector bool int v) +{ + return vec_insert(x, v, 12); +} +vector signed int +testsi_cst(signed int x, vector signed int v) +{ + return vec_insert(x, v, 12); +} +vector unsigned int +testui1_cst(signed int x, vector unsigned int v) +{ + return vec_insert(x, v, 12); +} +vector unsigned int +testui2_cst(unsigned int x, vector unsigned int v) +{ + return vec_insert(x, v, 12); +} + +/* Each test has lvx (8). cst tests have additional lvewx. (4) */ +/* var tests have both stwx (4) and stvx (4). cst tests have stw (4).*/ +/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 12 } } */ +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 } } */ + +/* { dg-final { scan-assembler-times {\mlvewx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mvperm\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c new file mode 100644 index 0000000..97daf94 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c @@ -0,0 +1,62 @@ +/* Verify that overloaded built-ins for vec_insert() with int + inputs produce the right codegen. Power9 variant. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power9" } */ + +#include + +vector bool int +testbi_var(unsigned int x, vector bool int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector signed int +testsi_var(signed int x, vector signed int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned int +testui1_var(signed int x, vector unsigned int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned int +testui2_var(unsigned int x, vector unsigned int v, signed int i) +{ + return vec_insert(x, v, i); +} +vector bool int +testbi_cst(unsigned int x, vector bool int v) +{ + return vec_insert(x, v, 12); +} +vector signed int +testsi_cst(signed int x, vector signed int v) +{ + return vec_insert(x, v, 12); +} +vector unsigned int +testui1_cst(signed int x, vector unsigned int v) +{ + return vec_insert(x, v, 12); +} +vector unsigned int +testui2_cst(unsigned int x, vector unsigned int v) +{ + return vec_insert(x, v, 12); +} + + +/* load immediate, add, store, stb, load variable test. */ +/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstwx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 4 } } */ + +/* an insert and a move per constant test. */ +/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxinsertw\M} 4 } } */ + + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c new file mode 100644 index 0000000..f77dbf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c @@ -0,0 +1,69 @@ +/* Verify that overloaded built-ins for vec_insert() with long long + inputs produce the right codegen. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector bool long long +testbl_var(unsigned long long x, vector bool long long v, signed int i) +{ + return vec_insert(x, v, i); +} + +vector signed long long +testsl_var(signed long long x, vector signed long long v, signed int i) +{ + return vec_insert(x, v, i); +} + +vector unsigned long long +testul1_var(signed long long x, vector unsigned long long v, signed int i) +{ + return vec_insert(x, v, i); +} + +vector unsigned long long +testul2_var(unsigned long long x, vector unsigned long long v, signed int i) +{ + return vec_insert(x, v, i); +} + +vector bool long long +testbl_cst(unsigned long long x, vector bool long long v) +{ + return vec_insert(x, v, 12); +} + +vector signed long long +testsl_cst(signed long long x, vector signed long long v) +{ + return vec_insert(x, v, 12); +} + +vector unsigned long long +testul1_cst(signed long long x, vector unsigned long v) +{ + return vec_insert(x, v, 12); +} + +vector unsigned long long +testul2_cst(unsigned long long x, vector unsigned long long v) +{ + return vec_insert(x, v, 12); +} + +/* Number of xxpermdi insns varies between power targets. ensure at least one. */ +/* { dg-final { scan-assembler {\mxxpermdi\M} } } */ + +/* { dg-final { scan-assembler-times {\mrldic\M} 4 } } */ +/* The number of addi instructions decreases on newer systems. Measured as 8 on + power7 and power8 targets, and drops to 4 on power9 targets that use the + newer stxv,lxv instructions. For this test ensure we get at least one. */ +/* { dg-final { scan-assembler {\maddi\M} } } */ +/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstdx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 4 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c new file mode 100644 index 0000000..e99e867 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c @@ -0,0 +1,58 @@ +/* Verify that overloaded built-ins for vec_insert() with short + inputs produce the right codegen. Power8 variant. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power8" } */ + +#include + +vector bool short +testbs_var(unsigned short x, vector bool short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector signed short +testss_var(signed short x, vector signed short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned short +testus1_var(signed short x, vector unsigned short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned short +testus2_var(unsigned short x, vector unsigned short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector bool short +testbs_cst(signed short x, vector bool short v) +{ + return vec_insert(x, v, 12); +} +vector signed short +testss_cst(signed short x, vector signed short v) +{ + return vec_insert(x, v, 12); +} +vector unsigned short +testus1_cst(signed short x, vector unsigned short v) +{ + return vec_insert(x, v, 12); +} +vector unsigned short +testus2_cst(unsigned short x, vector unsigned short v) +{ + return vec_insert(x, v, 12); +} + +/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 } } */ +/* stores.. 2 each per variable tests, 1 each per cst test. */ +/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 12 } } */ + +/* { dg-final { scan-assembler-times {\mlvehx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mvperm\M} 4 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c new file mode 100644 index 0000000..a9024c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c @@ -0,0 +1,57 @@ +/* Verify that overloaded built-ins for vec_insert() with short + inputs produce the right codegen. Power9 variant. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-maltivec -O2 -mcpu=power9" } */ + +#include + +vector bool short +testbs_var(unsigned short x, vector bool short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector signed short +testss_var(signed short x, vector signed short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned short +testus1_var(signed short x, vector unsigned short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector unsigned short +testus2_var(unsigned short x, vector unsigned short v, signed int i) +{ + return vec_insert(x, v, i); +} +vector bool short +testbs_cst(signed short x, vector bool short v) +{ + return vec_insert(x, v, 12); +} +vector signed short +testss_cst(signed short x, vector signed short v) +{ + return vec_insert(x, v, 12); +} +vector unsigned short +testus1_cst(signed short x, vector unsigned short v) +{ + return vec_insert(x, v, 12); +} +vector unsigned short +testus2_cst(unsigned short x, vector unsigned short v) +{ + return vec_insert(x, v, 12); +} + +/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mvinserth\M} 4 } } */ + +/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 4 } } */ +