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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 10 Oct 2018 09:13:50 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w9AFDncq27525238 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Oct 2018 08:13:49 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7083EC6065; Wed, 10 Oct 2018 09:13:49 -0600 (MDT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 25B1AC605D; Wed, 10 Oct 2018 09:13:49 -0600 (MDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 10 Oct 2018 09:13:48 -0600 (MDT) Subject: [PATCH, rs6000] testcases for vec_mergee and vec_mergeo From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: Segher Boessenkool , Bill Schmidt , David Edelsohn Cc: GCC Patches Date: Wed, 10 Oct 2018 10:13:48 -0500 Mime-Version: 1.0 x-cbid: 18101015-0012-0000-0000-000016C5B20B X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009854; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000268; SDB=6.01100666; UDB=6.00569489; IPR=6.00880714; MB=3.00023696; MTD=3.00000008; XFM=3.00000015; UTC=2018-10-10 15:13:51 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18101015-0013-0000-0000-000054B4951A Message-Id: <1539184428.16697.54.camel@brimstone.rchland.ibm.com> X-IsSubscribed: yes Hi, Some additional testcases to exercise the vec_mergee and vec_mergeo intrinsics. Tested across assorted power linux platforms. OK for trunk? Thanks -Will [testsuite] 2018-10-10 Will Schmidt * gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: New. * gcc.target/powerpc/fold-vec-mergeeo-int.c: New. * gcc.target/powerpc/fold-vec-mergeeo-longlong.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c new file mode 100644 index 0000000..d711848 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c @@ -0,0 +1,46 @@ +/* Verify that overloaded built-ins for vec_splat with float and + double inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -mpower8-vector " } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include + +/* + vector float foo = vec_mergee (vector float, vector float); + vector float foo = vec_mergeo (vector float, vector float); + vector double foo = vec_mergee (vector double , vector double); + vector double foo = vec_mergeo (vector double , vector double); +*/ + +vector float +testf_ee (vector float vf1, vector float vf2) +{ + return vec_mergee (vf1, vf2); +} + +vector float +testf_eo (vector float vf1, vector float vf2) +{ + return vec_mergeo (vf1, vf2); +} + +vector double +testd_ee ( vector double vd1, vector double vd2) +{ + return vec_mergee (vd1, vd2); +} + +vector double +testd_eo ( vector double vd1, vector double vd2) +{ + return vec_mergeo (vd1, vd2); +} +/* Doubles will generate vmrg*w instructions. */ +/* { dg-final { scan-assembler-times "vmrgow" 1 } } */ +/* { dg-final { scan-assembler-times "vmrgew" 1 } } */ +/* Floats will generate some number of xxpermdi instructions. Ensure we get at least one. */ +/* { dg-final { scan-assembler "xxpermdi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c new file mode 100644 index 0000000..565f3ac --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c @@ -0,0 +1,48 @@ +/* Verify that overloaded built-ins for vec_mergee and vec_mergeo with int + inputs produce the right codegen. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include + +vector bool int +testbi_ee (vector bool int v1, vector bool int v2) +{ + return vec_mergee (v1, v2); +} + +vector signed int +testsi_ee (vector signed int v1, vector signed int v2) +{ + return vec_mergee (v1, v2); +} + +vector unsigned int +testui_ee (vector unsigned int v1, vector unsigned int v2) +{ + return vec_mergee (v1, v2); +} + +vector bool int +testbi_eo (vector bool int v1, vector bool int v2) +{ + return vec_mergeo (v1, v2); +} + +vector signed int +testsi_eo (vector signed int v1, vector signed int v2) +{ + return vec_mergeo (v1, v2); +} + +vector unsigned int +testui_eo (vector unsigned int v1, vector unsigned int v2) +{ + return vec_mergeo (v1, v2); +} +/* { dg-final { scan-assembler-times "vmrgew" 3 } } */ +/* { dg-final { scan-assembler-times "vmrgow" 3 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c new file mode 100644 index 0000000..a5e59bf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c @@ -0,0 +1,52 @@ +/* Verify that overloaded built-ins for vec_mergee and vec_mergeo + with long long inputs produce the right codegen. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include + + +vector bool long long +testbi_ee (vector bool long long v1, vector bool long long v2) +{ + return vec_mergee (v1, v2); +} + +vector bool long long +testbi_eo (vector bool long long v1, vector bool long long v2) +{ + return vec_mergeo (v1, v2); +} + +vector signed long long +testsi_ee (vector signed long long v1, vector signed long long v2) +{ + return vec_mergee (v1, v2); +} + +vector signed long long +testsi_eo (vector signed long long v1, vector signed long long v2) +{ + return vec_mergeo (v1, v2); +} + +vector unsigned long long +testui_ee (vector unsigned long long v1, vector unsigned long long v2) +{ + return vec_mergee (v1, v2); +} + +vector unsigned long long +testui_eo (vector unsigned long long v1, vector unsigned long long v2) +{ + return vec_mergeo (v1, v2); +} + +/* long long ... */ +/* vec_mergee and vec_mergeo codegen will consist of some number of + xxpermdi instructions that will vary. Ensure we get at least one. */ +/* { dg-final { scan-assembler "xxpermdi" } } */ +