From patchwork Sun Oct 8 04:35:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 822964 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y8rDW06yjz9t4V for ; Sun, 8 Oct 2017 15:36:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750884AbdJHEgX (ORCPT ); Sun, 8 Oct 2017 00:36:23 -0400 Received: from hermes.aosc.io ([199.195.250.187]:44596 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750771AbdJHEgW (ORCPT ); Sun, 8 Oct 2017 00:36:22 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 39FFD47529; Sun, 8 Oct 2017 04:36:18 +0000 (UTC) From: Icenowy Zheng To: Tejun Heo , Maxime Ripard , Chen-Yu Tsai Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH 1/2] dt-bindings: add binding for Allwinner R40 SATA AHCI controller Date: Sun, 8 Oct 2017 12:35:40 +0800 Message-Id: <20171008043541.48564-1-icenowy@aosc.io> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Allwinner R40 SoC contains a SATA AHCI controller like the one in A10/A20 SoCs, however a reset control and two power supplies are added to it. Add a binding document for it. As a dedicated binding document is needed now for the A10/A20/R40 AHCI controller, drop the A10 compatible line from generic platform AHCI controller binding document. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/ata/ahci-platform.txt | 1 - .../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index fedc213b5f1a..da6818b2c204 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -9,7 +9,6 @@ PHYs. Required properties: - compatible : compatible string, one of: - - "allwinner,sun4i-a10-ahci" - "brcm,iproc-ahci" - "hisilicon,hisi-ahci" - "cavium,octeon-7130-ahci" diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt new file mode 100644 index 000000000000..0eea78c14ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt @@ -0,0 +1,40 @@ +Allwinner A10/A20/R40 SoC SATA AHCI Controller + +Required properties: +- compatible : compatible string, one of: + - "allwinner,sun4i-a10-ahci" + - "allwinner,sun8i-r40-ahci" +- interrupts : the SATA IRQ +- reg : the register mapping +- clocks : the clocks needed by SATA controller, usually contains + an AHB clock and a mod clock + +Optional properties: +- target-supply : regulator for SATA target power + +Required properties for the following compatibles: + - "allwinner,sun8i-r40-ahci" +- resets : the reset control needed by SATA controller +- vdd1v2-supply : regulator for SATA controller's 1.2V VDD +- vdd2v5-supply : regulator for SATA controller's 2.5V VDD + + +Examples for A10: + ahci: sata@1c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = <&pll6 0>, <&ahb_gates 25>; + target-supply = <®_ahci_5v>; + }; + +Examples for R40: + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_SATA>, <&ccu CLK_BUS_SATA>; + resets = <&ccu RST_BUS_SATA>; + vdd1v2-supply = <®_eldo3>; + vdd2v5-supply = <®_dldo4>; + };