From patchwork Mon Oct 8 05:34:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 980336 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42T8Gt5qJSz9s55 for ; Mon, 8 Oct 2018 16:36:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 298ACC21F75; Mon, 8 Oct 2018 05:36:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.2 required=5.0 tests=RDNS_DYNAMIC, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A59B0C21EFF; Mon, 8 Oct 2018 05:35:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B676C21DD9; Mon, 8 Oct 2018 05:35:56 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 6A3F9C21DB3 for ; Mon, 8 Oct 2018 05:35:55 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id w985cTdd074205; Mon, 8 Oct 2018 13:38:29 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.12.145) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Mon, 8 Oct 2018 13:35:40 +0800 From: Andes To: Date: Mon, 8 Oct 2018 13:34:12 +0800 Message-ID: <20181008053412.17883-1-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Originating-IP: [10.0.12.145] X-DNSRBL: X-MAIL: ATCSQR.andestech.com w985cTdd074205 Cc: rickchen36@gmail.com, greentime@andestech.com Subject: [U-Boot] [PATCH 1/2] riscv: configs: Separate ax25-ae350 for 32/64 bit. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Separate ax25-ae350 from one to two for 32 and 64 bit individually. And also select different dts for 32 and 64 bit. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ax25-ae350-32_defconfig | 33 +++++++++++++++++++++++++++++++++ configs/ax25-ae350-64_defconfig | 34 ++++++++++++++++++++++++++++++++++ configs/ax25-ae350_defconfig | 34 ---------------------------------- 3 files changed, 67 insertions(+), 34 deletions(-) create mode 100644 configs/ax25-ae350-32_defconfig create mode 100644 configs/ax25-ae350-64_defconfig delete mode 100644 configs/ax25-ae350_defconfig diff --git a/configs/ax25-ae350-32_defconfig b/configs/ax25-ae350-32_defconfig new file mode 100644 index 0000000..9126c39 --- /dev/null +++ b/configs/ax25-ae350-32_defconfig @@ -0,0 +1,33 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +CONFIG_ATCPIT100_TIMER=y diff --git a/configs/ax25-ae350-64_defconfig b/configs/ax25-ae350-64_defconfig new file mode 100644 index 0000000..7923050 --- /dev/null +++ b/configs/ax25-ae350-64_defconfig @@ -0,0 +1,34 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_AX25_AE350=y +CONFIG_CPU_RISCV_64=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +CONFIG_ATCPIT100_TIMER=y diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig deleted file mode 100644 index 614ef15..0000000 --- a/configs/ax25-ae350_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_RISCV=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_TARGET_AX25_AE350=y -CONFIG_CPU_RISCV_64=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_CMD_IMLS=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SF_TEST=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_PREFER_SERVERIP=y -CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y -CONFIG_DEFAULT_DEVICE_TREE="ae350" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_MMC=y -CONFIG_FTSDC010=y -CONFIG_FTSDC010_SDIO=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_CFI_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_FTMAC100=y -CONFIG_BAUDRATE=38400 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_ATCSPI200_SPI=y -CONFIG_ATCPIT100_TIMER=y From patchwork Mon Oct 8 05:35:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 980339 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42T8Hr5V9wz9s55 for ; Mon, 8 Oct 2018 16:36:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 735FDC21F4F; Mon, 8 Oct 2018 05:36:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C6454C21DD9; Mon, 8 Oct 2018 05:36:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C75B7C21DD9; Mon, 8 Oct 2018 05:36:46 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 8670EC21DB3 for ; Mon, 8 Oct 2018 05:36:45 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id w985dKhw074379; Mon, 8 Oct 2018 13:39:20 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.12.145) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Mon, 8 Oct 2018 13:36:31 +0800 From: Andes To: Date: Mon, 8 Oct 2018 13:35:03 +0800 Message-ID: <20181008053503.18240-1-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Originating-IP: [10.0.12.145] X-DNSRBL: X-MAIL: ATCSQR.andestech.com w985dKhw074379 Cc: rickchen36@gmail.com, greentime@andestech.com Subject: [U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 229 -------------------------------------------- arch/riscv/dts/ae350_32.dts | 229 ++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/dts/ae350_64.dts | 229 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 458 insertions(+), 229 deletions(-) delete mode 100644 arch/riscv/dts/ae350.dts create mode 100644 arch/riscv/dts/ae350_32.dts create mode 100644 arch/riscv/dts/ae350_64.dts diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts deleted file mode 100644 index e48c298..0000000 --- a/arch/riscv/dts/ae350.dts +++ /dev/null @@ -1,229 +0,0 @@ -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,ax25"; - model = "andestech,ax25"; - - aliases { - uart0 = &serial0; - spi0 = &spi; - }; - - chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; - stdout-path = "uart0:38400n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <60000000>; - CPU0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv39"; - clock-frequency = <60000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <32>; - CPU0_intc: interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,riscv-ae350-soc"; - ranges; - - plic0: interrupt-controller@e4000000 { - compatible = "riscv,plic0"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe4000000 0x0 0x2000000>; - riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; - }; - - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe6400000 0x0 0x400000>; - riscv,ndev=<1>; - interrupts-extended = <&CPU0_intc 3>; - }; - - plmt0@e6000000 { - compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7>; - reg = <0x0 0xe6000000 0x0 0x100000>; - }; - }; - - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0x0 0xf0400000 0x0 0x1000>; - clock-frequency = <60000000>; - interrupts = <3 4>; - interrupt-parent = <&plic0>; - }; - - serial0: serial@f0300000 { - compatible = "andestech,uart16550", "ns16550a"; - reg = <0x0 0xf0300000 0x0 0x1000>; - interrupts = <9 4>; - clock-frequency = <19660800>; - reg-shift = <2>; - reg-offset = <32>; - no-loopback-test = <1>; - interrupt-parent = <&plic0>; - }; - - mac0: mac@e0100000 { - compatible = "andestech,atmac100"; - reg = <0x0 0xe0100000 0x0 0x1000>; - interrupts = <19 4>; - interrupt-parent = <&plic0>; - }; - - mmc0: mmc@f0e00000 { - compatible = "andestech,atfsdc010"; - max-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - fifo-depth = <0x10>; - reg = <0x0 0xf0e00000 0x0 0x1000>; - interrupts = <18 4>; - cap-sd-highspeed; - interrupt-parent = <&plic0>; - }; - - dma0: dma@f0c00000 { - compatible = "andestech,atcdmac300"; - reg = <0x0 0xf0c00000 0x0 0x1000>; - interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; - dma-channels = <8>; - interrupt-parent = <&plic0>; - }; - - lcd0: lcd@e0200000 { - compatible = "andestech,atflcdc100"; - reg = <0x0 0xe0200000 0x0 0x1000>; - interrupts = <20 4>; - interrupt-parent = <&plic0>; - }; - - smc0: smc@e0400000 { - compatible = "andestech,atfsmc020"; - reg = <0x0 0xe0400000 0x0 0x1000>; - }; - - snd0: snd@f0d00000 { - compatible = "andestech,atfac97"; - reg = <0x0 0xf0d00000 0x0 0x1000>; - interrupts = <17 4>; - interrupt-parent = <&plic0>; - }; - - virtio_mmio@fe007000 { - interrupts = <0x17 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe007000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe006000 { - interrupts = <0x16 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe006000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe005000 { - interrupts = <0x15 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe005000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe004000 { - interrupts = <0x14 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe004000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe003000 { - interrupts = <0x13 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe003000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe002000 { - interrupts = <0x12 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe002000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe001000 { - interrupts = <0x11 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe001000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe000000 { - interrupts = <0x10 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe000000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x88000000 0x0 0x1000>; - bank-width = <2>; - device-width = <1>; - }; - - spi: spi@f0b00000 { - compatible = "andestech,atcspi200"; - reg = <0x0 0xf0b00000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - clocks = <&spiclk>; - interrupts = <4 4>; - interrupt-parent = <&plic0>; - flash@0 { - compatible = "spi-flash"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-cpol; - spi-cpha; - }; - }; -}; diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts new file mode 100644 index 0000000..33bbea8 --- /dev/null +++ b/arch/riscv/dts/ae350_32.dts @@ -0,0 +1,229 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <60000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "andestech,riscv-ae350-soc"; + ranges; + + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe4000000 0x2000000>; + riscv,ndev=<71>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + }; + + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe6400000 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; + + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0xe6000000 0x100000>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + clock-frequency = <60000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <9 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + interrupt-parent = <&plic0>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <18 4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + }; + + dma0: dma@f0c00000 { + compatible = "andestech,atcdmac300"; + reg = <0xf0c00000 0x1000>; + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; + dma-channels = <8>; + interrupt-parent = <&plic0>; + }; + + lcd0: lcd@e0200000 { + compatible = "andestech,atflcdc100"; + reg = <0xe0200000 0x1000>; + interrupts = <20 4>; + interrupt-parent = <&plic0>; + }; + + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0xe0400000 0x1000>; + }; + + snd0: snd@f0d00000 { + compatible = "andestech,atfac97"; + reg = <0xf0d00000 0x1000>; + interrupts = <17 4>; + interrupt-parent = <&plic0>; + }; + + virtio_mmio@fe007000 { + interrupts = <0x17 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe007000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe006000 { + interrupts = <0x16 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe006000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe005000 { + interrupts = <0x15 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe005000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe004000 { + interrupts = <0x14 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe004000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe003000 { + interrupts = <0x13 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe003000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe002000 { + interrupts = <0x12 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe002000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe001000 { + interrupts = <0x11 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe001000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe000000 { + interrupts = <0x10 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe000000 0x1000>; + compatible = "virtio,mmio"; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x88000000 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <4 4>; + interrupt-parent = <&plic0>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts new file mode 100644 index 0000000..e48c298 --- /dev/null +++ b/arch/riscv/dts/ae350_64.dts @@ -0,0 +1,229 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <60000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,riscv-ae350-soc"; + ranges; + + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe4000000 0x0 0x2000000>; + riscv,ndev=<71>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + }; + + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe6400000 0x0 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; + + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0x0 0xf0400000 0x0 0x1000>; + clock-frequency = <60000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x0 0xf0300000 0x0 0x1000>; + interrupts = <9 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + interrupt-parent = <&plic0>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0x0 0xe0100000 0x0 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0x0 0xf0e00000 0x0 0x1000>; + interrupts = <18 4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + }; + + dma0: dma@f0c00000 { + compatible = "andestech,atcdmac300"; + reg = <0x0 0xf0c00000 0x0 0x1000>; + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; + dma-channels = <8>; + interrupt-parent = <&plic0>; + }; + + lcd0: lcd@e0200000 { + compatible = "andestech,atflcdc100"; + reg = <0x0 0xe0200000 0x0 0x1000>; + interrupts = <20 4>; + interrupt-parent = <&plic0>; + }; + + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0x0 0xe0400000 0x0 0x1000>; + }; + + snd0: snd@f0d00000 { + compatible = "andestech,atfac97"; + reg = <0x0 0xf0d00000 0x0 0x1000>; + interrupts = <17 4>; + interrupt-parent = <&plic0>; + }; + + virtio_mmio@fe007000 { + interrupts = <0x17 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe007000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe006000 { + interrupts = <0x16 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe006000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe005000 { + interrupts = <0x15 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe005000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe004000 { + interrupts = <0x14 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe004000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe003000 { + interrupts = <0x13 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe003000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe002000 { + interrupts = <0x12 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe002000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe001000 { + interrupts = <0x11 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe001000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe000000 { + interrupts = <0x10 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe000000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x88000000 0x0 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0x0 0xf0b00000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <4 4>; + interrupt-parent = <&plic0>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; +};