From patchwork Sun Oct 7 07:16:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 980023 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="uQM3TL34"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42SZYB1V8JzB2xQ for ; Sun, 7 Oct 2018 18:16:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 45E18C21ECF; Sun, 7 Oct 2018 07:16:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 68A29C21DB3; Sun, 7 Oct 2018 07:16:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F3A3BC21DB3; Sun, 7 Oct 2018 07:16:14 +0000 (UTC) Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by lists.denx.de (Postfix) with ESMTPS id 63D5DC21CB1 for ; Sun, 7 Oct 2018 07:16:14 +0000 (UTC) Received: by mail-wr1-f47.google.com with SMTP id a2-v6so10347937wrc.13 for ; Sun, 07 Oct 2018 00:16:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Ue24yK66MFSZ4F3FD6D+tECk5NKXrIeN4dMAuVWez/M=; b=uQM3TL34y7uAXFT8Uh+L3ow0RsZ7XRC4vX9pKlAISUmgVRQQwa7EY9kUVkIk2tLx0f lUawMbUCHHUftXwN3G5Glbu7nM3u5RBaakh/3p4OzNv+rp1N1mjDfUNId4mymGGLwSXL ib7cVX0osM6Ga4svBUCWmIRzrC+5P/dz33HWviIuWM6Es1IZD3kD5u0rdc813v/oOmCy tw3SOTK5MRzIzZ2fGpVbi+qLBpgDBtHqWTYCZJ2CNeKvuqlOgkW0dXAa0VJ1hrn/ybsj igLpXpW2ewmGSra4M2Tl18CEGz9lAJ9ZgqNwVlAiA0HBVIVCMwcCdUbVylx473v77bLT mRTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Ue24yK66MFSZ4F3FD6D+tECk5NKXrIeN4dMAuVWez/M=; b=hfd31EMELHt4jGcFNM2k3uxgD1/Q1kft13/AvpMEkQhJSoL8tElbdCFzkmAuncNZ16 TyUhikuJtYyQ5LVMGUWg4Qiu8z2gylvs85QtytLi1Y0eyQwlHumVcZU09lQ7bB9Lv+34 RIkbPx+GxLdDxSIyRb4j74jKi5aHrl+PO00ZhnJAzq3e4bj81R+7k2v+2bCM/zZN96oC A7I0tY2rT+6taaBlBjNE7QSaUueroSymVgoPIgRN5AT81lnUXdRu3WeNKJbUUAcE4pna FZHEk3i+Oniva39m3U5CXBMeA/pS7Fw7KBYV62jQ4qUrKZon0M7qbWyPTLtwMKQ0g7ok 4lWA== X-Gm-Message-State: ABuFfojyVNUnP+4ahZPgh6JJymvpNNcAqXQ7Nn9Qx+E70xXGLsSGwH1i cjsA5PxF4hysx4GQsScB3E0= X-Google-Smtp-Source: ACcGV60cxsLeKAAA0f74F58VKcX3f/a6Sx2OAM0hbX+lBkdH9Za5itPWDcEz43Yzp9nQ2Cz0RuxQiQ== X-Received: by 2002:adf:d082:: with SMTP id y2-v6mr6613852wrh.314.1538896573458; Sun, 07 Oct 2018 00:16:13 -0700 (PDT) Received: from ubuntu.home ([2a02:8071:6a3:700:6d78:dde7:de55:d75a]) by smtp.gmail.com with ESMTPSA id b2-v6sm9634192wru.51.2018.10.07.00.16.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Oct 2018 00:16:12 -0700 (PDT) From: Simon Goldschmidt To: Jagan Teki Date: Sun, 7 Oct 2018 09:16:01 +0200 Message-Id: <20181007071601.12302-1-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 Cc: u-boot@lists.denx.de, Jagan Teki Subject: [U-Boot] [PATCH v2] sf: remove spi-flash chip names from SPL binary X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The table of spi flash chips 'spi_flash_ids' currently includes chip names. The only usage of these is to print the name when the chip is probed. Since this message is not shown in SPL, we can remove the names from the SPL binary. Removing the chip names saves ~890 Byte from the SPL binary in my configuration (socfpga_socrates_defconfig, MACRONIX, SPANSION and STMICRO enabled). Signed-off-by: Simon Goldschmidt --- Changes in v2: - use CONFIG_SPL_BUILD directly instead of SPI_FLASH_INCLUDE_NAME - iterate spi_flash_ids list until info->sector_size == 0, remove the extra global 'const size_t spi_flash_ids_size' drivers/mtd/spi/sf_internal.h | 3 + drivers/mtd/spi/spi_flash.c | 6 +- drivers/mtd/spi/spi_flash_ids.c | 269 +++++++++++++++++--------------- 3 files changed, 147 insertions(+), 131 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4f63cacc64..dab3a5bfbc 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -114,8 +114,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, #define SPI_FLASH_MAX_ID_LEN 6 struct spi_flash_info { +/* Exclude chip names for SPL to save space */ +#ifndef CONFIG_SPL_BUILD /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ const char *name; +#endif /* * This array stores the ID bytes. diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124259..e6d0fa5fcf 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1069,7 +1069,7 @@ static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) } info = spi_flash_ids; - for (; info->name != NULL; info++) { + for (; info->sector_size != 0; info++) { if (info->id_len) { if (!memcmp(info->id, id, info->id_len)) return info; @@ -1160,7 +1160,11 @@ int spi_flash_scan(struct spi_flash *flash) write_sr(flash, sr); } +#ifndef CONFIG_SPL_BUILD flash->name = info->name; +#else + flash->name = "spi-flash"; +#endif flash->memory_map = spi->memory_map; if (info->flags & SST_WR) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index e662e4b42e..dd3033b1b8 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -12,8 +12,16 @@ #include "sf_internal.h" +/* Exclude chip names for SPL to save space */ +#ifndef CONFIG_SPL_BUILD +#define INFO_NAME(_name) .name = _name, +#else +#define INFO_NAME(_name) +#endif + /* Used when the "_ext_id" is two bytes at most */ -#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ +#define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + INFO_NAME(_name) \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -27,7 +35,8 @@ .page_size = 256, \ .flags = (_flags), -#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ +#define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + INFO_NAME(_name) \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -44,150 +53,150 @@ const struct spi_flash_info spi_flash_ids[] = { #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, - {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, - {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, - {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, - {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, - {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, - {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, - {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, - {"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, - {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, + {INFO("at45db011d", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, + {INFO("at45db021d", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("at45db041d", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("at45db081d", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, + {INFO("at45db161d", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("at45db321d", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("at45db641d", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("at25df321a", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("at25df321", 0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("at26df081a", 0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, - {"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, - {"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, - {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, + {INFO("en25q32b", 0x1c3016, 0x0, 64 * 1024, 64, 0) }, + {INFO("en25q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("en25q128b", 0x1c3018, 0x0, 64 * 1024, 256, 0) }, + {INFO("en25s64", 0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"gd25q16c", INFO(0xc84015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, - {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, - {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("gd25q16c", 0xc84015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("gd25q64b", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("gd25q32b", 0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("gd25lq32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ - {"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) }, - {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, - {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, - {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, - {"is25lp256", INFO(0x9d6019, 0x0, 64 * 1024, 512, 0) }, - {"is25wp032", INFO(0x9d7016, 0x0, 64 * 1024, 64, RD_FULL | SECT_4K) }, - {"is25wp064", INFO(0x9d7017, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, - {"is25wp128", INFO(0x9d7018, 0x0, 64 * 1024, 256, RD_FULL | SECT_4K) }, + {INFO("is25lq040b", 0x9d4013, 0x0, 64 * 1024, 8, 0) }, + {INFO("is25lp032", 0x9d6016, 0x0, 64 * 1024, 64, 0) }, + {INFO("is25lp064", 0x9d6017, 0x0, 64 * 1024, 128, 0) }, + {INFO("is25lp128", 0x9d6018, 0x0, 64 * 1024, 256, 0) }, + {INFO("is25lp256", 0x9d6019, 0x0, 64 * 1024, 512, 0) }, + {INFO("is25wp032", 0x9d7016, 0x0, 64 * 1024, 64, RD_FULL | SECT_4K) }, + {INFO("is25wp064", 0x9d7017, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, + {INFO("is25wp128", 0x9d7018, 0x0, 64 * 1024, 256, RD_FULL | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, - {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, - {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, - {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, - {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, - {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, - {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, - {"mx25l1633e", INFO(0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, - {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, - {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, - {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + {INFO("mx25l2006e", 0xc22012, 0x0, 64 * 1024, 4, 0) }, + {INFO("mx25l4005", 0xc22013, 0x0, 64 * 1024, 8, 0) }, + {INFO("mx25l8005", 0xc22014, 0x0, 64 * 1024, 16, 0) }, + {INFO("mx25l1605d", 0xc22015, 0x0, 64 * 1024, 32, 0) }, + {INFO("mx25l3205d", 0xc22016, 0x0, 64 * 1024, 64, 0) }, + {INFO("mx25l6405d", 0xc22017, 0x0, 64 * 1024, 128, 0) }, + {INFO("mx25l12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("mx25l25635f", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {INFO("mx25l51235f", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {INFO("mx25l1633e", 0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("mx25u6435f", 0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {INFO("mx25l12855e", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("mx25u1635e", 0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("mx25u25635f", 0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {INFO("mx66u51235f", 0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {INFO("mx66l1g45g", 0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, - {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, - {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, - {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, - {"s25fl208k", INFO(0x014014, 0x0, 64 * 1024, 16, 0) }, - {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) }, - {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, - {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, - {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, - {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, - {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, - {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, - {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, - {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl008a", 0x010213, 0x0, 64 * 1024, 16, 0) }, + {INFO("s25fl016a", 0x010214, 0x0, 64 * 1024, 32, 0) }, + {INFO("s25fl032a", 0x010215, 0x0, 64 * 1024, 64, 0) }, + {INFO("s25fl064a", 0x010216, 0x0, 64 * 1024, 128, 0) }, + {INFO("s25fl208k", 0x014014, 0x0, 64 * 1024, 16, 0) }, + {INFO("s25fl116k", 0x014015, 0x0, 64 * 1024, 32, 0) }, + {INFO("s25fl164k", 0x014017, 0x0140, 64 * 1024, 128, 0) }, + {INFO("s25fl128p_256k", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {INFO("s25fl128p_64k", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl032p", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, + {INFO("s25fl064p", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {INFO("s25fl128s_256k", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {INFO("s25fl128s_64k", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl256s_256k", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, + {INFO6("s25fs256s_64k", 0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("s25fl256s_64k", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, - {"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, - {"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, - {"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, - {"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, - {"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, - {"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, - {"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, - {"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, - {"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, - {"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, - {"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, - {"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, + {INFO("m25p10", 0x202011, 0x0, 32 * 1024, 4, 0) }, + {INFO("m25p20", 0x202012, 0x0, 64 * 1024, 4, 0) }, + {INFO("m25p40", 0x202013, 0x0, 64 * 1024, 8, 0) }, + {INFO("m25p80", 0x202014, 0x0, 64 * 1024, 16, 0) }, + {INFO("m25p16", 0x202015, 0x0, 64 * 1024, 32, 0) }, + {INFO("m25pE16", 0x208015, 0x1000, 64 * 1024, 32, 0) }, + {INFO("m25pX16", 0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, + {INFO("m25p32", 0x202016, 0x0, 64 * 1024, 64, 0) }, + {INFO("m25p64", 0x202017, 0x0, 64 * 1024, 128, 0) }, + {INFO("m25p128", 0x202018, 0x0, 256 * 1024, 64, 0) }, + {INFO("m25pX64", 0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("n25q016a", 0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("n25q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q32a", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q64a", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("n25q128a", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("n25q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q256a", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q512a", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q1024a", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("mt25qu02g", 0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("mt25ql02g", 0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO6("mt35xu512g", 0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, - {"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, - {"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, - {"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, - {"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, - {"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, - {"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, - {"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, - {"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, - {"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, - {"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, - {"sst26wf016", INFO(0xbf2651, 0x0, 64 * 1024, 32, SECT_4K) }, - {"sst26wf032", INFO(0xbf2622, 0x0, 64 * 1024, 64, SECT_4K) }, - {"sst26wf064", INFO(0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("sst25vf040b", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {INFO("sst25vf080b", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + {INFO("sst25vf016b", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, + {INFO("sst25vf032b", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, + {INFO("sst25vf064c", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("sst25wf512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, + {INFO("sst25wf010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, + {INFO("sst25wf020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, + {INFO("sst25wf040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {INFO("sst25wf040b", 0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("sst25wf080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + {INFO("sst26wf016", 0xbf2651, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("sst26wf032", 0xbf2622, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("sst26wf064", 0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, - {"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, - {"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, - {"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, - {"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, - {"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, - {"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, - {"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q16jv", INFO(0xef7015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q32jv", INFO(0xef7016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q64jv", INFO(0xef7017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q128jv", INFO(0xef7018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q256fw", INFO(0xef6019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q256jw", INFO(0xef7019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, + {INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, + {INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, + {INFO("w25x40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("w25x16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("w25x32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("w25x64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("w25q80bl", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q16cl", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q32bv", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q64cv", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q128bv", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q80bw", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q16dw", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q16jv", 0xef7015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q32dw", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q32jv", 0xef7016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q64dw", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q64jv", 0xef7017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q128fw", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q128jv", 0xef7018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q256fw", 0xef6019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q256jw", 0xef7019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, #endif {}, /* Empty entry to terminate the list */ /*