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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id b193-v6sm527380wmg.44.2018.10.02.22.43.38 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 02 Oct 2018 22:43:38 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de Date: Wed, 3 Oct 2018 07:43:34 +0200 Message-Id: X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH] arm64: gic: Do gicv3 secure initialization based on EL level X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Do gic cpu initialization based on EL level which u-boot enters. U-Boot can't access EL3 regs when runs in EL2/EL1, etc. Signed-off-by: Michal Simek --- arch/arm/lib/gic_64.S | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 745c7858da79..155212a419be 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -107,6 +107,8 @@ ENTRY(gic_init_secure_percpu) mov w11, #0x1 /* Enable SGI 0 */ str w11, [x10, GICR_ISENABLERn] + switch_el x10, 3f, 2f, 1f +3: /* Initialize Cpu Interface */ mrs x10, ICC_SRE_EL3 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ @@ -114,19 +116,19 @@ ENTRY(gic_init_secure_percpu) msr ICC_SRE_EL3, x10 isb - mrs x10, ICC_SRE_EL2 - orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ - /* Allow EL1 access to ICC_SRE_EL1 */ - msr ICC_SRE_EL2, x10 - isb - mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */ msr ICC_IGRPEN1_EL3, x10 isb msr ICC_CTLR_EL3, xzr isb - +2: + mrs x10, ICC_SRE_EL2 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL1 access to ICC_SRE_EL1 */ + msr ICC_SRE_EL2, x10 + isb +1: msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */ isb