From patchwork Fri Oct 6 10:13:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lq23xnvz9t4R for ; Fri, 6 Oct 2017 21:14:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751883AbdJFKOE (ORCPT ); Fri, 6 Oct 2017 06:14:04 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50766 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751663AbdJFKOD (ORCPT ); Fri, 6 Oct 2017 06:14:03 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id AD2FD209A4; Fri, 6 Oct 2017 12:14:00 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 473DD20909; Fri, 6 Oct 2017 12:14:00 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 01/16] dt-bindings: mvebu-uart: update documentation with extended UART Date: Fri, 6 Oct 2017 12:13:29 +0200 Message-Id: <20171006101344.15590-2-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Update the Device Tree binding documentation for the Marvell EBU UART, in order to allow describing the extended UART IP block, in addition to the already supported standard UART IP. This requires adding a new compatible string, the introduction of a clocks property, and extensions to the interrupts property. Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- .../devicetree/bindings/serial/mvebu-uart.txt | 49 +++++++++++++++++++--- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt index d37fabe17bd1..3df3a3fab4bb 100644 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt @@ -1,13 +1,52 @@ -* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., Armada-3700) +* Marvell UART : Non standard UART used in some of Marvell EBU SoCs + e.g., Armada-3700. Required properties: -- compatible: "marvell,armada-3700-uart" +- compatible: + - "marvell,armada-3700-uart" for the standard variant of the UART + (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the + FIFO, baudrate limited to 230400). + - "marvell,armada-3700-uart-ext" for the extended variant of the + UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit + accesses to the FIFO, baudrate unlimited by the dividers). - reg: offset and length of the register set for the device. -- interrupts: device interrupt +- clocks: UART reference clock used to derive the baudrate (only + mandatory with "marvell,armada-3700-uart-ext" compatible). +- interrupts: + - Must contain three elements for the standard variant of the IP + (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx", + respectively the UART sum interrupt, the UART TX interrupt and + UART RX interrupt. A corresponding interrupt-names property must + be defined. + - Must contain two elements for the extended variant of the IP + (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx", + respectively the UART TX interrupt and the UART RX interrupt. A + corresponding interrupts-names property must be defined. + - For backward compatibility reasons, a single element interrupts + property is also supported for the standard variant of the IP, + containing only the UART sum interrupt. This form is deprecated + and should no longer be used. Example: - serial@12000 { + uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x200>; - interrupts = <43>; + clocks = <&xtalclk>; + interrupts = + , + , + ; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + status = "disabled"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&xtalclk>; + interrupts = + , + ; + interrupt-names = "uart-tx", "uart-rx"; + status = "disabled"; }; From patchwork Fri Oct 6 10:13:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqq3YtBz9t48 for ; Fri, 6 Oct 2017 21:14:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751892AbdJFKOI (ORCPT ); Fri, 6 Oct 2017 06:14:08 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50781 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751888AbdJFKOG (ORCPT ); Fri, 6 Oct 2017 06:14:06 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id C22F2209A9; Fri, 6 Oct 2017 12:14:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5C8A6209A2; Fri, 6 Oct 2017 12:14:03 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 02/16] pinctrl: dt-bindings: Fix A37xx uart2 group name Date: Fri, 6 Oct 2017 12:13:30 +0200 Message-Id: <20171006101344.15590-3-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix a typo in A37xx pin controllers documentation about uart2 pin group. Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- .../devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt index f64060908d5a..c7c088d2dd50 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt @@ -97,8 +97,8 @@ group spi_quad - pins 15-16 - functions spi, gpio -group uart_2 - - pins 9-10 +group uart2 + - pins 9-10 and 18-19 - functions uart, gpio Available groups and functions for the South bridge: From patchwork Fri Oct 6 10:13:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822327 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqm5mqqz9t5C for ; Fri, 6 Oct 2017 21:14:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751604AbdJFKOJ (ORCPT ); Fri, 6 Oct 2017 06:14:09 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50793 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751663AbdJFKOH (ORCPT ); Fri, 6 Oct 2017 06:14:07 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id EA95E209AC; Fri, 6 Oct 2017 12:14:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 7DFB420909; Fri, 6 Oct 2017 12:14:04 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Yehuda Yitschak , Miquel Raynal Subject: [PATCH 03/16] serial: mvebu-uart: use driver name when requesting an interrupt Date: Fri, 6 Oct 2017 12:13:31 +0200 Message-Id: <20171006101344.15590-4-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Yehuda Yitschak Use the driver name when requesting an interrupt for consistency. Avoids possible confusion with DW8250 driver interrupt names in /proc/interrupts. Signed-off-by: Yehuda Yitschak Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 45b57c294d13..7e0a3e9fee15 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -90,6 +90,7 @@ #define MVEBU_NR_UARTS 1 #define MVEBU_UART_TYPE "mvebu-uart" +#define DRIVER_NAME "mvebu_serial" static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; @@ -287,8 +288,8 @@ static int mvebu_uart_startup(struct uart_port *port) udelay(1); writel(CTRL_RX_INT, port->membase + UART_CTRL); - ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial", - port); + ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, + DRIVER_NAME, port); if (ret) { dev_err(port->dev, "failed to request irq\n"); return ret; @@ -538,7 +539,7 @@ console_initcall(mvebu_uart_console_init); static struct uart_driver mvebu_uart_driver = { .owner = THIS_MODULE, - .driver_name = "mvebu_serial", + .driver_name = DRIVER_NAME, .dev_name = "ttyMV", .nr = MVEBU_NR_UARTS, #ifdef CONFIG_SERIAL_MVEBU_CONSOLE From patchwork Fri Oct 6 10:13:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822313 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqC0T3Lz9t48 for ; Fri, 6 Oct 2017 21:14:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751663AbdJFKOK (ORCPT ); Fri, 6 Oct 2017 06:14:10 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50807 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751717AbdJFKOJ (ORCPT ); Fri, 6 Oct 2017 06:14:09 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 4D93D209AE; Fri, 6 Oct 2017 12:14:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id D3DFC209A2; Fri, 6 Oct 2017 12:14:05 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Allen Yan , Miquel Raynal Subject: [PATCH 04/16] serial: mvebu-uart: support probe of multiple ports Date: Fri, 6 Oct 2017 12:13:32 +0200 Message-Id: <20171006101344.15590-5-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Allen Yan Until now, the mvebu-uart driver only supported probing a single UART port. However, some platforms have multiple instances of this UART controller, and therefore the driver should support multiple ports. In order to achieve this, we make sure to assign port->line properly, instead of hardcoding it to zero. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal --- drivers/tty/serial/mvebu-uart.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 7e0a3e9fee15..25b11ede3a97 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -560,7 +560,16 @@ static int mvebu_uart_probe(struct platform_device *pdev) return -EINVAL; } - port = &mvebu_uart_ports[0]; + if (pdev->dev.of_node) + pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); + + if (pdev->id >= MVEBU_NR_UARTS) { + dev_err(&pdev->dev, "cannot have more than %d UART ports\n", + MVEBU_NR_UARTS); + return -EINVAL; + } + + port = &mvebu_uart_ports[pdev->id]; spin_lock_init(&port->lock); @@ -572,7 +581,7 @@ static int mvebu_uart_probe(struct platform_device *pdev) port->fifosize = 32; port->iotype = UPIO_MEM32; port->flags = UPF_FIXED_PORT; - port->line = 0; /* single port: force line number to 0 */ + port->line = pdev->id; port->irq = irq->start; port->irqflags = 0; From patchwork Fri Oct 6 10:13:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqG0GVpz9t48 for ; Fri, 6 Oct 2017 21:14:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751932AbdJFKOP (ORCPT ); Fri, 6 Oct 2017 06:14:15 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50819 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751888AbdJFKOK (ORCPT ); Fri, 6 Oct 2017 06:14:10 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id D5335209AD; Fri, 6 Oct 2017 12:14:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 60A3620909; Fri, 6 Oct 2017 12:14:07 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 05/16] serial: mvebu-uart: use a generic way to access the registers Date: Fri, 6 Oct 2017 12:13:33 +0200 Message-Id: <20171006101344.15590-6-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org There are two UART ports on Armada3700. The second UART is based on the first one, plus additional features, but it has a different register layout (some bit fields are also moved inside the registers). Clearly separate register offsets and bit fields that differ between the standard and the extended IP. Access them in a generic way. Rename the defines with the "STD" prefix for future distinction with "EXT" defines. Point to these defines in the main driver data structure. The early console only uses the standard port (not extended). Suggested-by: Wilson Ding Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 213 ++++++++++++++++++++++++++-------------- 1 file changed, 140 insertions(+), 73 deletions(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 25b11ede3a97..82438884af1e 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -38,46 +38,32 @@ #include /* Register Map */ -#define UART_RBR 0x00 -#define RBR_BRK_DET BIT(15) -#define RBR_FRM_ERR_DET BIT(14) -#define RBR_PAR_ERR_DET BIT(13) -#define RBR_OVR_ERR_DET BIT(12) +#define UART_STD_RBR 0x00 -#define UART_TSH 0x04 +#define UART_STD_TSH 0x04 -#define UART_CTRL 0x08 +#define UART_STD_CTRL1 0x08 #define CTRL_SOFT_RST BIT(31) #define CTRL_TXFIFO_RST BIT(15) #define CTRL_RXFIFO_RST BIT(14) -#define CTRL_ST_MIRR_EN BIT(13) -#define CTRL_LPBK_EN BIT(12) #define CTRL_SND_BRK_SEQ BIT(11) -#define CTRL_PAR_EN BIT(10) -#define CTRL_TWO_STOP BIT(9) -#define CTRL_TX_HFL_INT BIT(8) -#define CTRL_RX_HFL_INT BIT(7) -#define CTRL_TX_EMP_INT BIT(6) -#define CTRL_TX_RDY_INT BIT(5) -#define CTRL_RX_RDY_INT BIT(4) #define CTRL_BRK_DET_INT BIT(3) #define CTRL_FRM_ERR_INT BIT(2) #define CTRL_PAR_ERR_INT BIT(1) #define CTRL_OVR_ERR_INT BIT(0) -#define CTRL_RX_INT (CTRL_RX_RDY_INT | CTRL_BRK_DET_INT |\ - CTRL_FRM_ERR_INT | CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) +#define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \ + CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) -#define UART_STAT 0x0c +#define UART_STD_CTRL2 UART_STD_CTRL1 +#define CTRL_STD_TX_RDY_INT BIT(5) +#define CTRL_STD_RX_RDY_INT BIT(4) + +#define UART_STAT 0x0C #define STAT_TX_FIFO_EMP BIT(13) -#define STAT_RX_FIFO_EMP BIT(12) #define STAT_TX_FIFO_FUL BIT(11) -#define STAT_TX_FIFO_HFL BIT(10) -#define STAT_RX_TOGL BIT(9) -#define STAT_RX_FIFO_FUL BIT(8) -#define STAT_RX_FIFO_HFL BIT(7) #define STAT_TX_EMP BIT(6) -#define STAT_TX_RDY BIT(5) -#define STAT_RX_RDY BIT(4) +#define STAT_STD_TX_RDY BIT(5) +#define STAT_STD_RX_RDY BIT(4) #define STAT_BRK_DET BIT(3) #define STAT_FRM_ERR BIT(2) #define STAT_PAR_ERR BIT(1) @@ -92,13 +78,55 @@ #define MVEBU_UART_TYPE "mvebu-uart" #define DRIVER_NAME "mvebu_serial" -static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; +/* Register offsets, different depending on the UART */ +struct uart_regs_layout { + unsigned int rbr; + unsigned int tsh; + unsigned int ctrl; + unsigned int intr; +}; + +/* Diverging flags */ +struct uart_flags { + unsigned int ctrl_tx_rdy_int; + unsigned int ctrl_rx_rdy_int; + unsigned int stat_tx_rdy; + unsigned int stat_rx_rdy; +}; + +/* Driver data, a structure for each UART port */ +struct mvebu_uart_driver_data { + bool is_ext; + struct uart_regs_layout regs; + struct uart_flags flags; +}; -struct mvebu_uart_data { +/* MVEBU UART driver structure */ +struct mvebu_uart { struct uart_port *port; - struct clk *clk; + struct clk *clk; + struct mvebu_uart_driver_data *data; }; +static struct mvebu_uart *to_mvuart(struct uart_port *port) +{ + return (struct mvebu_uart *)port->private_data; +} + +#define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext) + +#define UART_RBR(port) (to_mvuart(port)->data->regs.rbr) +#define UART_TSH(port) (to_mvuart(port)->data->regs.tsh) +#define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl) +#define UART_INTR(port) (to_mvuart(port)->data->regs.intr) + +#define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int) +#define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int) +#define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy) +#define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy) + +static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; + /* Core UART Driver Operations */ static unsigned int mvebu_uart_tx_empty(struct uart_port *port) { @@ -128,26 +156,31 @@ static void mvebu_uart_set_mctrl(struct uart_port *port, static void mvebu_uart_stop_tx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_CTRL); + unsigned int ctl = readl(port->membase + UART_INTR(port)); - ctl &= ~CTRL_TX_RDY_INT; - writel(ctl, port->membase + UART_CTRL); + ctl &= ~CTRL_TX_RDY_INT(port); + writel(ctl, port->membase + UART_INTR(port)); } static void mvebu_uart_start_tx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_CTRL); + unsigned int ctl = readl(port->membase + UART_INTR(port)); - ctl |= CTRL_TX_RDY_INT; - writel(ctl, port->membase + UART_CTRL); + ctl |= CTRL_TX_RDY_INT(port); + writel(ctl, port->membase + UART_INTR(port)); } static void mvebu_uart_stop_rx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_CTRL); + unsigned int ctl; - ctl &= ~CTRL_RX_INT; - writel(ctl, port->membase + UART_CTRL); + ctl = readl(port->membase + UART_CTRL(port)); + ctl &= ~CTRL_BRK_INT; + writel(ctl, port->membase + UART_CTRL(port)); + + ctl = readl(port->membase + UART_INTR(port)); + ctl &= ~CTRL_RX_RDY_INT(port); + writel(ctl, port->membase + UART_INTR(port)); } static void mvebu_uart_break_ctl(struct uart_port *port, int brk) @@ -156,12 +189,12 @@ static void mvebu_uart_break_ctl(struct uart_port *port, int brk) unsigned long flags; spin_lock_irqsave(&port->lock, flags); - ctl = readl(port->membase + UART_CTRL); + ctl = readl(port->membase + UART_CTRL(port)); if (brk == -1) ctl |= CTRL_SND_BRK_SEQ; else ctl &= ~CTRL_SND_BRK_SEQ; - writel(ctl, port->membase + UART_CTRL); + writel(ctl, port->membase + UART_CTRL(port)); spin_unlock_irqrestore(&port->lock, flags); } @@ -172,8 +205,8 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) char flag = 0; do { - if (status & STAT_RX_RDY) { - ch = readl(port->membase + UART_RBR); + if (status & STAT_RX_RDY(port)) { + ch = readl(port->membase + UART_RBR(port)); ch &= 0xff; flag = TTY_NORMAL; port->icount.rx++; @@ -199,7 +232,7 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) goto ignore_char; if (status & port->ignore_status_mask & STAT_PAR_ERR) - status &= ~STAT_RX_RDY; + status &= ~STAT_RX_RDY(port); status &= port->read_status_mask; @@ -208,7 +241,7 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) status &= ~port->ignore_status_mask; - if (status & STAT_RX_RDY) + if (status & STAT_RX_RDY(port)) tty_insert_flip_char(tport, ch, flag); if (status & STAT_BRK_DET) @@ -222,7 +255,7 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) ignore_char: status = readl(port->membase + UART_STAT); - } while (status & (STAT_RX_RDY | STAT_BRK_DET)); + } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET)); tty_flip_buffer_push(tport); } @@ -234,7 +267,7 @@ static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) unsigned int st; if (port->x_char) { - writel(port->x_char, port->membase + UART_TSH); + writel(port->x_char, port->membase + UART_TSH(port)); port->icount.tx++; port->x_char = 0; return; @@ -246,7 +279,7 @@ static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) } for (count = 0; count < port->fifosize; count++) { - writel(xmit->buf[xmit->tail], port->membase + UART_TSH); + writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; @@ -270,10 +303,11 @@ static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) struct uart_port *port = (struct uart_port *)dev_id; unsigned int st = readl(port->membase + UART_STAT); - if (st & (STAT_RX_RDY | STAT_OVR_ERR | STAT_FRM_ERR | STAT_BRK_DET)) + if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | + STAT_BRK_DET)) mvebu_uart_rx_chars(port, st); - if (st & STAT_TX_RDY) + if (st & STAT_TX_RDY(port)) mvebu_uart_tx_chars(port, st); return IRQ_HANDLED; @@ -281,12 +315,17 @@ static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) static int mvebu_uart_startup(struct uart_port *port) { + unsigned int ctl; int ret; writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, - port->membase + UART_CTRL); + port->membase + UART_CTRL(port)); udelay(1); - writel(CTRL_RX_INT, port->membase + UART_CTRL); + writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); + + ctl = readl(port->membase + UART_INTR(port)); + ctl |= CTRL_RX_RDY_INT(port); + writel(ctl, port->membase + UART_INTR(port)); ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, DRIVER_NAME, port); @@ -300,7 +339,7 @@ static int mvebu_uart_startup(struct uart_port *port) static void mvebu_uart_shutdown(struct uart_port *port) { - writel(0, port->membase + UART_CTRL); + writel(0, port->membase + UART_INTR(port)); free_irq(port->irq, port); } @@ -314,8 +353,8 @@ static void mvebu_uart_set_termios(struct uart_port *port, spin_lock_irqsave(&port->lock, flags); - port->read_status_mask = STAT_RX_RDY | STAT_OVR_ERR | - STAT_TX_RDY | STAT_TX_FIFO_FUL; + port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | + STAT_TX_RDY(port) | STAT_TX_FIFO_FUL; if (termios->c_iflag & INPCK) port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; @@ -326,7 +365,7 @@ static void mvebu_uart_set_termios(struct uart_port *port, STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR; if ((termios->c_cflag & CREAD) == 0) - port->ignore_status_mask |= STAT_RX_RDY | STAT_BRK_ERR; + port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; if (old) tty_termios_copy_hw(termios, old); @@ -357,10 +396,10 @@ static int mvebu_uart_get_poll_char(struct uart_port *port) { unsigned int st = readl(port->membase + UART_STAT); - if (!(st & STAT_RX_RDY)) + if (!(st & STAT_RX_RDY(port))) return NO_POLL_CHAR; - return readl(port->membase + UART_RBR); + return readl(port->membase + UART_RBR(port)); } static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) @@ -376,7 +415,7 @@ static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) udelay(1); } - writel(c, port->membase + UART_TSH); + writel(c, port->membase + UART_TSH(port)); } #endif @@ -414,7 +453,8 @@ static void mvebu_uart_putc(struct uart_port *port, int c) break; } - writel(c, port->membase + UART_TSH); + /* At early stage, DT is not parsed yet, only use UART0 */ + writel(c, port->membase + UART_STD_TSH); for (;;) { st = readl(port->membase + UART_STAT); @@ -459,7 +499,7 @@ static void wait_for_xmitr(struct uart_port *port) static void mvebu_uart_console_putchar(struct uart_port *port, int ch) { wait_for_xmitr(port); - writel(ch, port->membase + UART_TSH); + writel(ch, port->membase + UART_TSH(port)); } static void mvebu_uart_console_write(struct console *co, const char *s, @@ -467,7 +507,7 @@ static void mvebu_uart_console_write(struct console *co, const char *s, { struct uart_port *port = &mvebu_uart_ports[co->index]; unsigned long flags; - unsigned int ier; + unsigned int ier, intr, ctl; int locked = 1; if (oops_in_progress) @@ -475,16 +515,23 @@ static void mvebu_uart_console_write(struct console *co, const char *s, else spin_lock_irqsave(&port->lock, flags); - ier = readl(port->membase + UART_CTRL) & - (CTRL_RX_INT | CTRL_TX_RDY_INT); - writel(0, port->membase + UART_CTRL); + ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; + intr = readl(port->membase + UART_INTR(port)) & + (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port)); + writel(0, port->membase + UART_CTRL(port)); + writel(0, port->membase + UART_INTR(port)); uart_console_write(port, s, count, mvebu_uart_console_putchar); wait_for_xmitr(port); if (ier) - writel(ier, port->membase + UART_CTRL); + writel(ier, port->membase + UART_CTRL(port)); + + if (intr) { + ctl = intr | readl(port->membase + UART_INTR(port)); + writel(ctl, port->membase + UART_INTR(port)); + } if (locked) spin_unlock_irqrestore(&port->lock, flags); @@ -547,12 +594,16 @@ static struct uart_driver mvebu_uart_driver = { #endif }; +static const struct of_device_id mvebu_uart_of_match[]; + static int mvebu_uart_probe(struct platform_device *pdev) { struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + const struct of_device_id *match = of_match_device(mvebu_uart_of_match, + &pdev->dev); struct uart_port *port; - struct mvebu_uart_data *data; + struct mvebu_uart *mvuart; int ret; if (!reg || !irq) { @@ -591,15 +642,16 @@ static int mvebu_uart_probe(struct platform_device *pdev) if (IS_ERR(port->membase)) return -PTR_ERR(port->membase); - data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data), - GFP_KERNEL); - if (!data) + mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), + GFP_KERNEL); + if (!mvuart) return -ENOMEM; - data->port = port; + mvuart->data = (struct mvebu_uart_driver_data *)match->data; + mvuart->port = port; - port->private_data = data; - platform_set_drvdata(pdev, data); + port->private_data = mvuart; + platform_set_drvdata(pdev, mvuart); ret = uart_add_one_port(&mvebu_uart_driver, port); if (ret) @@ -607,9 +659,24 @@ static int mvebu_uart_probe(struct platform_device *pdev) return 0; } +static struct mvebu_uart_driver_data uart_std_driver_data = { + .is_ext = false, + .regs.rbr = UART_STD_RBR, + .regs.tsh = UART_STD_TSH, + .regs.ctrl = UART_STD_CTRL1, + .regs.intr = UART_STD_CTRL2, + .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT, + .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT, + .flags.stat_tx_rdy = STAT_STD_TX_RDY, + .flags.stat_rx_rdy = STAT_STD_RX_RDY, +}; + /* Match table for of_platform binding */ static const struct of_device_id mvebu_uart_of_match[] = { - { .compatible = "marvell,armada-3700-uart", }, + { + .compatible = "marvell,armada-3700-uart", + .data = (void *)&uart_std_driver_data, + }, {} }; From patchwork Fri Oct 6 10:13:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqJ4PPqz9t5C for ; Fri, 6 Oct 2017 21:14:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751917AbdJFKOO (ORCPT ); Fri, 6 Oct 2017 06:14:14 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50807 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751620AbdJFKOL (ORCPT ); Fri, 6 Oct 2017 06:14:11 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 20F29209B1; Fri, 6 Oct 2017 12:14:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id A86D2209A2; Fri, 6 Oct 2017 12:14:08 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Allen Yan , Miquel Raynal Subject: [PATCH 06/16] serial: mvebu-uart: add soft reset at probe Date: Fri, 6 Oct 2017 12:13:34 +0200 Message-Id: <20171006101344.15590-7-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Allen Yan The existing UART driver relies on the bootloader to initialize the port(s). However, the secondary uart port may not be initialized properly in early boot stage. This patch adds the UART soft reset when probing, for all ports. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 82438884af1e..da756cfec0bb 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -653,6 +653,11 @@ static int mvebu_uart_probe(struct platform_device *pdev) port->private_data = mvuart; platform_set_drvdata(pdev, mvuart); + /* UART Soft Reset*/ + writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); + udelay(1); + writel(0, port->membase + UART_CTRL(port)); + ret = uart_add_one_port(&mvebu_uart_driver, port); if (ret) return ret; From patchwork Fri Oct 6 10:13:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822328 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqp6PJLz9t4R for ; Fri, 6 Oct 2017 21:14:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751985AbdJFKOm (ORCPT ); Fri, 6 Oct 2017 06:14:42 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50840 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751717AbdJFKON (ORCPT ); Fri, 6 Oct 2017 06:14:13 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id C36FC209B5; Fri, 6 Oct 2017 12:14:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 4F0FE209B0; Fri, 6 Oct 2017 12:14:10 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Allen Yan , Miquel Raynal Subject: [PATCH 07/16] serial: mvebu-uart: add function to change baudrate Date: Fri, 6 Oct 2017 12:13:35 +0200 Message-Id: <20171006101344.15590-8-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Allen Yan Until now, the first UART port baudrate was set by the bootloader. Add a function allowing to change the baudrate. Changes may be done from userspace but also at probe time by the kernel. Use the simplest method: baudrate divisor. Works for all UART ports until 230400 baud. To achieve higher baudrates, software should implement the fractional divisor feature that allows more accuracy for higher rates. Signed-off-by: Allen Yan [: changed termios handling] Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 69 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index da756cfec0bb..81a3d2714fd3 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -72,6 +72,7 @@ | STAT_PAR_ERR | STAT_OVR_ERR) #define UART_BRDV 0x10 +#define BRDV_BAUD_MASK 0x3FF #define MVEBU_NR_UARTS 1 @@ -344,6 +345,31 @@ static void mvebu_uart_shutdown(struct uart_port *port) free_irq(port->irq, port); } +static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) +{ + struct mvebu_uart *mvuart = to_mvuart(port); + unsigned int baud_rate_div; + u32 brdv; + + if (IS_ERR(mvuart->clk)) + return -PTR_ERR(mvuart->clk); + + /* + * The UART clock is divided by the value of the divisor to generate + * UCLK_OUT clock, which is 16 times faster than the baudrate. + * This prescaler can achieve all standard baudrates until 230400. + * Higher baudrates could be achieved for the extended UART by using the + * programmable oversampling stack (also called fractional divisor). + */ + baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16); + brdv = readl(port->membase + UART_BRDV); + brdv &= ~BRDV_BAUD_MASK; + brdv |= baud_rate_div; + writel(brdv, port->membase + UART_BRDV); + + return 0; +} + static void mvebu_uart_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) @@ -367,11 +393,30 @@ static void mvebu_uart_set_termios(struct uart_port *port, if ((termios->c_cflag & CREAD) == 0) port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; - if (old) - tty_termios_copy_hw(termios, old); + /* + * Maximum achievable frequency with simple baudrate divisor is 230400. + * Since the error per bit frame would be of more than 15%, achieving + * higher frequencies would require to implement the fractional divisor + * feature. + */ + baud = uart_get_baud_rate(port, termios, old, 0, 230400); + if (mvebu_uart_baud_rate_set(port, baud)) { + /* No clock available, baudrate cannot be changed */ + if (old) + baud = uart_get_baud_rate(port, old, NULL, 0, 230400); + } else { + tty_termios_encode_baud_rate(termios, baud, baud); + uart_update_timeout(port, termios->c_cflag, baud); + } - baud = uart_get_baud_rate(port, termios, old, 0, 460800); - uart_update_timeout(port, termios->c_cflag, baud); + /* Only the following flag changes are supported */ + if (old) { + termios->c_iflag &= INPCK | IGNPAR; + termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); + termios->c_cflag &= CREAD | CBAUD; + termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); + termios->c_lflag = old->c_lflag; + } spin_unlock_irqrestore(&port->lock, flags); } @@ -647,12 +692,28 @@ static int mvebu_uart_probe(struct platform_device *pdev) if (!mvuart) return -ENOMEM; + /* Get controller data depending on the compatible string */ mvuart->data = (struct mvebu_uart_driver_data *)match->data; mvuart->port = port; port->private_data = mvuart; platform_set_drvdata(pdev, mvuart); + /* Get fixed clock frequency */ + mvuart->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(mvuart->clk)) { + if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) + return PTR_ERR(mvuart->clk); + + if (IS_EXTENDED(port)) { + dev_err(&pdev->dev, "unable to get UART clock\n"); + return PTR_ERR(mvuart->clk); + } + } else { + if (!clk_prepare_enable(mvuart->clk)) + port->uartclk = clk_get_rate(mvuart->clk); + } + /* UART Soft Reset*/ writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); udelay(1); From patchwork Fri Oct 6 10:13:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqc5dK1z9t4R for ; Fri, 6 Oct 2017 21:14:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751931AbdJFKOV (ORCPT ); Fri, 6 Oct 2017 06:14:21 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50819 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751913AbdJFKOO (ORCPT ); Fri, 6 Oct 2017 06:14:14 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id D6B13209BA; Fri, 6 Oct 2017 12:14:11 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 6A6B3209B0; Fri, 6 Oct 2017 12:14:11 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Allen Yan , Miquel Raynal Subject: [PATCH 08/16] serial: mvebu-uart: clear state register before IRQ request Date: Fri, 6 Oct 2017 12:13:36 +0200 Message-Id: <20171006101344.15590-9-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Allen Yan When receiving data on RX pin before ->uart_startup() is called, some error bits in the state register could be set up (like BRK_DET). This is harmless when using only the standard UART (error bits are read-only), but may procude an endless loop once in the extended UART RX interrupt handler (error bits must be cleared). Clear the status register in ->uart_startup() to avoid this situation. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 81a3d2714fd3..67f302748b78 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -322,6 +322,12 @@ static int mvebu_uart_startup(struct uart_port *port) writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, port->membase + UART_CTRL(port)); udelay(1); + + /* Clear the error bits of state register before IRQ request */ + ret = readl(port->membase + UART_STAT); + ret |= STAT_BRK_ERR; + writel(ret, port->membase + UART_STAT); + writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); ctl = readl(port->membase + UART_INTR(port)); From patchwork Fri Oct 6 10:13:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqc1Bjxz9t48 for ; Fri, 6 Oct 2017 21:14:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751827AbdJFKOT (ORCPT ); Fri, 6 Oct 2017 06:14:19 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50807 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751931AbdJFKOO (ORCPT ); Fri, 6 Oct 2017 06:14:14 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id BA2DF209A2; Fri, 6 Oct 2017 12:14:12 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 4B6B4209B0; Fri, 6 Oct 2017 12:14:12 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Allen Yan , Miquel Raynal Subject: [PATCH 09/16] serial: mvebu-uart: add TX interrupt trigger for pulse interrupts Date: Fri, 6 Oct 2017 12:13:37 +0200 Message-Id: <20171006101344.15590-10-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Allen Yan Pulse interrupts (extended UART only) needs a change of state to trigger the TX interrupt. In addition to enabling the TX_READY_INT_EN flag, produce a FIFO state change from 'empty' to 'not full'. For this, write only one data byte in TX start, making the TX FIFO not empty, and wait for the TX interrupt to continue the transfer. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 67f302748b78..46d10209637a 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -165,8 +165,16 @@ static void mvebu_uart_stop_tx(struct uart_port *port) static void mvebu_uart_start_tx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_INTR(port)); + unsigned int ctl; + struct circ_buf *xmit = &port->state->xmit; + if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { + writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + ctl = readl(port->membase + UART_INTR(port)); ctl |= CTRL_TX_RDY_INT(port); writel(ctl, port->membase + UART_INTR(port)); } From patchwork Fri Oct 6 10:13:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqj62lNz9t4R for ; Fri, 6 Oct 2017 21:14:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751945AbdJFKOT (ORCPT ); Fri, 6 Oct 2017 06:14:19 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50862 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751907AbdJFKOQ (ORCPT ); Fri, 6 Oct 2017 06:14:16 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id B0102209B3; Fri, 6 Oct 2017 12:14:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 3FB3120909; Fri, 6 Oct 2017 12:14:13 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 10/16] serial: mvebu-uart: dissociate RX and TX interrupts Date: Fri, 6 Oct 2017 12:13:38 +0200 Message-Id: <20171006101344.15590-11-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org While the standard UART port can use a single IRQ that 'sums' both RX and TX interrupts, the extended port cannot and has to use two different ISR, one for each direction. The standard port also has the hability to use two separate interrupts (one for each direction). The logic is then: either there is only one unnamed interrupt on the standard port and this interrupt must be used for both directions (this is legacy bindings); or all the interrupts must be described and named 'uart-sum' (if available), 'uart-rx', 'uart-tx' and two separate handlers for each direction will be used. Suggested-by: Allen Yan Signed-off-by: Miquel Raynal --- drivers/tty/serial/mvebu-uart.c | 129 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 118 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 46d10209637a..b52cbe8c0558 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -79,7 +79,16 @@ #define MVEBU_UART_TYPE "mvebu-uart" #define DRIVER_NAME "mvebu_serial" -/* Register offsets, different depending on the UART */ +enum { + /* Either there is only one summed IRQ... */ + UART_IRQ_SUM = 0, + /* ...or there are two separate IRQ for RX and TX */ + UART_RX_IRQ = 0, + UART_TX_IRQ, + UART_IRQ_COUNT +}; + +/* Diverging register offsets */ struct uart_regs_layout { unsigned int rbr; unsigned int tsh; @@ -106,6 +115,8 @@ struct mvebu_uart_driver_data { struct mvebu_uart { struct uart_port *port; struct clk *clk; + int irq[UART_IRQ_COUNT]; + unsigned char __iomem *nb; struct mvebu_uart_driver_data *data; }; @@ -313,9 +324,32 @@ static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) unsigned int st = readl(port->membase + UART_STAT); if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | + STAT_BRK_DET)) + mvebu_uart_rx_chars(port, st); + + if (st & STAT_TX_RDY(port)) + mvebu_uart_tx_chars(port, st); + + return IRQ_HANDLED; +} + +static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id) +{ + struct uart_port *port = (struct uart_port *)dev_id; + unsigned int st = readl(port->membase + UART_STAT); + + if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | STAT_BRK_DET)) mvebu_uart_rx_chars(port, st); + return IRQ_HANDLED; +} + +static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id) +{ + struct uart_port *port = (struct uart_port *)dev_id; + unsigned int st = readl(port->membase + UART_STAT); + if (st & STAT_TX_RDY(port)) mvebu_uart_tx_chars(port, st); @@ -324,6 +358,7 @@ static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) static int mvebu_uart_startup(struct uart_port *port) { + struct mvebu_uart *mvuart = to_mvuart(port); unsigned int ctl; int ret; @@ -342,11 +377,37 @@ static int mvebu_uart_startup(struct uart_port *port) ctl |= CTRL_RX_RDY_INT(port); writel(ctl, port->membase + UART_INTR(port)); - ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, - DRIVER_NAME, port); - if (ret) { - dev_err(port->dev, "failed to request irq\n"); - return ret; + if (!mvuart->irq[UART_TX_IRQ]) { + /* Old bindings with just one interrupt (UART0 only) */ + ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], + mvebu_uart_isr, port->irqflags, + dev_name(port->dev), port); + if (ret) { + dev_err(port->dev, "unable to request IRQ %d\n", + mvuart->irq[UART_IRQ_SUM]); + return ret; + } + } else { + /* New bindings with an IRQ for RX and TX (both UART) */ + ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], + mvebu_uart_rx_isr, port->irqflags, + dev_name(port->dev), port); + if (ret) { + dev_err(port->dev, "unable to request IRQ %d\n", + mvuart->irq[UART_RX_IRQ]); + return ret; + } + + ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], + mvebu_uart_tx_isr, port->irqflags, + dev_name(port->dev), + port); + if (ret) { + dev_err(port->dev, "unable to request IRQ %d\n", + mvuart->irq[UART_TX_IRQ]); + free_irq(mvuart->irq[UART_RX_IRQ], port); + return ret; + } } return 0; @@ -354,9 +415,16 @@ static int mvebu_uart_startup(struct uart_port *port) static void mvebu_uart_shutdown(struct uart_port *port) { + struct mvebu_uart *mvuart = to_mvuart(port); + writel(0, port->membase + UART_INTR(port)); - free_irq(port->irq, port); + if (!mvuart->irq[UART_TX_IRQ]) { + free_irq(mvuart->irq[UART_IRQ_SUM], port); + } else { + free_irq(mvuart->irq[UART_RX_IRQ], port); + free_irq(mvuart->irq[UART_TX_IRQ], port); + } } static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) @@ -658,15 +726,15 @@ static const struct of_device_id mvebu_uart_of_match[]; static int mvebu_uart_probe(struct platform_device *pdev) { struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); - struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); const struct of_device_id *match = of_match_device(mvebu_uart_of_match, &pdev->dev); struct uart_port *port; struct mvebu_uart *mvuart; + int irq; int ret; - if (!reg || !irq) { - dev_err(&pdev->dev, "no registers/irq defined\n"); + if (!reg) { + dev_err(&pdev->dev, "no registers defined\n"); return -EINVAL; } @@ -693,7 +761,12 @@ static int mvebu_uart_probe(struct platform_device *pdev) port->flags = UPF_FIXED_PORT; port->line = pdev->id; - port->irq = irq->start; + /* + * IRQ number is not stored in this structure because we may have two of + * them per port (RX and TX). Instead, use the driver UART structure + * array so called ->irq[]. + */ + port->irq = 0; port->irqflags = 0; port->mapbase = reg->start; @@ -728,6 +801,40 @@ static int mvebu_uart_probe(struct platform_device *pdev) port->uartclk = clk_get_rate(mvuart->clk); } + /* Manage interrupts */ + memset(mvuart->irq, 0, UART_IRQ_COUNT); + if (platform_irq_count(pdev) == 1) { + /* Old bindings: no name on the single unamed UART0 IRQ */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "unable to get UART IRQ\n"); + return irq; + } + + mvuart->irq[UART_IRQ_SUM] = irq; + } else { + /* + * New bindings: named interrupts (RX, TX) for both UARTS, + * only make use of uart-rx and uart-tx interrupts, do not use + * uart-sum of UART0 port. + */ + irq = platform_get_irq_byname(pdev, "uart-rx"); + if (irq < 0) { + dev_err(&pdev->dev, "unable to get 'uart-rx' IRQ\n"); + return irq; + } + + mvuart->irq[UART_RX_IRQ] = irq; + + irq = platform_get_irq_byname(pdev, "uart-tx"); + if (irq < 0) { + dev_err(&pdev->dev, "unable to get 'uart-tx' IRQ\n"); + return irq; + } + + mvuart->irq[UART_TX_IRQ] = irq; + } + /* UART Soft Reset*/ writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); udelay(1); From patchwork Fri Oct 6 10:13:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqN5Y9Jz9t48 for ; Fri, 6 Oct 2017 21:14:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751962AbdJFKOX (ORCPT ); Fri, 6 Oct 2017 06:14:23 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50840 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751888AbdJFKOQ (ORCPT ); Fri, 6 Oct 2017 06:14:16 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 947B4209C0; Fri, 6 Oct 2017 12:14:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 2649820909; Fri, 6 Oct 2017 12:14:14 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 11/16] serial: mvebu-uart: augment the maximum number of ports Date: Fri, 6 Oct 2017 12:13:39 +0200 Message-Id: <20171006101344.15590-12-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org A3700 boards may have up to two UART ports. Set the new limit to two maximum UART ports. Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index b52cbe8c0558..3e46affa09a8 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -74,7 +74,7 @@ #define UART_BRDV 0x10 #define BRDV_BAUD_MASK 0x3FF -#define MVEBU_NR_UARTS 1 +#define MVEBU_NR_UARTS 2 #define MVEBU_UART_TYPE "mvebu-uart" #define DRIVER_NAME "mvebu_serial" From patchwork Fri Oct 6 10:13:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqP4xSNz9t4R for ; Fri, 6 Oct 2017 21:14:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751966AbdJFKOX (ORCPT ); Fri, 6 Oct 2017 06:14:23 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50819 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935AbdJFKOR (ORCPT ); Fri, 6 Oct 2017 06:14:17 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 7F5AB209C1; Fri, 6 Oct 2017 12:14:15 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1826520909; Fri, 6 Oct 2017 12:14:15 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 12/16] serial: mvebu-uart: support extended port registers layout Date: Fri, 6 Oct 2017 12:13:40 +0200 Message-Id: <20171006101344.15590-13-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Define the missing register offsets and bit fields for the extended UART port. Add a second driver data structure filled with its port data, selected with the right compatible (marvell,armada-3700-uart-ext). Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT --- drivers/tty/serial/mvebu-uart.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 3e46affa09a8..38b067e0ef0c 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -39,10 +39,13 @@ /* Register Map */ #define UART_STD_RBR 0x00 +#define UART_EXT_RBR 0x18 #define UART_STD_TSH 0x04 +#define UART_EXT_TSH 0x1C #define UART_STD_CTRL1 0x08 +#define UART_EXT_CTRL1 0x04 #define CTRL_SOFT_RST BIT(31) #define CTRL_TXFIFO_RST BIT(15) #define CTRL_RXFIFO_RST BIT(14) @@ -55,15 +58,20 @@ CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) #define UART_STD_CTRL2 UART_STD_CTRL1 +#define UART_EXT_CTRL2 0x20 #define CTRL_STD_TX_RDY_INT BIT(5) +#define CTRL_EXT_TX_RDY_INT BIT(6) #define CTRL_STD_RX_RDY_INT BIT(4) +#define CTRL_EXT_RX_RDY_INT BIT(5) #define UART_STAT 0x0C #define STAT_TX_FIFO_EMP BIT(13) #define STAT_TX_FIFO_FUL BIT(11) #define STAT_TX_EMP BIT(6) #define STAT_STD_TX_RDY BIT(5) +#define STAT_EXT_TX_RDY BIT(15) #define STAT_STD_RX_RDY BIT(4) +#define STAT_EXT_RX_RDY BIT(14) #define STAT_BRK_DET BIT(3) #define STAT_FRM_ERR BIT(2) #define STAT_PAR_ERR BIT(1) @@ -858,12 +866,28 @@ static struct mvebu_uart_driver_data uart_std_driver_data = { .flags.stat_rx_rdy = STAT_STD_RX_RDY, }; +static struct mvebu_uart_driver_data uart_ext_driver_data = { + .is_ext = true, + .regs.rbr = UART_EXT_RBR, + .regs.tsh = UART_EXT_TSH, + .regs.ctrl = UART_EXT_CTRL1, + .regs.intr = UART_EXT_CTRL2, + .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT, + .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT, + .flags.stat_tx_rdy = STAT_EXT_TX_RDY, + .flags.stat_rx_rdy = STAT_EXT_RX_RDY, +}; + /* Match table for of_platform binding */ static const struct of_device_id mvebu_uart_of_match[] = { { .compatible = "marvell,armada-3700-uart", .data = (void *)&uart_std_driver_data, }, + { + .compatible = "marvell,armada-3700-uart-ext", + .data = (void *)&uart_ext_driver_data, + }, {} }; From patchwork Fri Oct 6 10:13:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqb37lrz9t63 for ; Fri, 6 Oct 2017 21:14:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751830AbdJFKOd (ORCPT ); Fri, 6 Oct 2017 06:14:33 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50893 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751913AbdJFKOW (ORCPT ); Fri, 6 Oct 2017 06:14:22 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id E8A402098F; Fri, 6 Oct 2017 12:14:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 66C7B209B4; Fri, 6 Oct 2017 12:14:19 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 13/16] arm64: dts: marvell: armada-37xx: add UART clock Date: Fri, 6 Oct 2017 12:13:41 +0200 Message-Id: <20171006101344.15590-14-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the missing clock property to armada-3700 UART node. This clock will be used to derive the prescaler value to comply to the requested baudrate. Signed-off-by: Miquel Raynal Acked-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index b554cdaf5e53..a36d667f770e 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -135,6 +135,7 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x200>; + clocks = <&xtalclk>; interrupts = ; status = "disabled"; }; From patchwork Fri Oct 6 10:13:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqQ24xDz9t5C for ; Fri, 6 Oct 2017 21:14:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751969AbdJFKOZ (ORCPT ); Fri, 6 Oct 2017 06:14:25 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50913 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751958AbdJFKOX (ORCPT ); Fri, 6 Oct 2017 06:14:23 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id CA7DE209C3; Fri, 6 Oct 2017 12:14:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 6658020909; Fri, 6 Oct 2017 12:14:20 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 14/16] arm64: dts: marvell: armada-37xx: add second UART port Date: Fri, 6 Oct 2017 12:13:42 +0200 Message-Id: <20171006101344.15590-15-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a node in Armada 37xx DTSI file for the second UART, with a different compatible due to its extended IP which has some differences with the first UART already in place. Make use of this commit to also fully describe the first port and use the same clear and named interrupt bindings for both ports. The standard UART (UART0) uses level-interrupts while the extended UART (UART1) uses edge-triggered interrupts. Signed-off-by: Miquel Raynal Acked-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index a36d667f770e..72b68f23c001 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; + serial1 = &uart1; }; cpus { @@ -136,7 +137,22 @@ compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x200>; clocks = <&xtalclk>; - interrupts = ; + interrupts = + , + , + ; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + status = "disabled"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&xtalclk>; + interrupts = + , + ; + interrupt-names = "uart-tx", "uart-rx"; status = "disabled"; }; From patchwork Fri Oct 6 10:13:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqX3X2jz9t48 for ; Fri, 6 Oct 2017 21:14:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751971AbdJFKO2 (ORCPT ); Fri, 6 Oct 2017 06:14:28 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50922 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751888AbdJFKOY (ORCPT ); Fri, 6 Oct 2017 06:14:24 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id C8FC3209C4; Fri, 6 Oct 2017 12:14:21 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 66479209B0; Fri, 6 Oct 2017 12:14:21 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 15/16] arm64: dts: marvell: armada-3720-db: enable second UART port Date: Fri, 6 Oct 2017 12:13:43 +0200 Message-Id: <20171006101344.15590-16-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Enable Armada-3720-DB second UART port by adding the corresponding device tree node in the board DTS and enabling it. Signed-off-by: Miquel Raynal Acked-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 9df0f06ce607..15713c19b3d0 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -216,7 +216,7 @@ /* * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through - * an FTDI + * an FTDI (also on CON24(V2.0)/CON26(V1.4)). */ &uart0 { pinctrl-names = "default"; @@ -224,6 +224,13 @@ status = "okay"; }; +/* CON26(V2.0)/CON28(V1.4) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + /* CON27(V2.0)/CON29(V1.4) */ &usb2 { status = "okay"; From patchwork Fri Oct 6 10:13:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 822320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7lqV2vJ9z9t48 for ; Fri, 6 Oct 2017 21:14:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751888AbdJFKO2 (ORCPT ); Fri, 6 Oct 2017 06:14:28 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:50937 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751958AbdJFKO0 (ORCPT ); Fri, 6 Oct 2017 06:14:26 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 5AACB209C5; Fri, 6 Oct 2017 12:14:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id E7D3E209A4; Fri, 6 Oct 2017 12:14:23 +0200 (CEST) From: Miquel Raynal To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Miquel Raynal Subject: [PATCH 16/16] arm64: dts: marvell: armada-3720-espressobin: fill UART nodes Date: Fri, 6 Oct 2017 12:13:44 +0200 Message-Id: <20171006101344.15590-17-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fill ESPRESSObin uart0 node with pinctrl information like in the Armada-3720-DB device tree (which uses the same node). Also explain how to enable the second UART port available on the headers. This second port is not enabled by default because both headers are dedicated to expose general purpose pins and remapping some of them to use the second UART would break existing users. Suggested-by: László ÁSHIN Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 2ce52ba74f73..c05b274ab1a9 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -98,9 +98,17 @@ /* Exported on the micro USB connector J5 through an FTDI */ &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; +/* + * Enabling the second UART on J17 (pins 24,26) is just a matter of copying the + * uart1 node from armada-3720-db.dts with one difference: it works with 1.8V + * TTL levels. + */ + /* J7 */ &usb3 { status = "okay";