From patchwork Thu Sep 27 04:48:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975535 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMn94f48z9s3Z for ; Thu, 27 Sep 2018 14:50:21 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMn93R7ZzF37m for ; Thu, 27 Sep 2018 14:50:21 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMm950MKzF32n for ; Thu, 27 Sep 2018 14:49:29 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRL028785; Wed, 26 Sep 2018 23:48:53 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:41 +1000 Message-Id: <20180927044849.28322-2-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 1/9] Add basic P9 fused core support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Ryan Grimm P9 cores can be configured into fused core mode where two core chiplets function as an 8-threaded, single core. So, bump four to eight in boot_entry when in fused core mode and cpu_thread_count in init_boot_cpu. The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet to load the copy for that core chiplet. So, send thread 1 of a fused core to init_shared_sprs in boot_entry. The code checks for fused core mode in the core thead state register and puts a field in struct cpu_thread. This flag is checked when updating the HID and in XIVE code when setting the special bar. For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the bits. It's fairly verbose but somewhat readable. This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours. Signed-off-by: Ryan Grimm Signed-off-by: Benjamin Herrenschmidt --- --- asm/head.S | 22 ++++++++++++++++++++-- core/chip.c | 15 +++++++++++---- core/cpu.c | 39 ++++++++++++++++++++++++++++++++++----- core/fast-reboot.c | 2 +- hw/xive.c | 2 +- include/chip.h | 31 +++++++++++++++++++++++++++++++ include/cpu.h | 6 ++++++ include/xscom.h | 3 +++ 8 files changed, 107 insertions(+), 13 deletions(-) diff --git a/asm/head.S b/asm/head.S index 803fbf1a..5aad6ca6 100644 --- a/asm/head.S +++ b/asm/head.S @@ -259,6 +259,7 @@ boot_offset: * r28 : PVR * r27 : DTB pointer (or NULL) * r26 : PIR thread mask + * r25 : P9 fused core flag */ .global boot_entry boot_entry: @@ -277,11 +278,19 @@ boot_entry: cmpwi cr0,%r3,PVR_TYPE_P8NVL beq 2f cmpwi cr0,%r3,PVR_TYPE_P9 - beq 1f + beq 3f attn /* Unsupported CPU type... what do we do ? */ b . /* loop here, just in case attn is disabled */ - /* P8 -> 8 threads */ + /* Check for fused core and set flag */ +3: + li %r3, 0x1e0 + mtspr SPR_SPRC, %r3 + mfspr %r3, SPR_SPRD + andi. %r25, %r3, 1 + beq 1f + + /* P8 or P9 fused -> 8 threads */ 2: li %r26,7 /* Get our reloc offset into r30 */ @@ -303,6 +312,15 @@ boot_entry: LOAD_IMM64(%r3, (MSR_HV | MSR_SF)) mtmsrd %r3,0 + /* If fused, t1 is primary chiplet and must init shared sprs */ + andi. %r3,%r25,1 + beq not_fused + + mfspr %r31,SPR_PIR + andi. %r3,%r31,1 + bnel init_shared_sprs + +not_fused: /* Check our PIR, avoid threads */ mfspr %r31,SPR_PIR and. %r0,%r31,%r26 diff --git a/core/chip.c b/core/chip.c index 65263253..2b9b6ef9 100644 --- a/core/chip.c +++ b/core/chip.c @@ -20,6 +20,7 @@ #include #include #include +#include static struct proc_chip *chips[MAX_CHIPS]; enum proc_chip_quirks proc_chip_quirks; @@ -37,7 +38,10 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { if (proc_gen == proc_gen_p9) - return P9_PIR2COREID(pir); + if (this_cpu()->is_fused_core) + return P9_PIRFUSED2NORMALCOREID(pir); + else + return P9_PIR2COREID(pir); else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else @@ -46,9 +50,12 @@ uint32_t pir_to_core_id(uint32_t pir) uint32_t pir_to_thread_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) - return P9_PIR2THREADID(pir); - else if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIR2FUSEDTHREADID(pir); + else + return P9_PIR2THREADID(pir); + } else if (proc_gen == proc_gen_p8) return P8_PIR2THREADID(pir); else return P7_PIR2THREADID(pir); diff --git a/core/cpu.c b/core/cpu.c index cc5b88c5..4b7bd059 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -893,6 +893,14 @@ void cpu_disable_all_threads(struct cpu_thread *cpu) /* XXX Do something to actually stop the core */ } +static int is_fused_core (void) +{ + unsigned int core_thread_state; + mtspr(SPR_SPRC, 0x00000000000001e0ULL); + core_thread_state = mfspr(SPR_SPRD); + return core_thread_state & PPC_BIT(63); +} + static void init_cpu_thread(struct cpu_thread *t, enum cpu_thread_state state, unsigned int pir) @@ -912,6 +920,7 @@ static void init_cpu_thread(struct cpu_thread *t, #ifdef STACK_CHECK_ENABLED t->stack_bot_mark = LONG_MAX; #endif + t->is_fused_core = is_fused_core(); assert(pir == container_of(t, struct cpu_stack, cpu) - cpu_stacks); } @@ -1004,14 +1013,16 @@ void init_boot_cpu(void) " (max %d threads/core)\n", cpu_thread_count); break; case proc_gen_p9: - cpu_thread_count = 4; + if (is_fused_core()) + cpu_thread_count = 8; + else + cpu_thread_count = 4; prlog(PR_INFO, "CPU: P9 generation processor" " (max %d threads/core)\n", cpu_thread_count); break; default: prerror("CPU: Unknown PVR, assuming 1 thread\n"); cpu_thread_count = 1; - cpu_max_pir = mfspr(SPR_PIR); } prlog(PR_DEBUG, "CPU: Boot CPU PIR is 0x%04x PVR is 0x%08x\n", @@ -1134,7 +1145,7 @@ void init_all_cpus(void) /* Iterate all CPUs in the device-tree */ dt_for_each_child(cpus, cpu) { - unsigned int pir, server_no, chip_id; + unsigned int pir, server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; struct cpu_thread *t, *pt; @@ -1162,6 +1173,14 @@ void init_all_cpus(void) prlog(PR_INFO, "CPU: CPU from DT PIR=0x%04x Server#=0x%x" " State=%d\n", pir, server_no, state); + /* Check max PIR */ + if (cpu_max_pir < (pir + cpu_thread_count - 1)) { + prlog(PR_WARNING, "CPU: CPU potentially out of range" + "PIR=0x%04x MAX=0x%04x !\n", + pir, cpu_max_pir); + continue; + } + /* Setup thread 0 */ assert(pir <= cpu_max_pir); t = pt = &cpu_stacks[pir].cpu; @@ -1187,11 +1206,21 @@ void init_all_cpus(void) /* Add the decrementer width property */ dt_add_property_cells(cpu, "ibm,dec-bits", dec_bits); + if (t->is_fused_core) + dt_add_property(t->node, "ibm,fused-core", NULL, 0); + /* Iterate threads */ p = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); if (!p) continue; - for (thread = 1; thread < (p->len / 4); thread++) { + threads = p->len / 4; + if (threads > cpu_thread_count) { + prlog(PR_WARNING, "CPU: Threads out of range for PIR 0x%04x" + " threads=%d max=%d\n", + pir, threads, cpu_thread_count); + threads = cpu_thread_count; + } + for (thread = 1; thread < threads; thread++) { prlog(PR_TRACE, "CPU: secondary thread %d found\n", thread); t = &cpu_stacks[pir + thread].cpu; @@ -1377,7 +1406,7 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req) assert(jobs); for_each_available_cpu(cpu) { - if (!cpu_is_thread0(cpu)) + if (!cpu_is_thread0(cpu) && !cpu_is_core_chiplet_primary(cpu)) continue; if (cpu == this_cpu()) continue; diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 8e95d834..f3fa42e2 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -206,7 +206,7 @@ static void cleanup_cpu_state(void) struct cpu_thread *cpu = this_cpu(); /* Per core cleanup */ - if (cpu_is_thread0(cpu)) { + if (cpu_is_thread0(cpu) | cpu_is_core_chiplet_primary(cpu)) { /* Shared SPRs whacked back to normal */ /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ diff --git a/hw/xive.c b/hw/xive.c index 515f154d..470cf5e3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3313,7 +3313,7 @@ static void xive_init_cpu(struct cpu_thread *c) * of a pair is present we just do the setup for each of them, which * is harmless. */ - if (cpu_is_thread0(c)) + if (cpu_is_thread0(c) || cpu_is_core_chiplet_primary(c)) xive_configure_ex_special_bar(x, c); /* Initialize the state structure */ diff --git a/include/chip.h b/include/chip.h index 2fb8126d..8eeea37e 100644 --- a/include/chip.h +++ b/include/chip.h @@ -91,6 +91,26 @@ * thus we have a 6-bit core number. * * Note: XIVE Only supports 4-bit chip numbers ... + * + * Upper PIR Bits + * -------------- + * + * Normal-Core Mode: + * 57:61 CoreID + * 62:62 ThreadID + * + * Fused-Core Mode: + * 57:59 FusedQuadID + * 60 FusedCoreID + * 61:63 FusedThreadID + * + * FusedCoreID 0 contains normal-core chiplet 0 and 1 + * FusedCoreID 1 contains normal-core chiplet 2 and 3 + * + * Fused cores have interleaved threads: + * core chiplet 0/2 = t0, t2, t4, t6 + * core chiplet 1/3 = t1, t3, t5, t7 + * */ #define P9_PIR2GCID(pir) (((pir) >> 8) & 0x7f) @@ -102,6 +122,17 @@ #define P9_GCID2CHIPID(gcid) ((gcid) & 0x7) +#define P9_PIR2FUSEDQUADID(pir) (((pir) >> 4) & 0x7) + +#define P9_PIR2FUSEDCOREID(pir) (((pir) >> 3) & 0x1) + +#define P9_PIR2FUSEDTHREADID(pir) ((pir) & 0x7) + +#define P9_PIRFUSED2NORMALCOREID(pir) \ + (P9_PIR2FUSEDQUADID(pir) << 2) | \ + (P9_PIR2FUSEDCOREID(pir) << 1) | \ + (P9_PIR2FUSEDTHREADID(pir) & 1) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) diff --git a/include/cpu.h b/include/cpu.h index 2fe47982..2fb5edd2 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -54,6 +54,7 @@ struct cpu_thread { uint32_t server_no; uint32_t chip_id; bool is_secondary; + bool is_fused_core; struct cpu_thread *primary; enum cpu_thread_state state; struct dt_node *node; @@ -260,6 +261,11 @@ static inline bool cpu_is_thread0(struct cpu_thread *cpu) return cpu->primary == cpu; } +static inline bool cpu_is_core_chiplet_primary(struct cpu_thread *cpu) +{ + return cpu->is_fused_core & (cpu_get_thread_index(cpu) == 1); +} + static inline bool cpu_is_sibling(struct cpu_thread *cpu1, struct cpu_thread *cpu2) { diff --git a/include/xscom.h b/include/xscom.h index 98532240..4e6ce92d 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -123,6 +123,9 @@ /* * Additional useful definitions for P9 + * + * Note: In all of these, the core numbering is the *small* core + * number. */ /* An EQ is a quad (also named an EP) */ From patchwork Thu Sep 27 04:48:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975531 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMm22VLnz9s3Z for ; Thu, 27 Sep 2018 14:49:22 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMm218c1zF32n for ; Thu, 27 Sep 2018 14:49:22 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMlv4lfdzF321 for ; Thu, 27 Sep 2018 14:49:15 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRM028785; Wed, 26 Sep 2018 23:48:56 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:42 +1000 Message-Id: <20180927044849.28322-3-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 2/9] hdat: Workaround HostBoot bug with fused core X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The TADA array is missing half of the secondary threads Signed-off-by: Benjamin Herrenschmidt --- hdata/pcia.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/hdata/pcia.c b/hdata/pcia.c index 9b210e4d..954c0491 100644 --- a/hdata/pcia.c +++ b/hdata/pcia.c @@ -103,7 +103,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus, const struct sppcia_core_unique *id, bool okay) { - const struct sppcia_cpu_thread *t; + const struct sppcia_cpu_thread *t, *t0; const struct sppcia_cpu_timebase *timebase; const struct sppcia_cpu_cache *cache; const struct sppcia_cpu_attr *attr; @@ -172,12 +172,27 @@ static struct dt_node *add_core_node(struct dt_node *cpus, /* Build ibm,ppc-interrupt-server#s with all threads */ for (i = 0; i < threads; i++) { t = find_tada(pcia, i); - if (!t) { - threads = i; - break; + if (i == 0) + t0 = t; + if (t) { + iserv[i] = t->pir; + } else { + if (i > 0 && i < cpu_thread_count) { + prerror("CORE[%i]: HDAT TADA bug for" + " thread %d, working around" + " using 0x%04x...\n", + pcia_index(pcia), i, t0->pir + i); + iserv[i] = t0->pir + i; + } else { + prerror("CORE[%i]: Failed to find TADA for" + " thread %d\n", + pcia_index(pcia), i); + threads = i; + break; + } } - - iserv[i] = t->pir; + printf("CORE[%i]: Thread %d PIR 0x%04x\n", + pcia_index(pcia), i, iserv[i]); } dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads); From patchwork Thu Sep 27 04:48:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LTyH5H5rz9s3Z for ; Thu, 27 Sep 2018 19:28:39 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LTyH2yVnzF377 for ; Thu, 27 Sep 2018 19:28:39 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LTvR2j43zF35X for ; Thu, 27 Sep 2018 19:26:10 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRN028785; Wed, 26 Sep 2018 23:48:58 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:43 +1000 Message-Id: <20180927044849.28322-4-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 3/9] xive: Set the fused core mode properly X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Set or clear the fused core mode bit in the XIVE inits properly. While HostBoot is supposed to do it, I prefer not depending on it doing the right thing, since we already configure that register ourselves anyway. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 4 ++++ include/xive.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 470cf5e3..f8e511c1 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1740,6 +1740,10 @@ static bool xive_config_init(struct xive *x) /* Disable pressure relief as we hijack the field in the VPs */ val &= ~PC_TCTXT_CFG_STORE_ACK; } + if (this_cpu()->is_fused_core) + val |= PC_TCTXT_CFG_FUSE_CORE_EN; + else + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive.h b/include/xive.h index acc696a4..f4365efc 100644 --- a/include/xive.h +++ b/include/xive.h @@ -86,6 +86,7 @@ #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) +#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) From patchwork Thu Sep 27 04:48:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMmM1S92z9sCK for ; Thu, 27 Sep 2018 14:49:39 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMmL6RSkzF342 for ; Thu, 27 Sep 2018 14:49:38 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMm15R7CzF324 for ; Thu, 27 Sep 2018 14:49:21 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRO028785; Wed, 26 Sep 2018 23:49:01 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:44 +1000 Message-Id: <20180927044849.28322-5-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 4/9] chip: Fix pir_to_thread_id for fused cores X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" pir_to_core_id() and pir_to_thread_id() are extensively used by the direct controls code and are expected to return the "normal" (non-fused, aka EC) core/thread IDs. Signed-off-by: Benjamin Herrenschmidt --- core/chip.c | 6 +++--- include/chip.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/core/chip.c b/core/chip.c index 2b9b6ef9..902327e1 100644 --- a/core/chip.c +++ b/core/chip.c @@ -37,12 +37,12 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) return P9_PIRFUSED2NORMALCOREID(pir); else return P9_PIR2COREID(pir); - else if (proc_gen == proc_gen_p8) + } else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else return P7_PIR2COREID(pir); @@ -52,7 +52,7 @@ uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) - return P9_PIR2FUSEDTHREADID(pir); + return P9_PIRFUSED2NORMALTHREADID(pir); else return P9_PIR2THREADID(pir); } else if (proc_gen == proc_gen_p8) diff --git a/include/chip.h b/include/chip.h index 8eeea37e..a9ab5560 100644 --- a/include/chip.h +++ b/include/chip.h @@ -133,6 +133,8 @@ (P9_PIR2FUSEDCOREID(pir) << 1) | \ (P9_PIR2FUSEDTHREADID(pir) & 1) +#define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) @@ -258,6 +260,11 @@ struct proc_chip { }; extern uint32_t pir_to_chip_id(uint32_t pir); + +/* + * Note: In P9 fused-core mode, these will return the "normal" + * core ID and thread ID (ie, thread ID 0..3) + */ extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir); From patchwork Thu Sep 27 04:48:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMnS6Bw6z9s3Z for ; Thu, 27 Sep 2018 14:50:36 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMnS41mfzF323 for ; Thu, 27 Sep 2018 14:50:36 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMmK48PPzF33f for ; Thu, 27 Sep 2018 14:49:37 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRP028785; Wed, 26 Sep 2018 23:49:03 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:45 +1000 Message-Id: <20180927044849.28322-6-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 5/9] cpu: Keep track of the "ec_primary" in big core more X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The "EC" primary is the primary thread of an EC, ie, the corresponding small core "half" of the big core where the thread resides. It will be necessary for the direct controls to target the right half when doing special wakeups among others. Signed-off-by: Benjamin Herrenschmidt --- core/cpu.c | 20 ++++++++++++++------ include/cpu.h | 1 + 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index 4b7bd059..0a0c5d7e 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -803,9 +803,11 @@ struct cpu_thread *first_ungarded_cpu(void) struct cpu_thread *next_ungarded_primary(struct cpu_thread *cpu) { + bool is_primary; do { cpu = next_cpu(cpu); - } while(cpu && (cpu->state == cpu_state_unavailable || cpu->primary != cpu)); + is_primary = cpu == cpu->primary || cpu == cpu->ec_primary; + } while(cpu && (cpu->state == cpu_state_unavailable || !is_primary)); return cpu; } @@ -1148,7 +1150,7 @@ void init_all_cpus(void) unsigned int pir, server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; - struct cpu_thread *t, *pt; + struct cpu_thread *t, *pt0, *pt1; /* Skip cache nodes */ if (strcmp(dt_prop_get(cpu, "device_type"), "cpu")) @@ -1183,14 +1185,18 @@ void init_all_cpus(void) /* Setup thread 0 */ assert(pir <= cpu_max_pir); - t = pt = &cpu_stacks[pir].cpu; + t = pt0 = &cpu_stacks[pir].cpu; if (t != boot_cpu) { init_cpu_thread(t, state, pir); /* Each cpu gets its own later in init_trace_buffers */ t->trace = boot_cpu->trace; } + if (t->is_fused_core) + pt1 = &cpu_stacks[pir + 1].cpu; + else + pt1 = pt0; t->server_no = server_no; - t->primary = t; + t->primary = t->ec_primary = t; t->node = cpu; t->chip_id = chip_id; t->icp_regs = NULL; /* Will be set later */ @@ -1228,10 +1234,12 @@ void init_all_cpus(void) t->trace = boot_cpu->trace; t->server_no = ((const u32 *)p->prop)[thread]; t->is_secondary = true; - t->primary = pt; + t->is_fused_core = pt0->is_fused_core; + t->primary = pt0; + t->ec_primary = (thread & 1) ? pt1 : pt0; t->node = cpu; t->chip_id = chip_id; - t->core_hmi_state_ptr = &pt->core_hmi_state; + t->core_hmi_state_ptr = &pt0->core_hmi_state; } prlog(PR_INFO, "CPU: %d secondary threads\n", thread); } diff --git a/include/cpu.h b/include/cpu.h index 2fb5edd2..a8ac5678 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -56,6 +56,7 @@ struct cpu_thread { bool is_secondary; bool is_fused_core; struct cpu_thread *primary; + struct cpu_thread *ec_primary; enum cpu_thread_state state; struct dt_node *node; struct trace_info *trace; From patchwork Thu Sep 27 04:48:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975533 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMmg2QQ1z9s3Z for ; Thu, 27 Sep 2018 14:49:55 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMmg13FfzF36b for ; Thu, 27 Sep 2018 14:49:55 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMm237S3zF33P for ; Thu, 27 Sep 2018 14:49:22 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRQ028785; Wed, 26 Sep 2018 23:49:06 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:46 +1000 Message-Id: <20180927044849.28322-7-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 6/9] direct-ctl: Use the EC primary for special wakeups X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Benjamin Herrenschmidt --- core/direct-controls.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 04b93a16..11686faf 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -550,7 +550,7 @@ static int p9_sreset_thread(struct cpu_thread *cpu) int dctl_set_special_wakeup(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc = OPAL_SUCCESS; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) @@ -572,7 +572,7 @@ int dctl_set_special_wakeup(struct cpu_thread *t) int dctl_clear_special_wakeup(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc = OPAL_SUCCESS; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) @@ -597,7 +597,7 @@ out: int dctl_core_is_gated(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; uint32_t chip_id = pir_to_chip_id(c->pir); uint32_t core_id = pir_to_core_id(c->pir); uint32_t sshhyp_addr; @@ -620,7 +620,7 @@ int dctl_core_is_gated(struct cpu_thread *t) static int dctl_stop(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) @@ -644,7 +644,7 @@ static int dctl_stop(struct cpu_thread *t) static int dctl_cont(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; if (proc_gen != proc_gen_p9) @@ -671,7 +671,7 @@ static int dctl_cont(struct cpu_thread *t) */ static int dctl_sreset(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) From patchwork Thu Sep 27 04:48:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMmw1V0Pz9s3Z for ; Thu, 27 Sep 2018 14:50:08 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMmw0BppzF378 for ; Thu, 27 Sep 2018 14:50:08 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMm66V23zF333 for ; Thu, 27 Sep 2018 14:49:26 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRR028785; Wed, 26 Sep 2018 23:49:08 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:47 +1000 Message-Id: <20180927044849.28322-8-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 7/9] slw: Limit fused cores P9 to STOP0/1 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Linux doesn't know how to properly restore state on "both halves" of a fused core, so limit ourselves to STOP states that don't require HV state restore for bare metal kernels (KVM is still broken) until we add a new representation for STOP states. The new representation will have per-state versioning so that we can control their individual enablement based on whether the OS has the necessary workarounds to make them work. Signed-off-by: Benjamin Herrenschmidt --- hw/slw.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/hw/slw.c b/hw/slw.c index dfa9189b..10907391 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -793,6 +793,70 @@ static struct cpu_idle_states power9_ndd1_cpu_idle_states[] = { | OPAL_PM_PSSCR_EC, .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK } }; + +static struct cpu_idle_states power9_bigcores_cpu_idle_states[] = { + { + .name = "stop0_lite", /* Enter stop0 with no state loss */ + .latency_ns = 1000, + .residency_ns = 10000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 0*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3), + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop0", + .latency_ns = 2000, + .residency_ns = 20000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop1_lite", /* Enter stop1 with no state loss */ + .latency_ns = 4900, + .residency_ns = 49000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 0*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(1) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3), + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop1", + .latency_ns = 5000, + .residency_ns = 50000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(1) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, +}; + static void slw_late_init_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -880,6 +944,9 @@ void add_cpu_idle_state_properties(void) (chip->type == PROC_CHIP_P9_NIMBUS)) { states = power9_ndd1_cpu_idle_states; nr_states = ARRAY_SIZE(power9_ndd1_cpu_idle_states); + } else if (this_cpu()->is_fused_core) { + states = power9_bigcores_cpu_idle_states; + nr_states = ARRAY_SIZE(power9_bigcores_cpu_idle_states); } else { states = power9_cpu_idle_states; nr_states = ARRAY_SIZE(power9_cpu_idle_states); From patchwork Thu Sep 27 04:48:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMnx44PJz9s3Z for ; Thu, 27 Sep 2018 14:51:01 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMnx2mxWzF36b for ; Thu, 27 Sep 2018 14:51:01 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMmQ5NLHzF35Y for ; Thu, 27 Sep 2018 14:49:42 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRS028785; Wed, 26 Sep 2018 23:49:11 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:48 +1000 Message-Id: <20180927044849.28322-9-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 8/9] cpu: Make cpu_get_core_index() return the fused core number X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" cpu_get_core_index() currently uses pir_to_core_id() which returns an EC number always (ie, a small core number) even in fused core mode. This is inconsistent with cpu_get_thread_index() which returns a thread within a fused core (0...7) on P9. So let's make things consistent and document it. Signed-off-by: Benjamin Herrenschmidt --- core/chip.c | 13 +++++++++++++ core/cpu.c | 2 +- include/chip.h | 5 +++++ include/cpu.h | 6 ++++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/core/chip.c b/core/chip.c index 902327e1..60c7a6e7 100644 --- a/core/chip.c +++ b/core/chip.c @@ -48,6 +48,19 @@ uint32_t pir_to_core_id(uint32_t pir) return P7_PIR2COREID(pir); } +uint32_t pir_to_fused_core_id(uint32_t pir) +{ + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIR2FUSEDCOREID(pir); + else + return P9_PIR2COREID(pir); + } else if (proc_gen == proc_gen_p8) + return P8_PIR2COREID(pir); + else + return P7_PIR2COREID(pir); +} + uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { diff --git a/core/cpu.c b/core/cpu.c index 0a0c5d7e..53dae741 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -846,7 +846,7 @@ struct cpu_thread *first_available_core_in_chip(u32 chip_id) uint32_t cpu_get_core_index(struct cpu_thread *cpu) { - return pir_to_core_id(cpu->pir); + return pir_to_fused_core_id(cpu->pir); } void cpu_remove_node(const struct cpu_thread *t) diff --git a/include/chip.h b/include/chip.h index a9ab5560..322f84e9 100644 --- a/include/chip.h +++ b/include/chip.h @@ -268,6 +268,11 @@ extern uint32_t pir_to_chip_id(uint32_t pir); extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir); +/* In P9 fused core mode, this is the "fused" core ID, in + * normal core mode or P8, this is the same as pir_to_core_id + */ +extern uint32_t pir_to_fused_core_id(uint32_t pir); + extern struct proc_chip *next_chip(struct proc_chip *chip); #define for_each_chip(__c) for (__c=next_chip(NULL); __c; __c=next_chip(__c)) diff --git a/include/cpu.h b/include/cpu.h index a8ac5678..3a266535 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -242,6 +242,12 @@ static inline __nomcount struct cpu_thread *this_cpu(void) return __this_cpu; } +/* + * Note: On POWER9 fused core, cpu_get_thread_index() and cpu_get_core_index() + * return respectively the thread number within a fused core (0..7) and + * the fused core number. If you want the EC (small core) number, you have + * to use the low level pir_to_core_id() and pir_to_thread_id(). + */ /* Get the thread # of a cpu within the core */ static inline uint32_t cpu_get_thread_index(struct cpu_thread *cpu) { From patchwork Thu Sep 27 04:48:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975538 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LMpF2XMTz9s3Z for ; Thu, 27 Sep 2018 14:51:17 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LMpF0bbqzF35n for ; Thu, 27 Sep 2018 14:51:17 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LMmT2Q3DzF325 for ; Thu, 27 Sep 2018 14:49:44 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRT028785; Wed, 26 Sep 2018 23:49:13 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:49 +1000 Message-Id: <20180927044849.28322-10-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 9/9] imc: Use pir_to_core_id() rather than cpu_get_core_index() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The IMC HW targets HW ECs, not fused cores on P9 Signed-off-by: Benjamin Herrenschmidt --- hw/imc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index 3392eaf1..0491fc51 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -657,7 +657,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu * pdbar in specific scom ports. port_id are in * pdbar_scom_index[] and htm_scom_index[]. */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -777,7 +777,7 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) * Core IMC hardware mandates setting of htm_mode in specific * scom ports (port_id are in htm_scom_index[]) */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -838,7 +838,7 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) * Core IMC hardware mandates setting of htm_mode in specific * scom ports (port_id are in htm_scom_index[]) */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)