From patchwork Wed Sep 26 13:55:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975183 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Lt7FzAGE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0XJ6vXZz9s4Z for ; Thu, 27 Sep 2018 00:22:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B3D73C21F3A; Wed, 26 Sep 2018 14:05:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2EC0FC21F99; Wed, 26 Sep 2018 13:50:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9F9D2C21F94; Wed, 26 Sep 2018 13:50:47 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 4D92DC21F99 for ; Wed, 26 Sep 2018 13:50:30 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id r77-v6so8845700pgr.5 for ; Wed, 26 Sep 2018 06:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=GqdBT4Ueeupfz3gZS65aRsorEQtE3EudLkWjwIByiDQ=; b=Lt7FzAGE4ME9DD4dAFc6ISWfc2AXJvJF7YG7yuo1agdJc3y5ic1lDeOgDnQblnENJv 7BJsTUQKe5pvRrt45XEdROx3e7/ixlEJzfdYQUu5NVMvqDphD11vfoCyPnrghCmoPCy2 JCueFwyLY0SdbwSiB4QDfIBW38GriofwM0kjxppF9z3XEkQPMlG1Oga0Bx/yfXUU/vAw Rsp4l9LTf2IPMbXeOjdREHdKPZRQlmTGKd8QW3pCiX3U40PBDYQwB0IzV5o5g/oMVZbO YLfHFT0V6KfD1aBFrbq4RdJZ/ZQZclQV/w4PkoSPIesj/1aJvQegLCwsFhvcUv+KqEIr PJsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=GqdBT4Ueeupfz3gZS65aRsorEQtE3EudLkWjwIByiDQ=; b=XRiD8aLKT4DenyvEFL9Fuq49dFC/wLIfd32Znwu1iJhOFYbf1FzpY/GgUhZfUM5A/M NdukoNMv1th4Pz689qgTKqY5pmsgueahS0nqgzWAnS/sjz7+rxNjNmCaFXeeHncSaNCb tGlg9CF1QuaYKCW5NCAY04OqFljl0abIBxMad8wid4kpr9ca90pff7qOgcw7+W7VnB89 DWXYbL9SlN0yatlA25I2XFlRMgRfy7P6j2RSmlXioGv+RItDvp05msdxF1K2JEnUoOaP ESxX+87y/fh6opjTHh9AVL1j1F6bi+QAYLOw7BN0O+tDNYjCaa+Ql5Vzni6pFq37G74f bzdg== X-Gm-Message-State: ABuFfojVb71DKhhyOj9CrytHMCzhI6Zpi8cSbdjPngZcyOm8wL2kVXej l/R6sUzJNUL8hSSiynUEVG4= X-Google-Smtp-Source: ACcGV61n/btXgAFk0JT1k00qiiTtkHSXVIToaeG4vDgyinouxbgHdHRgMVQaOPKOoQeSialPSWZcGg== X-Received: by 2002:a62:1895:: with SMTP id 143-v6mr6345587pfy.227.1537969828889; Wed, 26 Sep 2018 06:50:28 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.27 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:27 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:06 -0700 Message-Id: <1537970122-26443-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 01/17] riscv: kconfig: Normalize architecture name spelling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- Changes in v3: None Changes in v2: None arch/Kconfig | 2 +- arch/riscv/Kconfig | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 11900b0..cd424fd 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -60,7 +60,7 @@ config PPC select SYS_BOOT_GET_KBD config RISCV - bool "riscv architecture" + bool "RISC-V architecture" select SUPPORT_OF_CONTROL config SANDBOX diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 20a43d8..49f87de 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1,4 +1,4 @@ -menu "RISCV architecture" +menu "RISC-V architecture" depends on RISCV config SYS_ARCH @@ -20,13 +20,13 @@ choice default CPU_RISCV_32 config CPU_RISCV_32 - bool "RISCV 32 bit" + bool "RISC-V 32-bit" select 32BIT help Choose this option to build an U-Boot for RISCV32 architecture. config CPU_RISCV_64 - bool "RISCV 64 bit" + bool "RISC-V 64-bit" select 64BIT help Choose this option to build an U-Boot for RISCV64 architecture. From patchwork Wed Sep 26 13:55:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975159 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VdbjqstX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0Hc6ZJ5z9s4s for ; Thu, 27 Sep 2018 00:11:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 70942C21E44; Wed, 26 Sep 2018 14:05:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 74B54C21F22; Wed, 26 Sep 2018 13:50:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0F711C21F3F; Wed, 26 Sep 2018 13:50:47 +0000 (UTC) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by lists.denx.de (Postfix) with ESMTPS id 9526FC21ED5 for ; Wed, 26 Sep 2018 13:50:31 +0000 (UTC) Received: by mail-pf1-f194.google.com with SMTP id b7-v6so6066036pfo.3 for ; Wed, 26 Sep 2018 06:50:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=IAvd1g6GBrkYMkA5zRz+6YR6lqVbGuX892VYEoCnOqg=; b=VdbjqstXJbehKP95JS3XTGpeK2gExalTbaj6u/3AhQdpj19o3YGtGXW5UEDi+/op/b VzTVjhUyY2KF0qPsrPnoICF+D8qwMpZZphb/MrAFaz2HyIY4puUrWyAPpzn8Z1zXs5Oo t02m1qlLS4UPUC+PYJNMldTdiMnSrCwUUtKo5/Z+MVW3Eema5mHKfVIHay8uWyGuhNsY kZqWS0vItIuGot5kaKURhpNT9pMAoNpTkByBL6Idx1DRpSliUCNBWEp4QL+Y88+fPYEt YyVLvrwoDXYVq3wK74D07UfQATFiSUhRfdJKtVZIPneQMk9nLB/JOwpGdRIDMuNlAdon vpGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=IAvd1g6GBrkYMkA5zRz+6YR6lqVbGuX892VYEoCnOqg=; b=TQD5++/glPGkC6eyIwHYpyj7Vx2PQLWMK1fVUhMi/8kAuHoorzuwJbwfOpmUZVcjNo y+ukMpZo830uba5guqKPjbeIpOQ+LeG6bEzZrNck3U2EYgFYYRcm/NIGBiGSz4YhCe2/ 8KBMxlrfVBt8/n7p7oOZg/HCSRugq70y+jZu5xcDboCezGj0I/nNyOCioiA/j8LAcjVX jl5rfSQ914tDSPwkwGCUulsZ7Pt5YXz36xEj88V2Ta9pw2oRpJMZJQldIrUxhGWNAo9W fzDhUIgOqxDzDzqkvT67vzMmAyEjHTKgF9jb1U10bNB7mvdYqwACrEVUae4/0evRUXdG P69w== X-Gm-Message-State: ABuFfogO19r99kjmBc+ihSVVZwWeK4p7d5POwvbOcH//rLkuEOmWlFX3 Xsct5TyOY1K/qkROY+F+hVjkFCa8 X-Google-Smtp-Source: ACcGV61YeiBatSJQd87cedtGk/tk7XJR7xea3KnaUe+d0wmhYGm4WybhkFhbO8nwzyWxq1oHiAQD6w== X-Received: by 2002:a62:1157:: with SMTP id z84-v6mr6524170pfi.66.1537969830150; Wed, 26 Sep 2018 06:50:30 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.28 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:29 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:07 -0700 Message-Id: <1537970122-26443-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 02/17] riscv: Remove setup.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This was copied from ARM, and does not apply to RISC-V. While we are here, bootm.h is eventually removed as its content is only the inclusion of setup.h. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/setup.h | 194 ----------------------------------------- arch/riscv/lib/bootm.c | 1 - 3 files changed, 208 deletions(-) delete mode 100644 arch/riscv/include/asm/bootm.h delete mode 100644 arch/riscv/include/asm/setup.h diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h deleted file mode 100644 index 6786345..0000000 --- a/arch/riscv/include/asm/bootm.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013, Google Inc. - * - * Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz - */ -#ifndef NDS32_BOOTM_H -#define NDS32_BOOTM_H - -#include - -#endif diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h deleted file mode 100644 index ff8de16..0000000 --- a/arch/riscv/include/asm/setup.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/nds32/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * Copyright (C) 2008 Andes Technology Corporation - * Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com) - * Copyright (C) 2017 Rick Chen (rick@andestech.com) - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See Documentation/arm/Setup - * for more info. - */ -#ifndef __RISCV_SETUP_H -#define __RISCV_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* - * this one accidentally used virtual addresses - as such, - * it's deprecated. - * describes where the compressed ramdisk image lives (virtual address) - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[COMMAND_LINE_SIZE]; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define tag_member_present(_tag, member) \ - typeof(_tag) (tag) = (_tag); \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(_t) \ - typeof(_t) (t) = (_t); \ - ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(_t, base) \ - typeof(_t) (t) = (_t); \ - for (t = base; t->hdr.size; t = tag_next(t)) - -#ifdef __KERNEL__ - -#define __tag __used __attribute__((__section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -/* - * Early command line parameters. - */ -struct early_params { - const char *arg; - void (*fn)(char **p); -}; - -#define __early_param(name, fn) \ -static struct early_params __early_##fn __used \ -__attribute__((__section__("__early_param"))) = { name, fn } - -#endif -#endif diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 2610a57..6662aff 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -11,7 +11,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; From patchwork Wed Sep 26 13:55:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975163 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.30 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:30 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:08 -0700 Message-Id: <1537970122-26443-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 03/17] riscv: bootm: Correct the 1st kernel argument to hart id X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm. While we are here, this also changes the Linux kernel entry parameters' type to support both 32-bit and 64-bit. Note the hart id is hardcoded to zero for now, and we should change to fill in it with the value read from mhartid CSR of the hart which this routine is currently running on. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- Changes in v3: None Changes in v2: - Change Linux kernel entry parameters' type to support 32/64 bit arch/riscv/lib/bootm.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6662aff..6893108 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob) int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { - bd_t *bd = gd->bd; - char *s; - int machid = bd->bi_arch_number; - void (*theKernel)(int arch, uint params); + void (*kernel)(ulong hart, void *dtb); /* * allow the PREP bootm subcommand, it is required for bootm to work @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - theKernel = (void (*)(int, uint))images->ep; - - s = env_get("machid"); - if (s) { - machid = simple_strtoul(s, NULL, 16); - printf("Using machid 0x%x from environment\n", machid); - } + kernel = (void (*)(ulong, void *))images->ep; bootstage_mark(BOOTSTAGE_ID_RUN_OS); debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong)theKernel); + (ulong)kernel); if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) printf("\nStarting kernel ...\n\n"); cleanup_before_linux(); + /* TODO: hardcode the hart id to zero for now */ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - theKernel(machid, (unsigned long)images->ft_addr); + kernel(0, images->ft_addr); /* does not return */ From patchwork Wed Sep 26 13:55:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975174 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.31 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:31 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:09 -0700 Message-Id: <1537970122-26443-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 04/17] riscv: Remove mach type X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Since the mach_id is not used by RISC-V, remove it. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/include/asm/mach-types.h | 29 ----------------------------- arch/riscv/include/asm/u-boot.h | 1 - board/AndesTech/ax25-ae350/ax25-ae350.c | 2 -- cmd/bdinfo.c | 1 - 4 files changed, 33 deletions(-) delete mode 100644 arch/riscv/include/asm/mach-types.h diff --git a/arch/riscv/include/asm/mach-types.h b/arch/riscv/include/asm/mach-types.h deleted file mode 100644 index f219ced..0000000 --- a/arch/riscv/include/asm/mach-types.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#ifndef __ASM_RISCV_MACH_TYPE_H -#define __ASM_RISCV_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -#define MACH_TYPE_AE350 1 - -#ifdef CONFIG_ARCH_AE350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AE350 -# endif -# define machine_is_ae350() (machine_arch_type == MACH_TYPE_AE350) -#else -# define machine_is_ae350() (1) -#endif - -#endif /* __ASM_RISCV_MACH_TYPE_H */ diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h index 9e5b32d..3186835 100644 --- a/arch/riscv/include/asm/u-boot.h +++ b/arch/riscv/include/asm/u-boot.h @@ -23,7 +23,6 @@ #include typedef struct bd_info { - unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ unsigned long bi_memsize; /* size of DRAM memory in bytes */ diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index fd5aaa1..5f4ca0f 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -4,7 +4,6 @@ * Rick Chen, Andes Technology Corporation */ -#include #include #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) #include @@ -21,7 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_AE350; gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; return 0; diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 397dd15..bc440e4 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -424,7 +424,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { bd_t *bd = gd->bd; - print_num("arch_number", bd->bi_arch_number); print_bi_boot_params(bd); print_bi_dram(bd); print_eth_ip_addr(); From patchwork Wed Sep 26 13:55:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975165 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oGfTS8B0"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0LZ3p9Tz9s4s for ; Thu, 27 Sep 2018 00:14:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3B593C21E74; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.32 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:32 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:10 -0700 Message-Id: <1537970122-26443-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 05/17] riscv: cmd: bdinfo: Print the relocation address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add printing of U-Boot relocation address. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - net patch to print the relocation address in cmd 'bdinfo' Changes in v2: None cmd/bdinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index bc440e4..60b4387 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -426,6 +426,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_boot_params(bd); print_bi_dram(bd); + print_num("relocaddr", gd->relocaddr); + print_num("reloc off", gd->reloc_off); print_eth_ip_addr(); print_baudrate(); From patchwork Wed Sep 26 13:55:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975166 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TWVhsQsG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0MJ4Yjfz9s4s for ; Thu, 27 Sep 2018 00:15:08 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 33ABAC21E42; Wed, 26 Sep 2018 14:06:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE595C21E44; Wed, 26 Sep 2018 13:51:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A96CCC21F00; Wed, 26 Sep 2018 13:50:58 +0000 (UTC) Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) by lists.denx.de (Postfix) with ESMTPS id 2A6D7C21F00 for ; Wed, 26 Sep 2018 13:50:36 +0000 (UTC) Received: by mail-pl1-f181.google.com with SMTP id v19-v6so2326569ply.13 for ; Wed, 26 Sep 2018 06:50:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=x3Xm19uIWnxVdlFNer+C5CpxvwRLzL+n8PKKsmRiGyo=; b=TWVhsQsGxxBxR/be4KBcH6FdJGW80tDgkxzV5V69l5+Aak0jCLQRRTNXs7e84TVsmR WVn0SGffKpSGXPE+ajep2fWo9Bfz2vwSuvGv1EWZc5pykFhznycZZcKOTudpj6XmE5gd irhkVo7E7rq32WAMezCeH5dSXwQ9ylPRpV6NTKH+UsgSAWLJC//5xyl0vUyk+t4WTrb5 PgweINBXN0KR47lnH7Tz2N6IDmoj4x+oUxhE++kkEYWKXcf4fKeogTMSIRuK7vFKSnGB i04qPMZBDtp9jQncB/qpev2NhO1/Vtwsh7yN1QSuM/pQxnPTrNySw5LVCz6PBOHApmaC CrjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=x3Xm19uIWnxVdlFNer+C5CpxvwRLzL+n8PKKsmRiGyo=; b=Vega3NTfb2rZt5wAkQ020ius5mRcx6CWwgk53zaeiGOFOBbx/GehZ6gMQw626asweP uKcgZ0FjL9oJtGvw3Iw9263UVWxXwrpfPdagjDko8YtoYrw5z12oZOXbeUAKjFhhqjCe 9Ph6xRDNMpceWxmP4xaR3GumSAik771hSgs0GHpwh1Ec9orrfN8/PAlI40W2xZpWss6F V739ti6nOydcdQNzXzML65UxUGCOuN9j/WKLTahS8A6JwyH171O2/1Ev8maq9MIRYv0y 8vt9/K+/Nb0pA3ywOs1vSs9+K/MjW/PqTMy0JWhlBc3nzIkS9GmmqdsfmBve1xCUQcqD MATQ== X-Gm-Message-State: ABuFfojhz70vl4kd3Kp8AJ09/3yGgHwZWPgkO5QpydJgv2KtfvIjEfeB gjFQBtGuZrgXOChPcrmcyWQ= X-Google-Smtp-Source: ACcGV62dPpaOd9onM0o2ctTL6z341iyGB6fM06sH+OoYC95rjM7O4QSQFBH4rI7YxBWi6oLCmLexgg== X-Received: by 2002:a17:902:c3:: with SMTP id a61-v6mr6069207pla.279.1537969834849; Wed, 26 Sep 2018 06:50:34 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.33 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:34 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:11 -0700 Message-Id: <1537970122-26443-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 06/17] riscv: Move the linker script to the CPU root directory X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The linker script can be shared by all RISC-V targets. Move it to a common place. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/cpu/{ax25 => }/u-boot.lds | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/riscv/cpu/{ax25 => }/u-boot.lds (100%) diff --git a/arch/riscv/cpu/ax25/u-boot.lds b/arch/riscv/cpu/u-boot.lds similarity index 100% rename from arch/riscv/cpu/ax25/u-boot.lds rename to arch/riscv/cpu/u-boot.lds From patchwork Wed Sep 26 13:55:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975175 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GmM4yq/l"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0Sr4pgfz9s4s for ; Thu, 27 Sep 2018 00:19:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 5B5B0C21F0F; Wed, 26 Sep 2018 14:06:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E5FEBC21FAF; Wed, 26 Sep 2018 13:51:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4AE73C21EFC; Wed, 26 Sep 2018 13:50:59 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id 5185BC21EB9 for ; Wed, 26 Sep 2018 13:50:37 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id w14-v6so9986252plp.6 for ; Wed, 26 Sep 2018 06:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=j7/hnxxNfxmX9Xk+oDsA+APh2banIUFX9xiMaqW8od0=; b=GmM4yq/lRpuubeimYYQMW6KzNmeCWXVz6cIBR8hp/pjiAEVLhcmZ7EvGxpwUjkZv8Q BKDBE7+7rZNAnyBFur25tj+FYUzzkIMc1XvXJ1YIJfzzBC7y65bPJ7D6EEyWYEBpZmN3 D+yuhDOeEwNf8n6UJjk8EhXR5aeyDutO1gzvRzky+W4HmfRF9bOcHHdVyYpE0l2mqiOL /2ziaSHWY5G0El2Zi78TbMAGvBbDEtkJuj/19gSsAS/Z/LtggASIY8CaZZYtt24Ud4Pm 6nYnYjPwsNK7BOcqOqz6SRU9C3u+oh9M8LtqFN/iBi4s/To8KowtldKPx47m7snfE0+N I6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=j7/hnxxNfxmX9Xk+oDsA+APh2banIUFX9xiMaqW8od0=; b=h9vtV01dhPoF+HNjrMCgD1Gq+BlhkTWLwZTYX7GoGYfhevXCbPjhld/k6QiwPddDdL 2jpO65mu3/MCVc6FOnK4rbMtTYRYHTtBsOKzHjkpIDU5QSedrd8i9sWgt8rFN3Nn4dy6 4FlKTbq0lDWgfseZPXJ9lVJyLBIoKtnJ9NrFr6nzyGVVXGLBf/JaB0yroMBVQb+LP9df +irf+ppVnvwhD6W6AoRCRiOhcbzhCkdwiCB6liuBP8cOfnep0o6f1/ZUE4ilKlO1JFk5 G83Ijo1E2Cxnd9qs3wxpcDBMZLceXw8QBmsgyvNH5N5U2ZBAtdO2EN6x/lcyCT/HY5La swQQ== X-Gm-Message-State: ABuFfohUOB2MZESwDbaifVQJ3bKI0H4oCDETdLvk6PYGwrj97WfxP7Td PYB/hmkmoIqKSFtUxAThpck= X-Google-Smtp-Source: ACcGV61uT6DPEzdYQxEZQL0r47ZxiZLlBB5CTIq44r9z4/Nz34Cycfw1RyFWZLYREn9iRqVIstoHXQ== X-Received: by 2002:a17:902:a618:: with SMTP id u24-v6mr6278137plq.77.1537969835975; Wed, 26 Sep 2018 06:50:35 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.34 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:35 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:12 -0700 Message-Id: <1537970122-26443-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 07/17] riscv: Fix coding style issues in the linker script X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There are several coding style issues in the linker script. Fix them. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/cpu/u-boot.lds | 58 +++++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index c50b964..f414473 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -3,28 +3,27 @@ * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation */ + OUTPUT_ARCH("riscv") ENTRY(_start) SECTIONS { . = ALIGN(4); - .text : - { + .text : { arch/riscv/cpu/ax25/start.o (.text) } /* This needs to come before *(.text*) */ .efi_runtime : { - __efi_runtime_start = .; + __efi_runtime_start = .; *(.text.efi_runtime*) *(.rodata.efi_runtime*) *(.data.efi_runtime*) - __efi_runtime_stop = .; + __efi_runtime_stop = .; } - .text_rest : - { + .text_rest : { *(.text*) } @@ -39,10 +38,10 @@ SECTIONS . = ALIGN(4); .got : { - __got_start = .; - *(.got.plt) *(.got) - __got_end = .; - } + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } . = ALIGN(4); @@ -50,41 +49,40 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(4); .efi_runtime_rel : { - __efi_runtime_rel_start = .; + __efi_runtime_rel_start = .; *(.rel*.efi_runtime) *(.rel*.efi_runtime.*) - __efi_runtime_rel_stop = .; + __efi_runtime_rel_stop = .; } - . = ALIGN(4); + . = ALIGN(4); - /DISCARD/ : { *(.rela.plt*) } - .rela.dyn : { - __rel_dyn_start = .; - *(.rela*) - __rel_dyn_end = .; - } + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } - . = ALIGN(4); + . = ALIGN(4); - .dynsym : { - __dyn_sym_start = .; - *(.dynsym) - __dyn_sym_end = .; - } + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } - . = ALIGN(4); + . = ALIGN(4); _end = .; .bss : { - __bss_start = .; - *(.bss*) + __bss_start = .; + *(.bss*) . = ALIGN(4); __bss_end = .; } - } From patchwork Wed Sep 26 13:55:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975164 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FwubZu9e"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0LC4zf6z9s4s for ; Thu, 27 Sep 2018 00:14:11 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 08413C21E13; Wed, 26 Sep 2018 14:07:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 325ECC21F38; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.36 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:36 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:13 -0700 Message-Id: <1537970122-26443-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 08/17] riscv: Explicitly pass -march and -mabi to the compiler X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain configured for 64-bit riscv). Fix this by explicitly passing -march and -mabi to the compiler. Since generically we don't use floating point in U-Boot, specify the RV[32|64]IMA ISA and software floating ABI. This also fix some alignment coding style issues. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/config.mk | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index c0b3858..b235ae1 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -18,12 +18,16 @@ endif 64bit-emul := elf64lriscv ifdef CONFIG_32BIT +PLATFORM_CPPFLAGS += -march=rv32ima -mabi=ilp32 PLATFORM_LDFLAGS += -m $(32bit-emul) +CFLAGS_EFI += -march=rv32ima -mabi=ilp32 EFI_LDS := elf_riscv32_efi.lds endif ifdef CONFIG_64BIT +PLATFORM_CPPFLAGS += -march=rv64ima -mabi=lp64 PLATFORM_LDFLAGS += -m $(64bit-emul) +CFLAGS_EFI += -march=rv64ima -mabi=lp64 EFI_LDS := elf_riscv64_efi.lds endif @@ -31,8 +35,8 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ -T $(srctree)/examples/standalone/riscv.lds PLATFORM_CPPFLAGS += -ffixed-gp -fpic -PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections -LDFLAGS_u-boot += --gc-sections -static -pie +PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections +LDFLAGS_u-boot += --gc-sections -static -pie EFI_CRT0 := crt0_riscv_efi.o EFI_RELOC := reloc_riscv_efi.o From patchwork Wed Sep 26 13:55:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975184 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="q3YXM8m/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0XP6f2fz9s4Z for ; Thu, 27 Sep 2018 00:23:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A6A03C21E70; Wed, 26 Sep 2018 14:06:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D12FAC21E57; Wed, 26 Sep 2018 13:51:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1D438C21E57; Wed, 26 Sep 2018 13:51:00 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id A1369C21E76 for ; Wed, 26 Sep 2018 13:50:39 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id p25-v6so2878507pli.11 for ; Wed, 26 Sep 2018 06:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=XhStNfKV+AZaGRa8rI5Byz6+FyQG0C9DW2qsXZOj4JM=; b=q3YXM8m/zpaOy57ne+ikBFTLxZdXJn58YJaZ0EPHuTImBJ2A4F4hnvw/j/pC/OBLPa FoGVLCSUHlMGGLsayEkYJRGqeU4IVwbcasD8HbN9FVxCcy7Zjy4rLp9ZwwPuIoJIYcwd YW6tDWoOdmT0f5lEGenwZMHHbvZNNf+kQI3aSsLWMEQ2nn014YtaGTkbnetlj+og7CVK NamzE7K0S8xCk/G2VqkpIIYPu7Ck1XTw/5gvfSRN0ZtoURD2Lr+P9wR08E8PfN79eLDm mMP5Zr2rPDmOZaaDkrvM+Tab0uUZwhMAnPv3qXbrzC1uOIThx03ddZeSeJVYM8pSgcDC QJzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=XhStNfKV+AZaGRa8rI5Byz6+FyQG0C9DW2qsXZOj4JM=; b=rG4izsB1BN11uISnEAw9gqF9NymYyRbG8L2dr5e568vC4/mBbmDh8GOY5Xxh18H1pf fKYXPPTOZQzCZXXLOxnI0kpVmqrw6D5aCG3o/s8T4Xuh9g+fogSzGkKriypd3X4hdbX7 nym0eGZabO4yPodgSr9djRkwW7T6NPcHqKa5jBnop9orY6veg9yZiRxz9bztxWrvj1qs QzDQM1cWqe9GZAtJi6FKLYGe0c8lW+B4HgHvZC6Pluz1m1ezVwqlJIRILB5ebjNas8Xl kTKi61X9+0MS9GFTb+f1uZywRJtnLjBgTEye4vC+WuLVksfei2Z/kCRCvV3uSu3mZ0XI YZkA== X-Gm-Message-State: ABuFfogGx/bOZXCRfyP43rKZD9dN0KAyL9zsFxpqmqt5vJqV8Nx3165Z wIDjoPe/NvJbPqc/HA2p1lk= X-Google-Smtp-Source: ACcGV60VCweS5Y3YQHhO7aa67BuZ+CYkKrTmijpAymw0JT2rcNt/3z5wBp1EpkPA5wdyNGJoDtMUig== X-Received: by 2002:a17:902:f203:: with SMTP id gn3mr4640202plb.162.1537969838220; Wed, 26 Sep 2018 06:50:38 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.37 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:37 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:14 -0700 Message-Id: <1537970122-26443-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 09/17] riscv: Add a helper routine to print CPU information X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/Makefile | 1 + arch/riscv/cpu/Makefile | 5 ++ arch/riscv/cpu/cpu.c | 49 +++++++++++++++++ arch/riscv/include/asm/csr.h | 124 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 179 insertions(+) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/include/asm/csr.h diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 084888a..af432e1 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,5 +5,6 @@ head-y := arch/riscv/cpu/$(CPU)/start.o +libs-y += arch/riscv/cpu/ libs-y += arch/riscv/cpu/$(CPU)/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile new file mode 100644 index 0000000..63de163 --- /dev/null +++ b/arch/riscv/cpu/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +obj-y += cpu.o diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c new file mode 100644 index 0000000..ae57fb8 --- /dev/null +++ b/arch/riscv/cpu/cpu.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +enum { + ISA_INVALID = 0, + ISA_32BIT, + ISA_64BIT, + ISA_128BIT +}; + +static const char * const isa_bits[] = { + [ISA_INVALID] = NULL, + [ISA_32BIT] = "32", + [ISA_64BIT] = "64", + [ISA_128BIT] = "128" +}; + +static inline bool supports_extension(char ext) +{ + return csr_read(misa) & (1 << (ext - 'a')); +} + +int print_cpuinfo(void) +{ + char name[32]; + char *s = name; + int bit; + + s += sprintf(name, "rv"); + bit = csr_read(misa) >> (sizeof(long) * 8 - 2); + s += sprintf(s, isa_bits[bit]); + + supports_extension('i') ? *s++ = 'i' : 'r'; + supports_extension('m') ? *s++ = 'm' : 'i'; + supports_extension('a') ? *s++ = 'a' : 's'; + supports_extension('f') ? *s++ = 'f' : 'c'; + supports_extension('d') ? *s++ = 'd' : '-'; + supports_extension('c') ? *s++ = 'c' : 'v'; + *s++ = '\0'; + + printf("CPU: %s\n", name); + + return 0; +} diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index 0000000..50fccea --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Regents of the University of California + * + * Taken from Linux arch/riscv/include/asm/csr.h + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) + +#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif + +/* SATP flags */ +#if __riscv_xlen == 32 +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#endif + +/* Interrupt Enable and Interrupt Pending flags */ +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ + +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 + +#ifndef __ASSEMBLY__ + +#define csr_swap(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " #csr \ + : "=r" (__v) : \ + : "memory"); \ + __v; \ +}) + +#define csr_write(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrw " #csr ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrs " #csr ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrc " #csr ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_CSR_H */ From patchwork Wed Sep 26 13:55:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975182 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XkqapEmJ"; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.38 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:38 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:15 -0700 Message-Id: <1537970122-26443-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 10/17] riscv: Remove CSR read/write defines in encoding.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is no reason to keep two versions of CSR read/write defines in encoding.h. We already have one set of defines in csr.h, which is from Linux kernel, and let's drop the one in encoding.h. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- Changes in v3: None Changes in v2: - new patch to remove CSR read/write defines in encoding.h arch/riscv/include/asm/encoding.h | 50 ++++----------------------------------- 1 file changed, 4 insertions(+), 46 deletions(-) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index f237a72..9ea50ce 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -128,6 +128,7 @@ ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) #ifdef __riscv + #ifdef CONFIG_64BIT # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD @@ -141,53 +142,10 @@ # define MCAUSE_INT MCAUSE32_INT # define MCAUSE_CAUSE MCAUSE32_CAUSE #endif + #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, _val) ({ \ -typeof(_val) (val) = (_val); \ -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ -else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, _val) ({ unsigned long __tmp; \ -typeof(_val) (val) = (_val); \ -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ -else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, _bit) ({ unsigned long __tmp; \ -typeof(_bit) (bit) = (_bit); \ -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ -else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, _bit) ({ unsigned long __tmp; \ -typeof(_bit) (bit) = (_bit); \ -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ -else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) +#endif /* __riscv */ -#endif -#endif -#endif -#endif +#endif /* RISCV_CSR_ENCODING_H */ From patchwork Wed Sep 26 13:55:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975181 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.39 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:39 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:16 -0700 Message-Id: <1537970122-26443-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 11/17] riscv: bootm: Pass mhartid CSR value to kernel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" So far this is hardcoded to zero, and we should read the value from mhartid CSR and pass it to Linux kernel. Suggested-by: Lukas Auer Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- Changes in v3: None Changes in v2: - new patch to pass mhartid CSR value to kernel arch/riscv/lib/bootm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6893108..a7a9fb9 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -57,9 +58,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) printf("\nStarting kernel ...\n\n"); cleanup_before_linux(); - /* TODO: hardcode the hart id to zero for now */ + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - kernel(0, images->ft_addr); + kernel(csr_read(mhartid), images->ft_addr); /* does not return */ From patchwork Wed Sep 26 13:55:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975179 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y8zRh8OF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0Vz25myz9s4s for ; Thu, 27 Sep 2018 00:21:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E335CC21F0C; Wed, 26 Sep 2018 14:07:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AC882C21FBE; Wed, 26 Sep 2018 13:51:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C47A3C21FAB; Wed, 26 Sep 2018 13:51:06 +0000 (UTC) Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) by lists.denx.de (Postfix) with ESMTPS id 0D647C21F38 for ; Wed, 26 Sep 2018 13:50:43 +0000 (UTC) Received: by mail-pf1-f180.google.com with SMTP id j8-v6so13478682pff.6 for ; Wed, 26 Sep 2018 06:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=b4K4WqQHXpK6i9Lh5CNrUfAc7kcKHi4Ki9XJdACVf3I=; b=Y8zRh8OFhp8QMba3VRpbJ6pdbKnYW/rfHs4v37pejSoWwHbYIJwiB26ge7+lDwnaE7 XldHFxttsbI4vbDJuPMf0sqOGiRoo1byVUJLMj6kiBxgxL58xOoo9OmYsIJ4DX6mZWA6 LhmwnxXF5hxvfJx1b+ofaoHdOgiVgjIy5FIJ4zM2MxW+q6qUq9LX6/574bRiEDHnCJsU 3BdXld3ABJHv783SViy5jShNFk7LGyy0nciyAPIz3YNN8zTFkoziFCQgdfmd2ZHBrooE gYrgtav1o1zb0IWefhH6sPe6/E1amZ+rFHwFAxD17P03N/n55R7nU+/9ehN4afN3jgl4 dPEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=b4K4WqQHXpK6i9Lh5CNrUfAc7kcKHi4Ki9XJdACVf3I=; b=DcUJPDMVOtMxCV11t5ORthW041HQb8nt72M120SbcyYEzLCXztn3RpQ31Wjr5awsgE JuJsIdXWbRtnEKRfOusf154UZagrrAJ5oqju3F5z63onxiao9gqrgRiS0jCc9v2Oy3dL x3nel1vpVC5sMTrBvHlL2VWXo4UDubvJUbEVICQs76B02mv+eg3s/LWyNoCKfr7XxRGu LhtjIk2mbV87Wotma4B3DAMKbE3fb9Q8JDY/0IjehFW7dcFM9nD89IuxBTkrOA9gP8DX 1GafSg5aS5LRU0N8Z1vixVHnsHw02HiaNnjQpZxylsdD1qBi7LWyCZE33cBximKUwjnM d/HA== X-Gm-Message-State: ABuFfoh61PBXUO1HuoYpZ6XD3+Kjo2N+dGnsVI0PV0Q9+1EOGvwjhmyN TwL5IpvhToUdtJEz/SY3Ks0= X-Google-Smtp-Source: ACcGV61EPS6/YbUOWcYIkgV61V299VjkJGSiAfVp5JXeV6fdld6WRX2DU+1c8VzPay1MnsFKw5AxoQ== X-Received: by 2002:a63:2906:: with SMTP id p6-v6mr5843305pgp.204.1537969841714; Wed, 26 Sep 2018 06:50:41 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.40 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:40 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:17 -0700 Message-Id: <1537970122-26443-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 12/17] riscv: Make start.S available for all targets X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/Makefile | 2 +- arch/riscv/cpu/Makefile | 2 ++ arch/riscv/cpu/ax25/Makefile | 2 -- arch/riscv/cpu/{ax25 => }/start.S | 0 arch/riscv/cpu/u-boot.lds | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename arch/riscv/cpu/{ax25 => }/start.S (100%) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index af432e1..8fb6a88 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2017 Andes Technology Corporation. # Rick Chen, Andes Technology Corporation -head-y := arch/riscv/cpu/$(CPU)/start.o +head-y := arch/riscv/cpu/start.o libs-y += arch/riscv/cpu/ libs-y += arch/riscv/cpu/$(CPU)/ diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile index 63de163..2cc6757 100644 --- a/arch/riscv/cpu/Makefile +++ b/arch/riscv/cpu/Makefile @@ -2,4 +2,6 @@ # # Copyright (C) 2018, Bin Meng +extra-y = start.o + obj-y += cpu.o diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index c3f164c..2ab0342 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -3,6 +3,4 @@ # Copyright (C) 2017 Andes Technology Corporation # Rick Chen, Andes Technology Corporation -extra-y = start.o - obj-y := cpu.o diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/start.S similarity index 100% rename from arch/riscv/cpu/ax25/start.S rename to arch/riscv/cpu/start.S diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index f414473..11bc4a7 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -11,7 +11,7 @@ SECTIONS { . = ALIGN(4); .text : { - arch/riscv/cpu/ax25/start.o (.text) + arch/riscv/cpu/start.o (.text) } /* This needs to come before *(.text*) */ From patchwork Wed Sep 26 13:55:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975185 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EImfvjaE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0Xs0mPkz9s4Z for ; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.41 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:42 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:18 -0700 Message-Id: <1537970122-26443-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 13/17] riscv: ae350: Clean up mixed tabs and spaces in the dts X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There are quite a lot of mixed tabs and spaces in the ae350.dts. Clean them up. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/dts/ae350.dts | 177 ++++++++++++++++++++++++----------------------- 1 file changed, 90 insertions(+), 87 deletions(-) diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts index 2927e41..4717ae8 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350.dts @@ -1,144 +1,147 @@ /dts-v1/; / { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,ax25"; - model = "andestech,ax25"; + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; aliases { uart0 = &serial0; spi0 = &spi; - } ; + }; chosen { bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; stdout-path = "uart0:38400n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <10000000>; - CPU0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv39"; - clock-frequency = <60000000>; - CPU0_intc: interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; memory@0 { device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; + reg = <0x0 0x00000000 0x0 0x40000000>; }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,riscv-ae350-soc"; - ranges; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,riscv-ae350-soc"; + ranges; }; - plmt0@e6000000 { - compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7>; - reg = <0x0 0xe6000000 0x0 0x100000>; - }; + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; + }; - plic0: interrupt-controller@e4000000 { - compatible = "riscv,plic0"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe4000000 0x0 0x2000000>; - riscv,ndev=<31>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe4000000 0x0 0x2000000>; + riscv,ndev=<31>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; }; - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; - #address-cells = <2>; - #interrupt-cells = <2>; + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <2>; + #interrupt-cells = <2>; interrupt-controller; - reg = <0x0 0xe6400000 0x0 0x400000>; - riscv,ndev=<1>; - interrupts-extended = <&CPU0_intc 3>; - }; + reg = <0x0 0xe6400000 0x0 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0x0 0xf0400000 0x0 0x1000>; - clock-frequency = <40000000>; - interrupts = <3 4>; - interrupt-parent = <&plic0>; + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0x0 0xf0400000 0x0 0x1000>; + clock-frequency = <40000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; }; serial0: serial@f0300000 { compatible = "andestech,uart16550", "ns16550a"; - reg = <0x0 0xf0300000 0x0 0x1000>; - interrupts = <9 4>; + reg = <0x0 0xf0300000 0x0 0x1000>; + interrupts = <9 4>; clock-frequency = <19660800>; reg-shift = <2>; reg-offset = <32>; no-loopback-test = <1>; - interrupt-parent = <&plic0>; + interrupt-parent = <&plic0>; }; mac0: mac@e0100000 { compatible = "andestech,atmac100"; - reg = <0x0 0xe0100000 0x0 0x1000>; - interrupts = <19 4>; - interrupt-parent = <&plic0>; + reg = <0x0 0xe0100000 0x0 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; }; mmc0: mmc@f0e00000 { - compatible = "andestech,atfsdc010"; + compatible = "andestech,atfsdc010"; max-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; + clock-freq-min-max = <400000 100000000>; fifo-depth = <0x10>; - reg = <0x0 0xf0e00000 0x0 0x1000>; - interrupts = <18 4>; + reg = <0x0 0xf0e00000 0x0 0x1000>; + interrupts = <18 4>; cap-sd-highspeed; - interrupt-parent = <&plic0>; + interrupt-parent = <&plic0>; }; - smc0: smc@e0400000 { - compatible = "andestech,atfsmc020"; - reg = <0x0 0xe0400000 0x0 0x1000>; - }; + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0x0 0xe0400000 0x0 0x1000>; + }; - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x88000000 0x0 0x1000>; - bank-width = <2>; - device-width = <1>; - }; + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x88000000 0x0 0x1000>; + bank-width = <2>; + device-width = <1>; + }; spi: spi@f0b00000 { compatible = "andestech,atcspi200"; - reg = <0x0 0xf0b00000 0x0 0x1000>; + reg = <0x0 0xf0b00000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; clocks = <&spiclk>; interrupts = <3 4>; - interrupt-parent = <&plic0>; - flash@0 { + interrupt-parent = <&plic0>; + + flash@0 { compatible = "spi-flash"; spi-max-frequency = <50000000>; reg = <0>; From patchwork Wed Sep 26 13:55:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975168 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.42 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:43 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:19 -0700 Message-Id: <1537970122-26443-15-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 14/17] riscv: kconfig: Select DM and OF_CONTROL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RISC-V is a pretty new architecture and should support DM and OF_CONTROL by default. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/Kconfig | 3 +++ configs/ax25-ae350_defconfig | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index cd424fd..e62c3cb 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -62,6 +62,9 @@ config PPC config RISCV bool "RISC-V architecture" select SUPPORT_OF_CONTROL + select OF_CONTROL + select DM + imply CMD_DM config SANDBOX bool "Sandbox" diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index d64f078..ebcc52e 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -15,12 +15,10 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="ae350" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MMC=y CONFIG_DM_MMC=y From patchwork Wed Sep 26 13:55:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975169 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KmLKPYtU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0NP1cwCz9s5c for ; Thu, 27 Sep 2018 00:16:03 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B1258C21E44; Wed, 26 Sep 2018 14:09:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DD263C21FD0; Wed, 26 Sep 2018 13:51:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B8BFAC21FD5; Wed, 26 Sep 2018 13:51:13 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id 88F05C21E77 for ; Wed, 26 Sep 2018 13:50:46 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id az3-v6so534045plb.4 for ; Wed, 26 Sep 2018 06:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=8JaGCorwX+Tgdf6x3qTFu6kXcJSF0O5O3KFNNWxi8mI=; b=KmLKPYtUpXlDXO43u+YlzvhpWwqmJ5u1o6xnJcECs3/qzobY6N9WIt0hus+bgERRXP IDWLbPoW8n9NoXgNaGs05sYvBqTJmf4K7YKpSOMRxzZms3Wm8i2FFtnDI3evyhIOEFUO In2uXSUAcKu68wq7oc0mF2ACpqCkoemIGahukycsxk2zN+IgOSk0hKJ3mHB8CjBxSmCq jJkndmIdDBUwqg6RWbW/eCiwMhatM2WwgI0vt20aoextSPVkUxJ8VBSKJG1615rYFe+L onurIPAAItt6eJ8sT+VBWW2szv0GPeOURikuKigI8pSTXX8y2sgy295IrqiCZLTE3y4o RIHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8JaGCorwX+Tgdf6x3qTFu6kXcJSF0O5O3KFNNWxi8mI=; b=k2dpkMEtiOI1TWk20vNK6re1hSa5mW567ut9AQ7VTZ20QoRzxl2PhdzVmTGXonIvPO 1HGvxCGGx/72gnyq1RHGehEdPATG25kYGkFOktyfNu33EHTKavD10ei9qmvUopPdCe1s vdjP5QLRwzzsI5A5fjy9nz8+kCHySHYGKxsy75hoMSXm0/mZm7QLIbco5JgjEZtzU0nt PZjnGdz2HAYCxZXHMmDhPgleagu2R//YBen2iHhhu39EQcO9YnTyRGYV4Q4xHSQnhuEm ANoUUoahwQIIZUoR3bdQE+ckkP0Mzv1heksNZONrrq+0WB1k011uPjJ8IXHgzOZMIGKS bdDA== X-Gm-Message-State: ABuFfogOZWsH7EY+FlUg1WIDCqjmRf990I3K5ytANUIVsC+GqGZtqANE CFkCjkqoJPUnDjf4iU+7B/o= X-Google-Smtp-Source: ACcGV60afAPniq5JG0pBGA6j8HPMa49AtHZ0vVMfA7dnicvhOft0wpj3q5q2rXFb7/Cx0nqtttKTNg== X-Received: by 2002:a17:902:5ac9:: with SMTP id g9-v6mr6269780plm.311.1537969845199; Wed, 26 Sep 2018 06:50:45 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.44 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:44 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:20 -0700 Message-Id: <1537970122-26443-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 15/17] riscv: kconfig: Imply DM support for some common drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This implies DM support for some common drivers that are used on RISC-V. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - new patch to imply DM support for some common drivers Changes in v2: None arch/Kconfig | 9 +++++++++ configs/ax25-ae350_defconfig | 8 -------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index e62c3cb..ce183fa 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -64,6 +64,15 @@ config RISCV select SUPPORT_OF_CONTROL select OF_CONTROL select DM + imply DM_SERIAL + imply DM_ETH + imply DM_MMC + imply DM_SPI + imply DM_SPI_FLASH + imply BLK + imply CLK + imply MTD + imply TIMER imply CMD_DM config SANDBOX diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index ebcc52e..614ef15 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -19,24 +19,16 @@ CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="ae350" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y CONFIG_MMC=y -CONFIG_DM_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y -CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DM_ETH=y CONFIG_FTMAC100=y CONFIG_BAUDRATE=38400 -CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ATCSPI200_SPI=y -CONFIG_TIMER=y CONFIG_ATCPIT100_TIMER=y From patchwork Wed Sep 26 13:55:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975170 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HkYhAzoR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0Q63X0Yz9s4s for ; Thu, 27 Sep 2018 00:17:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 27EE5C21E1D; Wed, 26 Sep 2018 14:09:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EF593C21FEE; Wed, 26 Sep 2018 13:51:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E017AC21FDE; Wed, 26 Sep 2018 13:51:13 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id 9676EC21EC5 for ; Wed, 26 Sep 2018 13:50:48 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id s17-v6so9983215plp.7 for ; Wed, 26 Sep 2018 06:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=ZlTDE5r8f07uRobj2+YEVf7ioBlMrJiSkYJnfWUmzM4=; b=HkYhAzoRMtICtwMCxt6isy38Uz+PAlzQ+kqeTPbGRQvSKMLkAujMsN9adOUxD/pjzb Brc4NAxC68Rl6BVEMws+CryE57rp3TKXxE8s0+96T9CinoEXceKyvJ/PXuxVevXSW1w3 rTQlkqI723L5CqJ8e/jQsoGJkIx35XKrAtphNuNzmIDpLVqxx/TNAS31f88ufWU4R6fv xmbcLI2FDHAIm0Cgl77EVoDmpdRxrcdEP0VKauUgjRhkv3CGWqSIL0YRcMwpUmkbEAcw mr2ccaJCoAYXF8AM1pt5wSYH0cNSMmKhLsOCCDYUZF7e+SgX8pGh+hO+u/SZhEpVaXPE GB4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=ZlTDE5r8f07uRobj2+YEVf7ioBlMrJiSkYJnfWUmzM4=; b=JTiwdGp8vxwn7Qk8kdDBPU6tEO1JN5dE8CD8FRZODsXt+FMYJyiPWzd3kKoxOm/UyP USy75ETPeU8jLD4UMI9tKO28qJEnu3Dxh/Zdv1V+WHH0T/7vJ7YREk236o661++PdxBZ WJsPP589VN+FK1gi9WLichJD7ZU6z/b7WS6XeM9pM9cvLdPqnwlfQr2KiLK+DQl3LlD2 E6u8z+hfVwxcSjCyyZr8gFGBXigXfayVnFNM055pZWr0mzgDPlwaSMYKyGTNcoXhWY2l T7aEKWXmmeFE6YKksUE6qpmbI4vJiqdyZY2u2suWa+75xgLktkKhX6AZE/TKT6i83p6H UbDQ== X-Gm-Message-State: ABuFfoj4w0wwSvcISfEzBh6LqfyFyHUznmZZ7wcayh0Fns0k8NM0z5iK lCeJJAnlYhebisHS2YMr1AYf43aE X-Google-Smtp-Source: ACcGV61ak9HIraqiYn4p0cCfUakfD5ceAwBnAz3yNOStx+otL+sqq8fIlMCyJcdJmGoFNeaaF3N0sA== X-Received: by 2002:a17:902:167:: with SMTP id 94-v6mr6288298plb.142.1537969847062; Wed, 26 Sep 2018 06:50:47 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.45 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:45 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:21 -0700 Message-Id: <1537970122-26443-17-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 16/17] riscv: Add QEMU virt board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/Kconfig | 4 +++ arch/riscv/cpu/qemu/Makefile | 6 +++++ arch/riscv/cpu/qemu/cpu.c | 29 +++++++++++++++++++++ arch/riscv/cpu/qemu/dram.c | 17 ++++++++++++ board/emulation/qemu-riscv/Kconfig | 22 ++++++++++++++++ board/emulation/qemu-riscv/MAINTAINERS | 7 +++++ board/emulation/qemu-riscv/Makefile | 5 ++++ board/emulation/qemu-riscv/qemu-riscv.c | 23 +++++++++++++++++ configs/qemu-riscv32_defconfig | 6 +++++ configs/qemu-riscv64_defconfig | 7 +++++ doc/README.qemu-riscv | 46 +++++++++++++++++++++++++++++++++ include/configs/qemu-riscv.h | 21 +++++++++++++++ 12 files changed, 193 insertions(+) create mode 100644 arch/riscv/cpu/qemu/Makefile create mode 100644 arch/riscv/cpu/qemu/cpu.c create mode 100644 arch/riscv/cpu/qemu/dram.c create mode 100644 board/emulation/qemu-riscv/Kconfig create mode 100644 board/emulation/qemu-riscv/MAINTAINERS create mode 100644 board/emulation/qemu-riscv/Makefile create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c create mode 100644 configs/qemu-riscv32_defconfig create mode 100644 configs/qemu-riscv64_defconfig create mode 100644 doc/README.qemu-riscv create mode 100644 include/configs/qemu-riscv.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 49f87de..168ca3d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,9 +11,13 @@ choice config TARGET_AX25_AE350 bool "Support ax25-ae350" +config TARGET_QEMU_VIRT + bool "Support QEMU Virt Board" + endchoice source "board/AndesTech/ax25-ae350/Kconfig" +source "board/emulation/qemu-riscv/Kconfig" choice prompt "CPU selection" diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/qemu/Makefile new file mode 100644 index 0000000..258e462 --- /dev/null +++ b/arch/riscv/cpu/qemu/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c new file mode 100644 index 0000000..a064639 --- /dev/null +++ b/arch/riscv/cpu/qemu/cpu.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("reset unsupported yet\n"); + + return 0; +} diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/qemu/dram.c new file mode 100644 index 0000000..84d87d2 --- /dev/null +++ b/arch/riscv/cpu/qemu/dram.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig new file mode 100644 index 0000000..af23363 --- /dev/null +++ b/board/emulation/qemu-riscv/Kconfig @@ -0,0 +1,22 @@ +if TARGET_QEMU_VIRT + +config SYS_BOARD + default "qemu-riscv" + +config SYS_VENDOR + default "emulation" + +config SYS_CPU + default "qemu" + +config SYS_CONFIG_NAME + default "qemu-riscv" + +config SYS_TEXT_BASE + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + imply SYS_NS16550 + +endif diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS new file mode 100644 index 0000000..3c6eb4f --- /dev/null +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -0,0 +1,7 @@ +QEMU RISC-V 'VIRT' BOARD +M: Bin Meng +S: Maintained +F: board/emulation/qemu-riscv/ +F: include/configs/qemu-riscv.h +F: configs/qemu-riscv32_defconfig +F: configs/qemu-riscv64_defconfig diff --git a/board/emulation/qemu-riscv/Makefile b/board/emulation/qemu-riscv/Makefile new file mode 100644 index 0000000..3f29b90 --- /dev/null +++ b/board/emulation/qemu-riscv/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +obj-y += qemu-riscv.o diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c new file mode 100644 index 0000000..041e716 --- /dev/null +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +#define MROM_FDT_ADDR 0x1020 + +int board_init(void) +{ + return 0; +} + +void *board_fdt_blob_setup(void) +{ + /* + * QEMU loads a generated DTB for us immediately + * after the reset vectors in the MROM + */ + return (void *)MROM_FDT_ADDR; +} diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig new file mode 100644 index 0000000..ff1fb1f --- /dev/null +++ b/configs/qemu-riscv32_defconfig @@ -0,0 +1,6 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_OF_BOARD=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig new file mode 100644 index 0000000..d6c1a5d --- /dev/null +++ b/configs/qemu-riscv64_defconfig @@ -0,0 +1,7 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_CPU_RISCV_64=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_OF_BOARD=y diff --git a/doc/README.qemu-riscv b/doc/README.qemu-riscv new file mode 100644 index 0000000..e2e4804 --- /dev/null +++ b/doc/README.qemu-riscv @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +U-Boot on QEMU's 'virt' machine on RISC-V +========================================= + +QEMU for RISC-V supports a special 'virt' machine designed for emulation and +virtualization purposes. This document describes how to run U-Boot under it. +Both 32-bit 64-bit targets are supported. + +The QEMU virt machine models a generic RISC-V virtual machine with support for +the VirtIO standard networking and block storage devices. It has CLINT, PLIC, +16550A UART devices in addition to VirtIO and it also uses device-tree to pass +configuration information to guest software. It implements RISC-V privileged +architecture spec v1.10. + +Building U-Boot +--------------- +Set the CROSS_COMPILE environment variable as usual, and run: + +- For 32-bit RISC-V: + make qemu-riscv32_defconfig + make + +- For 64-bit RISC-V: + make qemu-riscv64_defconfig + make + +Running U-Boot +-------------- +The minimal QEMU command line to get U-Boot up and running is: + +- For 32-bit RISC-V: + qemu-system-riscv32 -nographic -machine virt -kernel u-boot + +- For 64-bit RISC-V: + qemu-system-riscv64 -nographic -machine virt -kernel u-boot + +The commands above create targets with 128MiB memory by default. +A freely configurable amount of RAM can be created via the '-m' +parameter. For example, '-m 2G' creates 2GiB memory for the target, +and the memory node in the embedded DTB created by QEMU reflects +the new setting. + +These have been tested in QEMU 3.0.0. diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h new file mode 100644 index 0000000..d279c23 --- /dev/null +++ b/include/configs/qemu-riscv.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +/* Environment options */ +#define CONFIG_ENV_SIZE SZ_4K + +#endif /* __CONFIG_H */ From patchwork Wed Sep 26 13:55:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 975180 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="refdrYUN"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42L0WN5f8gz9s5c for ; Thu, 27 Sep 2018 00:22:08 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 85AB1C21F32; Wed, 26 Sep 2018 14:09:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DE48EC21FDF; Wed, 26 Sep 2018 13:51:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 83657C21FCD; Wed, 26 Sep 2018 13:51:14 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id B45A1C21F94 for ; Wed, 26 Sep 2018 13:50:49 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id b97-v6so10015311plb.0 for ; Wed, 26 Sep 2018 06:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=CeGO5AslEYAkbwRMWG+D5sAd/9e31VzxHxVFw5zE+sk=; b=refdrYUNwNXfzDQqqb1oinbAPSHFbdQvGeIHxmgsCd2UPj91mCSYeey0wSiegUvpZQ ZjM2/jxzY4M1cwpDIJ80HeF5Fw4xJUOUchT86dgQ0wma6jX+9p15erY3xHFjc54XWEjb nY8gpK+pU+A9D6up/JGIb4OQ2Lyc6Pj7WAuykxIcROKDElVT45LyAICaLU+29746HxyX q6g0Sdv6Shk4a3YGom1GwG0TdYpQl4n1LF/icv16Q/ARTpUFXymC7F0NV6gIpBSozTMb BUzzyavwVcNIVOamSuYSZ4gU1M/UcfFcPQwzrVUobz6tjYE/ZVBMOJq/N8e50jL2d2LQ mIUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=CeGO5AslEYAkbwRMWG+D5sAd/9e31VzxHxVFw5zE+sk=; b=teXfDfweGe3w8UMc1djaRYBiJUfYNkv7YD39sKlU5FWoaKYpbpJytdZdqZan/Mg6LQ IkdUb2ZRTKJF5FKt2NdE2X7ksVC+gI55eH6874xD0fatTxc5bs3uetY0lagnE7B7yzTu IpdRN3m4FFGgSLNYudruhCMbdmm+8n3V8JiB5PgjxO07wd4pjioiaUDWrMWBtexuBtpf Bcwsk3ZFWkW9X5CnDFudHiXx9HaMpNKr9p/hiMcLuWdvapJZT3n8GWtAZaaCfJ2B/IxE RrSnYj1BnJT3jI35e4jvCNIZnuiAaLK69FGqO5R/YOfBf+zlsxf9Csi/P9lC2ATyJcqD G5Ag== X-Gm-Message-State: ABuFfojUCyEgHlZjZ+rifaGdXdVizJCYCZTLmtZ6kCmO+QFRBxg/2xvX NyXsWXssMrOkYmedXFJdalQ= X-Google-Smtp-Source: ACcGV63M2VxMkFD30qDlpwrLjdDsGHOJYK4koO2hNdHd9bM5UBjwEl3lS8AP/9ZRKkIz5cRFQMYYmA== X-Received: by 2002:a17:902:f203:: with SMTP id gn3mr4640845plb.162.1537969848346; Wed, 26 Sep 2018 06:50:48 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id t69-v6sm10849253pgd.43.2018.09.26.06.50.47 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 06:50:47 -0700 (PDT) From: Bin Meng To: Rick Chen , U-Boot Mailing List , Lukas Auer Date: Wed, 26 Sep 2018 06:55:22 -0700 Message-Id: <1537970122-26443-18-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> References: <1537970122-26443-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 17/17] riscv: Move do_reset() to a common place X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - reword the reset message a little, and call hang() in the end Changes in v2: - new patch to move do_reset() to a common place arch/riscv/cpu/ax25/cpu.c | 9 --------- arch/riscv/cpu/qemu/cpu.c | 8 -------- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/reset.c | 17 +++++++++++++++++ 4 files changed, 18 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/lib/reset.c diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index ab05b57..fddcc15 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -6,9 +6,6 @@ /* CPU specific code */ #include -#include -#include -#include /* * cleanup_before_linux() is called just before we call linux @@ -24,9 +21,3 @@ int cleanup_before_linux(void) return 0; } - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - disable_interrupts(); - panic("ax25-ae350 wdt not support yet.\n"); -} diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index a064639..6c7a327 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/qemu/cpu.c @@ -4,7 +4,6 @@ */ #include -#include /* * cleanup_before_linux() is called just before we call linux @@ -20,10 +19,3 @@ int cleanup_before_linux(void) return 0; } - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("reset unsupported yet\n"); - - return 0; -} diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index cc562f9..b58db89 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-y += interrupts.o +obj-y += reset.o obj-y += setjmp.o # For building EFI apps diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c new file mode 100644 index 0000000..a6aa8e2 --- /dev/null +++ b/arch/riscv/lib/reset.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("resetting ...\n"); + + printf("reset unsupported yet\n"); + hang(); + + return 0; +}