From patchwork Fri Sep 21 16:19:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzRH3rkLz9sCc for ; Sat, 22 Sep 2018 02:23:06 +1000 (AEST) Received: from localhost ([::1]:56430 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OCu-0005aU-Dk for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:23:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OAA-0003wS-Js for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OA6-0003l4-7I for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:14 -0400 Received: from 15.mo3.mail-out.ovh.net ([87.98.150.177]:37775) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OA5-0003fC-U9 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:10 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.24]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id E2FFB1D75EB for ; Fri, 21 Sep 2018 18:20:06 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 758C752008E; Fri, 21 Sep 2018 18:19:57 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:29 +0200 Message-Id: <20180921161939.822-2-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1888697097958689600 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.150.177 Subject: [Qemu-devel] [PATCH v2 01/11] aspeed/timer: fix compile breakage with clang 3.4.2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16: /home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error: redefinition of typedef 'AspeedSCUState' is a C11 feature [-Werror,-Wtypedef-redefinition] } AspeedSCUState; ^ /home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note: previous definition is here typedef struct AspeedSCUState AspeedSCUState; Reported-by: Thomas Huth Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- include/hw/timer/aspeed_timer.h | 3 +-- hw/timer/aspeed_timer.c | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h index 040a08873432..1fb949e16710 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -23,8 +23,7 @@ #define ASPEED_TIMER_H #include "qemu/timer.h" - -typedef struct AspeedSCUState AspeedSCUState; +#include "hw/misc/aspeed_scu.h" #define ASPEED_TIMER(obj) \ OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER); diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 5e3f51b66b43..54b400b94aa9 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -13,7 +13,6 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/timer/aspeed_timer.h" -#include "hw/misc/aspeed_scu.h" #include "qemu-common.h" #include "qemu/bitops.h" #include "qemu/timer.h" From patchwork Fri Sep 21 16:19:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzTS58prz9s7T for ; Sat, 22 Sep 2018 02:25:00 +1000 (AEST) Received: from localhost ([::1]:56439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OEj-0007Fj-Sc for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:24:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OAL-000441-I0 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OAI-0003tc-5f for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:25 -0400 Received: from 8.mo1.mail-out.ovh.net ([178.33.110.239]:42600) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OAG-0003os-7C for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:21 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.143]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 30B801363DD for ; Fri, 21 Sep 2018 18:20:16 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id C9DA65200AE; Fri, 21 Sep 2018 18:20:06 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:30 +0200 Message-Id: <20180921161939.822-3-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1891511844664216384 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.110.239 Subject: [Qemu-devel] [PATCH v2 02/11] hw/arm/aspeed: change the FMC flash model of the AST2500 evb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The AST2500 evb is shipped with a W25Q256 which has a non volatile bit to make the chip operate in 4 Byte address mode at power up. This should be an interesting feature to model as it will exercise a bit more the SMC controllers and MMIO execution at boot time. Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index bb9590f1aed1..f2d64e45511a 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -105,7 +105,7 @@ static const AspeedBoardConfig aspeed_boards[] = { [AST2500_EVB] = { .soc_name = "ast2500-a1", .hw_strap1 = AST2500_EVB_HW_STRAP1, - .fmc_model = "n25q256a", + .fmc_model = "w25q256", .spi_model = "mx25l25635e", .num_cs = 1, .i2c_init = ast2500_evb_i2c_init, From patchwork Fri Sep 21 16:19:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973305 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzP90RTDz9sCR for ; Sat, 22 Sep 2018 02:21:17 +1000 (AEST) Received: from localhost ([::1]:56421 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OB8-0004Bq-K6 for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:21:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OAQ-0004AC-Ak for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OAM-0003w0-VB for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:30 -0400 Received: from 5.mo69.mail-out.ovh.net ([46.105.43.105]:34244) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OAM-0003vS-Ly for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:26 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.163]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 920A72D88F for ; Fri, 21 Sep 2018 18:20:25 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 2EC6352008F; Fri, 21 Sep 2018 18:20:16 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:31 +0200 Message-Id: <20180921161939.822-4-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1894045122383350592 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.43.105 Subject: [Qemu-devel] [PATCH v2 03/11] hw/arm/aspeed: Add an Aspeed machine class X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The code looks better, it removes duplicated lines and it will ease the introduction of common properties for the Aspeed machines. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- include/hw/arm/aspeed.h | 46 +++++++++ hw/arm/aspeed.c | 212 +++++++++++++--------------------------- 2 files changed, 116 insertions(+), 142 deletions(-) create mode 100644 include/hw/arm/aspeed.h diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h new file mode 100644 index 000000000000..325c091d09e4 --- /dev/null +++ b/include/hw/arm/aspeed.h @@ -0,0 +1,46 @@ +/* + * Aspeed Machines + * + * Copyright 2018 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ +#ifndef ARM_ASPEED_H +#define ARM_ASPEED_H + +#include "hw/boards.h" + +typedef struct AspeedBoardState AspeedBoardState; + +typedef struct AspeedBoardConfig { + const char *name; + const char *desc; + const char *soc_name; + uint32_t hw_strap1; + const char *fmc_model; + const char *spi_model; + uint32_t num_cs; + void (*i2c_init)(AspeedBoardState *bmc); +} AspeedBoardConfig; + +#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") +#define ASPEED_MACHINE(obj) \ + OBJECT_CHECK(AspeedMachine, (obj), TYPE_ASPEED_MACHINE) + +typedef struct AspeedMachine { + MachineState parent_obj; +} AspeedMachine; + +#define ASPEED_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(AspeedMachineClass, (klass), TYPE_ASPEED_MACHINE) +#define ASPEED_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AspeedMachineClass, (obj), TYPE_ASPEED_MACHINE) + +typedef struct AspeedMachineClass { + MachineClass parent_obj; + const AspeedBoardConfig *board; +} AspeedMachineClass; + + +#endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index f2d64e45511a..6b33ecd5aa43 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -15,6 +15,7 @@ #include "cpu.h" #include "exec/address-spaces.h" #include "hw/arm/arm.h" +#include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/boards.h" #include "hw/i2c/smbus.h" @@ -34,22 +35,6 @@ typedef struct AspeedBoardState { MemoryRegion max_ram; } AspeedBoardState; -typedef struct AspeedBoardConfig { - const char *soc_name; - uint32_t hw_strap1; - const char *fmc_model; - const char *spi_model; - uint32_t num_cs; - void (*i2c_init)(AspeedBoardState *bmc); -} AspeedBoardConfig; - -enum { - PALMETTO_BMC, - AST2500_EVB, - ROMULUS_BMC, - WITHERSPOON_BMC, -}; - /* Palmetto hardware value: 0x120CE416 */ #define PALMETTO_BMC_HW_STRAP1 ( \ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ @@ -88,46 +73,6 @@ enum { /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 -static void palmetto_bmc_i2c_init(AspeedBoardState *bmc); -static void ast2500_evb_i2c_init(AspeedBoardState *bmc); -static void romulus_bmc_i2c_init(AspeedBoardState *bmc); -static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc); - -static const AspeedBoardConfig aspeed_boards[] = { - [PALMETTO_BMC] = { - .soc_name = "ast2400-a1", - .hw_strap1 = PALMETTO_BMC_HW_STRAP1, - .fmc_model = "n25q256a", - .spi_model = "mx25l25635e", - .num_cs = 1, - .i2c_init = palmetto_bmc_i2c_init, - }, - [AST2500_EVB] = { - .soc_name = "ast2500-a1", - .hw_strap1 = AST2500_EVB_HW_STRAP1, - .fmc_model = "w25q256", - .spi_model = "mx25l25635e", - .num_cs = 1, - .i2c_init = ast2500_evb_i2c_init, - }, - [ROMULUS_BMC] = { - .soc_name = "ast2500-a1", - .hw_strap1 = ROMULUS_BMC_HW_STRAP1, - .fmc_model = "n25q256a", - .spi_model = "mx66l1g45g", - .num_cs = 2, - .i2c_init = romulus_bmc_i2c_init, - }, - [WITHERSPOON_BMC] = { - .soc_name = "ast2500-a1", - .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, - .fmc_model = "mx25l25635e", - .spi_model = "mx66l1g45g", - .num_cs = 2, - .i2c_init = witherspoon_bmc_i2c_init, - }, -}; - /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -313,30 +258,6 @@ static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); } -static void palmetto_bmc_init(MachineState *machine) -{ - aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]); -} - -static void palmetto_bmc_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; - mc->init = palmetto_bmc_init; - mc->max_cpus = 1; - mc->no_sdcard = 1; - mc->no_floppy = 1; - mc->no_cdrom = 1; - mc->no_parallel = 1; -} - -static const TypeInfo palmetto_bmc_type = { - .name = MACHINE_TYPE_NAME("palmetto-bmc"), - .parent = TYPE_MACHINE, - .class_init = palmetto_bmc_class_init, -}; - static void ast2500_evb_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc = &bmc->soc; @@ -353,30 +274,6 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); } -static void ast2500_evb_init(MachineState *machine) -{ - aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]); -} - -static void ast2500_evb_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Aspeed AST2500 EVB (ARM1176)"; - mc->init = ast2500_evb_init; - mc->max_cpus = 1; - mc->no_sdcard = 1; - mc->no_floppy = 1; - mc->no_cdrom = 1; - mc->no_parallel = 1; -} - -static const TypeInfo ast2500_evb_type = { - .name = MACHINE_TYPE_NAME("ast2500-evb"), - .parent = TYPE_MACHINE, - .class_init = ast2500_evb_class_init, -}; - static void romulus_bmc_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc = &bmc->soc; @@ -386,30 +283,6 @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); } -static void romulus_bmc_init(MachineState *machine) -{ - aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]); -} - -static void romulus_bmc_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; - mc->init = romulus_bmc_init; - mc->max_cpus = 1; - mc->no_sdcard = 1; - mc->no_floppy = 1; - mc->no_cdrom = 1; - mc->no_parallel = 1; -} - -static const TypeInfo romulus_bmc_type = { - .name = MACHINE_TYPE_NAME("romulus-bmc"), - .parent = TYPE_MACHINE, - .class_init = romulus_bmc_class_init, -}; - static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc = &bmc->soc; @@ -433,36 +306,91 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 0x60); } -static void witherspoon_bmc_init(MachineState *machine) +static void aspeed_machine_init(MachineState *machine) { - aspeed_board_init(machine, &aspeed_boards[WITHERSPOON_BMC]); + AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); + + aspeed_board_init(machine, amc->board); } -static void witherspoon_bmc_class_init(ObjectClass *oc, void *data) +static void aspeed_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + const AspeedBoardConfig *board = data; - mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; - mc->init = witherspoon_bmc_init; + mc->desc = board->desc; + mc->init = aspeed_machine_init; mc->max_cpus = 1; mc->no_sdcard = 1; mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + amc->board = board; } -static const TypeInfo witherspoon_bmc_type = { - .name = MACHINE_TYPE_NAME("witherspoon-bmc"), +static const TypeInfo aspeed_machine_type = { + .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, - .class_init = witherspoon_bmc_class_init, + .instance_size = sizeof(AspeedMachine), + .class_size = sizeof(AspeedMachineClass), + .abstract = true, +}; + +static const AspeedBoardConfig aspeed_boards[] = { + { + .name = MACHINE_TYPE_NAME("palmetto-bmc"), + .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)", + .soc_name = "ast2400-a1", + .hw_strap1 = PALMETTO_BMC_HW_STRAP1, + .fmc_model = "n25q256a", + .spi_model = "mx25l25635e", + .num_cs = 1, + .i2c_init = palmetto_bmc_i2c_init, + }, { + .name = MACHINE_TYPE_NAME("ast2500-evb"), + .desc = "Aspeed AST2500 EVB (ARM1176)", + .soc_name = "ast2500-a1", + .hw_strap1 = AST2500_EVB_HW_STRAP1, + .fmc_model = "w25q256", + .spi_model = "mx25l25635e", + .num_cs = 1, + .i2c_init = ast2500_evb_i2c_init, + }, { + .name = MACHINE_TYPE_NAME("romulus-bmc"), + .desc = "OpenPOWER Romulus BMC (ARM1176)", + .soc_name = "ast2500-a1", + .hw_strap1 = ROMULUS_BMC_HW_STRAP1, + .fmc_model = "n25q256a", + .spi_model = "mx66l1g45g", + .num_cs = 2, + .i2c_init = romulus_bmc_i2c_init, + }, { + .name = MACHINE_TYPE_NAME("witherspoon-bmc"), + .desc = "OpenPOWER Witherspoon BMC (ARM1176)", + .soc_name = "ast2500-a1", + .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, + .fmc_model = "mx25l25635e", + .spi_model = "mx66l1g45g", + .num_cs = 2, + .i2c_init = witherspoon_bmc_i2c_init, + }, }; -static void aspeed_machine_init(void) +static void aspeed_machine_types(void) { - type_register_static(&palmetto_bmc_type); - type_register_static(&ast2500_evb_type); - type_register_static(&romulus_bmc_type); - type_register_static(&witherspoon_bmc_type); + int i; + + type_register_static(&aspeed_machine_type); + for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) { + TypeInfo ti = { + .name = aspeed_boards[i].name, + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_class_init, + .class_data = (void *)&aspeed_boards[i], + }; + type_register(&ti); + } } -type_init(aspeed_machine_init) +type_init(aspeed_machine_types) From patchwork Fri Sep 21 16:19:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzRT4pYFz9s7T for ; Sat, 22 Sep 2018 02:23:17 +1000 (AEST) Received: from localhost ([::1]:56433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OD5-0005fQ-8w for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:23:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OAa-0004CF-AB for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OAW-00043A-J0 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:40 -0400 Received: from 4.mo179.mail-out.ovh.net ([46.105.36.149]:34310) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OAW-00042j-A0 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:36 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.201]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 05B0A10003D for ; Fri, 21 Sep 2018 18:20:34 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 956395200B3; Fri, 21 Sep 2018 18:20:25 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:32 +0200 Message-Id: <20180921161939.822-5-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1896578393404181312 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.36.149 Subject: [Qemu-devel] [PATCH v2 04/11] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The overhead for the OpenBMC firmware images using the a custom U-Boot is around 2 seconds, which is fine, but with a U-Boot from mainline, it takes an extra 50 seconds or so to reach Linux. A quick survey on the number of reads performed on the flash memory region gives the following figures : OpenBMC U-Boot 922478 (~ 3.5 MBytes) Mainline U-Boot 20569977 (~ 80 MBytes) QEMU must be trashing the TCG TBs and reloading text very often. Some addresses are read more than 250.000 times. Until we find a solution to improve boot time, execution from MMIO is not activated by default. Setting this option also breaks migration compatibility. Signed-off-by: Cédric Le Goater Reviewed-by: Peter Maydell --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 44 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 325c091d09e4..b67f633ddbd1 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -30,6 +30,8 @@ typedef struct AspeedBoardConfig { typedef struct AspeedMachine { MachineState parent_obj; + + bool mmio_exec; } AspeedMachine; #define ASPEED_MACHINE_CLASS(klass) \ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6b33ecd5aa43..e7b87e355f12 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -216,11 +216,18 @@ static void aspeed_board_init(MachineState *machine, * SoC and 128MB for the AST2500 SoC, which is twice as big as * needed by the flash modules of the Aspeed machines. */ - memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", - fl->size, &error_abort); - memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, - boot_rom); - write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); + if (ASPEED_MACHINE(machine)->mmio_exec) { + memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + &fl->mmio, 0, fl->size); + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, + boot_rom); + } else { + memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + fl->size, &error_abort); + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, + boot_rom); + write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); + } } aspeed_board_binfo.kernel_filename = machine->kernel_filename; @@ -313,6 +320,30 @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_init(machine, amc->board); } +static bool aspeed_get_mmio_exec(Object *obj, Error **errp) +{ + return ASPEED_MACHINE(obj)->mmio_exec; +} + +static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) +{ + ASPEED_MACHINE(obj)->mmio_exec = value; +} + +static void aspeed_machine_instance_init(Object *obj) +{ + ASPEED_MACHINE(obj)->mmio_exec = false; +} + +static void aspeed_machine_class_props_init(ObjectClass *oc) +{ + object_class_property_add_bool(oc, "execute-in-place", + aspeed_get_mmio_exec, + aspeed_set_mmio_exec, &error_abort); + object_class_property_set_description(oc, "execute-in-place", + "boot directly from CE0 flash device", &error_abort); +} + static void aspeed_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -327,6 +358,8 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) mc->no_cdrom = 1; mc->no_parallel = 1; amc->board = board; + + aspeed_machine_class_props_init(oc); } static const TypeInfo aspeed_machine_type = { @@ -334,6 +367,7 @@ static const TypeInfo aspeed_machine_type = { .parent = TYPE_MACHINE, .instance_size = sizeof(AspeedMachine), .class_size = sizeof(AspeedMachineClass), + .instance_init = aspeed_machine_instance_init, .abstract = true, }; From patchwork Fri Sep 21 16:19:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973309 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzTr2Vkcz9s7T for ; Sat, 22 Sep 2018 02:25:20 +1000 (AEST) Received: from localhost ([::1]:56443 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OF3-0007P4-DD for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:25:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OAn-0004K4-LF for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OAf-0004BU-Qf for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:49 -0400 Received: from 2.mo3.mail-out.ovh.net ([46.105.75.36]:46289) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OAf-000480-IM for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:20:45 -0400 Received: from player799.ha.ovh.net (unknown [10.109.159.159]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 4C1151D723E for ; Fri, 21 Sep 2018 18:20:44 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id EA1AF5200AE; Fri, 21 Sep 2018 18:20:34 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:33 +0200 Message-Id: <20180921161939.822-6-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1899393145862589248 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.75.36 Subject: [Qemu-devel] [PATCH v2 05/11] aspeed/smc: fix some alignment issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- hw/ssi/aspeed_smc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index b29bfd3124a9..1270842dcf0c 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -388,8 +388,8 @@ static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%" - PRIx64 "\n", __func__, addr, size, data); + qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%" + PRIx64 "\n", __func__, addr, size, data); } static const MemoryRegionOps aspeed_smc_flash_default_ops = { @@ -529,7 +529,7 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) */ if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { - ssi_transfer(fl->controller->spi, 0xFF); + ssi_transfer(fl->controller->spi, 0xFF); } } } @@ -567,7 +567,7 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) } static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, - unsigned size) + unsigned size) { AspeedSMCFlash *fl = opaque; AspeedSMCState *s = fl->controller; From patchwork Fri Sep 21 16:19:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzmN1k9Dz9sCS for ; Sat, 22 Sep 2018 02:37:56 +1000 (AEST) Received: from localhost ([::1]:56481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3ORF-0002Vn-Rd for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:37:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQX-0002Rn-3s for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OAx-0004Mm-DA for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:08 -0400 Received: from 5.mo179.mail-out.ovh.net ([46.105.43.140]:40687) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OAw-0004Ia-RT for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:03 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.211]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 9D1411000E3 for ; Fri, 21 Sep 2018 18:20:53 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 4B1E9520093; Fri, 21 Sep 2018 18:20:44 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:34 +0200 Message-Id: <20180921161939.822-7-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1901926419541232448 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.43.140 Subject: [Qemu-devel] [PATCH v2 06/11] aspeed/smc: fix default read value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" 0xFFFFFFFF should be returned for non implemented registers. Also, the model should expose one control register per possible CS even if there is no flash device attached. When testing the validity of the register number in the read operation, replace 's->num_cs' by 'ctrl->max_slaves' which represents the maximum number of flash devices a controller can handle. Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 1270842dcf0c..6045ca11b969 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -665,12 +665,12 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == s->r_ce_ctrl || addr == R_INTR_CTRL || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) { + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { return s->regs[addr]; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", __func__, addr); - return 0; + return -1; } } From patchwork Fri Sep 21 16:19:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Gztt5jgYz9s8F for ; Sat, 22 Sep 2018 02:43:34 +1000 (AEST) Received: from localhost ([::1]:56524 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OWi-00080s-Ge for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:43:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42350) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQp-0001yx-EZ for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OB3-0004Q7-1e for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:13 -0400 Received: from 10.mo179.mail-out.ovh.net ([46.105.79.46]:45627) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OB0-0004MM-Dj for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:06 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.146]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id F4007100050 for ; Fri, 21 Sep 2018 18:21:02 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 9FF5A520093; Fri, 21 Sep 2018 18:20:53 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:35 +0200 Message-Id: <20180921161939.822-8-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1904459693030738752 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.79.46 Subject: [Qemu-devel] [PATCH v2 07/11] aspeed/smc: add a 'sdram_base' and 'max-ram-size' properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The setting of the DRAM address of the DMA transaction depends on the DRAM base address and the maximum DRAM size of the SoC. Let's add a couple of properties to give this information to the SMC controller model. Also, move the SDRAM Memory controller realization before the other controllers which need it. Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 4 ++++ hw/arm/aspeed_soc.c | 28 +++++++++++++++++++--------- hw/ssi/aspeed_smc.c | 2 ++ 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 1f557313fa93..d7090bb5e9b7 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -97,6 +97,10 @@ typedef struct AspeedSMCState { uint8_t r_timings; uint8_t conf_enable_w0; + /* for DMA support */ + uint64_t sdram_base; + uint64_t max_ram_size; + AspeedSMCFlash *flashes; } AspeedSMCState; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 2cbacb4430bb..bbc05d172fe1 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -209,6 +209,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); + /* SDMC - SDRAM Memory Controller */ + object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); + /* VIC */ object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); if (err) { @@ -252,7 +260,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->vic), 12)); /* FMC, The number of CS is set at the board level */ - object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); + object_property_set_int(OBJECT(&s->fmc), sc->info->sdram_base, "sdram-base", + &err); + object_property_set_int(OBJECT(&s->fmc), s->sdmc.max_ram_size, + "max-ram-size", &local_err); + error_propagate(&err, local_err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err); + error_propagate(&err, local_err); if (err) { error_propagate(errp, err); return; @@ -278,14 +296,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) s->spi[i].ctrl->flash_window_base); } - /* SDMC - SDRAM Memory Controller */ - object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); - /* Watch dog */ for (i = 0; i < sc->info->wdts_num; i++) { object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 6045ca11b969..500de6d16d09 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -800,6 +800,8 @@ static const VMStateDescription vmstate_aspeed_smc = { static Property aspeed_smc_properties[] = { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), + DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), + DEFINE_PROP_UINT64("max-ram-size", AspeedSMCState, max_ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; From patchwork Fri Sep 21 16:19:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Gzp74XlTz9sCV for ; Sat, 22 Sep 2018 02:39:27 +1000 (AEST) Received: from localhost ([::1]:56491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OSj-0004Om-1t for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:39:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQn-0002dN-St for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OBA-0004Vs-Gy for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:19 -0400 Received: from 3.mo173.mail-out.ovh.net ([46.105.34.1]:60827) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OB9-0004Sg-F1 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:16 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.109]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 5903EDA7C6 for ; Fri, 21 Sep 2018 18:21:12 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 036D3520093; Fri, 21 Sep 2018 18:21:02 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:36 +0200 Message-Id: <20180921161939.822-9-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1907274444585929536 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.34.1 Subject: [Qemu-devel] [PATCH v2 08/11] aspeed/smc: add support for DMAs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces a custom address space for DMAs populated with the required regions : an alias region on the AHB window for the flash devices and another alias on the SDRAM. Our primary need is to support the checksum calculation mode and the model only implements synchronous DMA accesses. Something to improve in the future. Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 2 + hw/ssi/aspeed_smc.c | 227 +++++++++++++++++++++++++++++++++++- 2 files changed, 223 insertions(+), 6 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index d7090bb5e9b7..b8b2dfbec280 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -100,6 +100,8 @@ typedef struct AspeedSMCState { /* for DMA support */ uint64_t sdram_base; uint64_t max_ram_size; + MemoryRegion dma_mr; + AddressSpace dma_as; AspeedSMCFlash *flashes; } AspeedSMCState; diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 500de6d16d09..625c29ba4ad2 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -23,10 +23,12 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/sysbus.h" #include "sysemu/sysemu.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "exec/address-spaces.h" #include "hw/ssi/aspeed_smc.h" @@ -109,8 +111,8 @@ #define DMA_CTRL_FREQ_SHIFT 4 #define DMA_CTRL_MODE (1 << 3) #define DMA_CTRL_CKSUM (1 << 2) -#define DMA_CTRL_DIR (1 << 1) -#define DMA_CTRL_EN (1 << 0) +#define DMA_CTRL_WRITE (1 << 1) +#define DMA_CTRL_ENABLE (1 << 0) /* DMA Flash Side Address */ #define R_DMA_FLASH_ADDR (0x84 / 4) @@ -142,6 +144,21 @@ #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000 +/* + * DMA DRAM addresses should be 4 bytes aligned and the valid address + * range is the full address space of the SoC + * + * DMA flash addresses should be 4 bytes aligned and the valid address + * range is 0x20000000 - 0x2FFFFFFF. + * + * DMA length is from 4 bytes to 32MB + * 0: 4 bytes + * 0x7FFFFF: 32M bytes + */ +#define DMA_DRAM_MASK(s) ((s)->max_ram_size - 4) +#define DMA_FLASH_MASK 0x0FFFFFFC +#define DMA_LENGTH_MASK 0x01FFFFFC + /* Flash opcodes. */ #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ @@ -625,9 +642,6 @@ static void aspeed_smc_reset(DeviceState *d) memset(s->regs, 0, sizeof s->regs); - /* Pretend DMA is done (u-boot initialization) */ - s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS; - /* Unselect all slaves */ for (i = 0; i < s->num_cs; ++i) { s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; @@ -664,6 +678,11 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == s->r_timings || addr == s->r_ce_ctrl || addr == R_INTR_CTRL || + (s->ctrl->has_dma && addr == R_DMA_CTRL) || + (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) || + (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || + (s->ctrl->has_dma && addr == R_DMA_LEN) || + (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { return s->regs[addr]; @@ -674,6 +693,154 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) } } +/* + * Accumulate the result of the reads to provide a checksum that will + * be used to validate the read timing settings. + */ +static void aspeed_smc_dma_checksum(AspeedSMCState *s) +{ + MemTxResult result; + uint32_t data; + + if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid direction for DMA checksum\n", __func__); + return; + } + + while (s->regs[R_DMA_LEN]) { + result = address_space_read(&s->dma_as, s->regs[R_DMA_FLASH_ADDR], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)&data, 4); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n", + __func__, s->regs[R_DMA_FLASH_ADDR]); + return; + } + + /* + * When the DMA is on-going, the DMA registers are updated + * with the current working addresses and length. + */ + s->regs[R_DMA_CHECKSUM] += data; + s->regs[R_DMA_FLASH_ADDR] += 4; + s->regs[R_DMA_LEN] -= 4; + } +} + +static void aspeed_smc_dma_rw(AspeedSMCState *s) +{ + MemTxResult result; + uint32_t data; + + while (s->regs[R_DMA_LEN]) { + if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { + result = address_space_read(&s->dma_as, s->regs[R_DMA_DRAM_ADDR], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)&data, 4); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", + __func__, s->regs[R_DMA_DRAM_ADDR]); + return; + } + + result = address_space_write(&s->dma_as, s->regs[R_DMA_FLASH_ADDR], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)&data, 4); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%08x\n", + __func__, s->regs[R_DMA_FLASH_ADDR]); + return; + } + } else { + result = address_space_read(&s->dma_as, s->regs[R_DMA_FLASH_ADDR], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)&data, 4); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n", + __func__, s->regs[R_DMA_FLASH_ADDR]); + return; + } + + result = address_space_write(&s->dma_as, s->regs[R_DMA_DRAM_ADDR], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)&data, 4); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", + __func__, s->regs[R_DMA_DRAM_ADDR]); + return; + } + } + + /* + * When the DMA is on-going, the DMA registers are updated + * with the current working addresses and length. + */ + s->regs[R_DMA_FLASH_ADDR] += 4; + s->regs[R_DMA_DRAM_ADDR] += 4; + s->regs[R_DMA_LEN] -= 4; + } +} + +static void aspeed_smc_dma_stop(AspeedSMCState *s) +{ + /* + * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the + * engine is idle + */ + s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; + s->regs[R_DMA_CHECKSUM] = 0; + + /* + * Lower the DMA irq in any case. The IRQ control register could + * have been cleared before disabling the DMA. + */ + qemu_irq_lower(s->irq); +} + +/* + * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA + * can start even if the result of the previous was not collected. + */ +static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) +{ + return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && + !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); +} + +static void aspeed_smc_dma_done(AspeedSMCState *s) +{ + s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; + if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { + qemu_irq_raise(s->irq); + } +} + +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl) +{ + if (!(dma_ctrl & DMA_CTRL_ENABLE)) { + s->regs[R_DMA_CTRL] = dma_ctrl; + + aspeed_smc_dma_stop(s); + return; + } + + if (aspeed_smc_dma_in_progress(s)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__); + return; + } + + s->regs[R_DMA_CTRL] = dma_ctrl; + + if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { + aspeed_smc_dma_checksum(s); + } else { + aspeed_smc_dma_rw(s); + } + + aspeed_smc_dma_done(s); +} + static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -697,6 +864,19 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, if (value != s->regs[R_SEG_ADDR0 + cs]) { aspeed_smc_flash_set_segment(s, cs, value); } + } else if (addr == R_INTR_CTRL) { + s->regs[addr] = value; + } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) { + aspeed_smc_dma_ctrl(s, value); + } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) { + value &= DMA_DRAM_MASK(s); + s->regs[addr] = s->sdram_base | value; + } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) { + value &= DMA_FLASH_MASK; + s->regs[addr] = s->ctrl->flash_window_base | value; + } else if (s->ctrl->has_dma && addr == R_DMA_LEN) { + value &= DMA_LENGTH_MASK; + s->regs[addr] = value; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", __func__, addr); @@ -711,6 +891,34 @@ static const MemoryRegionOps aspeed_smc_ops = { .valid.unaligned = true, }; + +/* + * Populate our custom address space for DMAs with only the regions we + * need : the AHB window for the flash devices and the SDRAM. + */ +static void aspeed_smc_dma_setup(AspeedSMCState *s) +{ + char name[32]; + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); + MemoryRegion *sdram_alias = g_new(MemoryRegion, 1); + + snprintf(name, sizeof(name), "%s-dma", s->ctrl->name); + memory_region_init(&s->dma_mr, OBJECT(s), name, + s->sdram_base + s->max_ram_size); + address_space_init(&s->dma_as, &s->dma_mr, name); + + snprintf(name, sizeof(name), "%s.flash", s->ctrl->name); + memory_region_init_alias(flash_alias, OBJECT(s), name, &s->mmio_flash, + 0, s->ctrl->flash_window_size); + memory_region_add_subregion(&s->dma_mr, s->ctrl->flash_window_base, + flash_alias); + + memory_region_init_alias(sdram_alias, OBJECT(s), "ram", sysmem, + s->sdram_base, s->max_ram_size); + memory_region_add_subregion(&s->dma_mr, s->sdram_base, sdram_alias); +} + static void aspeed_smc_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -736,10 +944,12 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) s->num_cs = s->ctrl->max_slaves; } + /* DMA irq. Keep it first for the initialization in the SoC */ + sysbus_init_irq(sbd, &s->irq); + s->spi = ssi_create_bus(dev, "spi"); /* Setup cs_lines for slaves */ - sysbus_init_irq(sbd, &s->irq); s->cs_lines = g_new0(qemu_irq, s->num_cs); ssi_auto_connect_slaves(dev, s->cs_lines, s->spi); @@ -786,6 +996,11 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); offset += fl->size; } + + /* DMA support */ + if (s->ctrl->has_dma) { + aspeed_smc_dma_setup(s); + } } static const VMStateDescription vmstate_aspeed_smc = { From patchwork Fri Sep 21 16:19:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973313 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Gzp96Blzz9sCS for ; Sat, 22 Sep 2018 02:39:29 +1000 (AEST) Received: from localhost ([::1]:56492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OSl-0004QO-8t for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:39:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43068) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQn-0002f4-8m for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OBH-0004Yt-3J for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:26 -0400 Received: from 1.mo173.mail-out.ovh.net ([178.33.111.180]:36975) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OBG-0004YY-RD for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:23 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.137]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id AC6A4DA7F0 for ; Fri, 21 Sep 2018 18:21:21 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 5BBD6520093; Fri, 21 Sep 2018 18:21:12 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:37 +0200 Message-Id: <20180921161939.822-10-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1909807720689470272 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.111.180 Subject: [Qemu-devel] [PATCH v2 09/11] aspeed/smc: add DMA calibration settings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When doing calibration, the SPI clock rate in the CE0 Control Register and the read delay cycles in the Read Timing Compensation Register are set using bit[11:4] of the DMA Control Register. Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 64 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 625c29ba4ad2..db89c54dfc9f 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -74,6 +74,10 @@ #define CTRL_CMD_MASK 0xff #define CTRL_DUMMY_HIGH_SHIFT 14 #define CTRL_AST2400_SPI_4BYTE (1 << 13) +#define CE_CTRL_CLOCK_FREQ_SHIFT 8 +#define CE_CTRL_CLOCK_FREQ_MASK 0xf +#define CE_CTRL_CLOCK_FREQ(div) \ + (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ #define CTRL_CE_STOP_ACTIVE (1 << 2) #define CTRL_CMD_MODE_MASK 0x3 @@ -109,7 +113,7 @@ #define DMA_CTRL_DELAY_SHIFT 8 #define DMA_CTRL_FREQ_MASK 0xf #define DMA_CTRL_FREQ_SHIFT 4 -#define DMA_CTRL_MODE (1 << 3) +#define DMA_CTRL_CALIB (1 << 3) #define DMA_CTRL_CKSUM (1 << 2) #define DMA_CTRL_WRITE (1 << 1) #define DMA_CTRL_ENABLE (1 << 0) @@ -693,6 +697,60 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) } } +static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) +{ + /* HCLK/1 .. HCLK/16 */ + const uint8_t hclk_divisors[] = { + 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 + }; + int i; + + for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { + if (hclk_mask == hclk_divisors[i]) { + return i + 1; + } + } + + qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask); + return 0; +} + +/* + * When doing calibration, the SPI clock rate in the CE0 Control + * Register and the read delay cycles in the Read Timing Compensation + * Register are set using bit[11:4] of the DMA Control Register. + */ +static void aspeed_smc_dma_calibration(AspeedSMCState *s) +{ + uint8_t delay = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; + uint8_t hclk_mask = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); + uint32_t hclk_shift = (hclk_div - 1) << 2; + uint8_t cs; + + /* + * The Read Timing Compensation Register values apply to all CS on + * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays + */ + if (hclk_div && hclk_div < 6) { + s->regs[s->r_timings] &= ~(0xf << hclk_shift); + s->regs[s->r_timings] |= delay << hclk_shift; + } + + /* + * TODO: compute the CS from the DMA address and the segment + * registers. This is not really a problem for now because the + * Timing Register values apply to all CS and software uses CS0 to + * do calibration. + */ + cs = 0; + s->regs[s->r_ctrl0 + cs] &= + ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); + s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -708,6 +766,10 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) return; } + if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { + aspeed_smc_dma_calibration(s); + } + while (s->regs[R_DMA_LEN]) { result = address_space_read(&s->dma_as, s->regs[R_DMA_FLASH_ADDR], MEMTXATTRS_UNSPECIFIED, From patchwork Fri Sep 21 16:19:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzsP2LTwz9s8F for ; Sat, 22 Sep 2018 02:42:15 +1000 (AEST) Received: from localhost ([::1]:56518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OVQ-0006ei-4d for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:42:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQm-0002a1-Ko for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OBS-0004fK-5W for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:37 -0400 Received: from 10.mo178.mail-out.ovh.net ([46.105.76.150]:50672) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OBR-0004eN-D9 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:34 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.143]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 2E1E2332D4 for ; Fri, 21 Sep 2018 18:21:31 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id AE1FD5200B6; Fri, 21 Sep 2018 18:21:21 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:38 +0200 Message-Id: <20180921161939.822-11-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1912340993998490432 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.76.150 Subject: [Qemu-devel] [PATCH v2 10/11] aspeed/smc: inject errors in DMA checksum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index db89c54dfc9f..01c3fd7b2666 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -751,6 +751,30 @@ static void aspeed_smc_dma_calibration(AspeedSMCState *s) s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); } +static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) +{ + uint8_t delay = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; + uint8_t hclk_mask = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + + /* + * Typical values of a palmetto-bmc machine. + */ + switch (aspeed_smc_hclk_divisor(hclk_mask)) { + case 4 ... 16: + return false; + case 3: /* at least one HCLK cycle delay */ + return (delay & 0x7) < 1; + case 2: /* at least two HCLK cycle delay */ + return (delay & 0x7) < 2; + case 1: /* (> 100MHz) is above the max freq of the controller */ + return true; + default: + g_assert_not_reached(); + } +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -788,6 +812,11 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) s->regs[R_DMA_FLASH_ADDR] += 4; s->regs[R_DMA_LEN] -= 4; } + + if (aspeed_smc_inject_read_failure(s)) { + s->regs[R_DMA_CHECKSUM] = 0xbadc0de; + } + } static void aspeed_smc_dma_rw(AspeedSMCState *s) From patchwork Fri Sep 21 16:19:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzqD0Lggz9sCS for ; Sat, 22 Sep 2018 02:40:24 +1000 (AEST) Received: from localhost ([::1]:56494 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OTd-00052R-K6 for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:40:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQm-0002Rn-HD for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OBZ-0004hE-G6 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:44 -0400 Received: from 13.mo7.mail-out.ovh.net ([87.98.150.175]:59418) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OBZ-0004h1-9T for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:41 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.76]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 61DD3DDCAE for ; Fri, 21 Sep 2018 18:21:40 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 0DC3F520093; Fri, 21 Sep 2018 18:21:31 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:39 +0200 Message-Id: <20180921161939.822-12-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1915155742927981376 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.150.175 Subject: [Qemu-devel] [PATCH v2 11/11] aspeed/smc: Add dummy data register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The SMC controllers have a register containing the byte that will be used as dummy output. It can be modified by software. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- hw/ssi/aspeed_smc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 01c3fd7b2666..55ceffe100d3 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -104,8 +104,8 @@ /* Misc Control Register #1 */ #define R_MISC_CTRL1 (0x50 / 4) -/* Misc Control Register #2 */ -#define R_MISC_CTRL2 (0x54 / 4) +/* SPI dummy cycle data */ +#define R_DUMMY_DATA (0x54 / 4) /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) @@ -550,7 +550,7 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) */ if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { - ssi_transfer(fl->controller->spi, 0xFF); + ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); } } } @@ -682,6 +682,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == s->r_timings || addr == s->r_ce_ctrl || addr == R_INTR_CTRL || + addr == R_DUMMY_DATA || (s->ctrl->has_dma && addr == R_DMA_CTRL) || (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) || (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || @@ -957,6 +958,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, } } else if (addr == R_INTR_CTRL) { s->regs[addr] = value; + } else if (addr == R_DUMMY_DATA) { + s->regs[addr] = value & 0xff ; } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) { aspeed_smc_dma_ctrl(s, value); } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {