From patchwork Fri Aug 24 13:17:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roman Kapl X-Patchwork-Id: 961849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sysgo.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41xhg01LWwz9s0n for ; Fri, 24 Aug 2018 23:18:20 +1000 (AEST) Received: from localhost ([::1]:41782 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftByj-0000vo-TH for incoming@patchwork.ozlabs.org; Fri, 24 Aug 2018 09:18:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34697) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftByH-0000vS-Ax for qemu-devel@nongnu.org; Fri, 24 Aug 2018 09:17:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ftByC-00020G-Gk for qemu-devel@nongnu.org; Fri, 24 Aug 2018 09:17:49 -0400 Received: from mail.sysgo.com ([176.9.12.79]:53020) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftByC-0001yF-8i for qemu-devel@nongnu.org; Fri, 24 Aug 2018 09:17:44 -0400 From: Roman Kapl To: Date: Fri, 24 Aug 2018 15:17:34 +0200 Message-Id: <20180824131734.18557-1-rka@sysgo.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 176.9.12.79 Subject: [Qemu-devel] [PATCH] tcg/i386: fix vector operations on 32-bit hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-devel@nongnu.org, Roman Kapl Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers. This was defined as no-op for 32-bit x86, with the assumption that we have eight registers anyway. This assumption is not true once we have xmm regs. Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes and have overflown into other opcode fields, wreaking havoc. To trigger these problems, you can try running the "movi d8, #0x0" AArch64 instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated, but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2". Fixes: 770c2fc7bb ("Add vector operations") Signed-off-by: Roman Kapl --- Note: It could also be possible to add a dedicated VEC_LOWREGMASK, but I don't think it is better or signigicantly faster. tcg/i386/tcg-target.inc.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index a91e4f1313..436195894b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -302,11 +302,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, return 0; } -#if TCG_TARGET_REG_BITS == 64 # define LOWREGMASK(x) ((x) & 7) -#else -# define LOWREGMASK(x) (x) -#endif #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */