From patchwork Wed Aug 22 20:41:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961030 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="GVvhlFEz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfb93K33z9s4Z for ; Thu, 23 Aug 2018 06:41:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727346AbeHWAHs (ORCPT ); Wed, 22 Aug 2018 20:07:48 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:37712 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727285AbeHWAHs (ORCPT ); Wed, 22 Aug 2018 20:07:48 -0400 Received: by mail-lj1-f195.google.com with SMTP id v9-v6so2447614ljk.4 for ; Wed, 22 Aug 2018 13:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LFNwoKHWnAWrIGSswOfaA83EB0WZUvIJWxI4582V7zU=; b=GVvhlFEzCrNJjg99FnARE8VpwbpgDTLBIMayWMkU+aouBmuZTxxtDAmy7Wn4PX/Tu4 QUmWW6sSI89K0qoZlj1yYqzQgRFMo+2k2tOV35Ym44Bw8KDicm8Avfs+iQrES9ZQg/uO lKp2UiXOgp4vMW0dmdgie+elOAwvkVhjWiHm8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LFNwoKHWnAWrIGSswOfaA83EB0WZUvIJWxI4582V7zU=; b=uVaM/HjX1DJwuyqVu/rjJUwbLScZzKYEKIJtVkzDPGCDP5eSrm+qoer+qSkuzLkN8h Pdj9CJx7KvHEOxIFoyoPoxCTDRS6FVsj3YRX3tvjl7UlNeIXP1ROxQ9S64jkY9J99atx r0t5JQ3/O8W2FcCbKpaPgJpn8KwDZ/OJ0Izl61wl5eNIxrgzAeaa/ZB/cfjQVSPbt1Dj iuNFf4jYto4dVL/RuZoF9No6Zm45nyovLocOcJjjB/zNrBcTSoJVMCgXga81L2qZBuWm CIo8nf1zhHq8dCSZ6o9aQBCp9yZKU2KyIZ1vN2DV1dKmK1K90l7FbR3aCEbpKeoNxv7t RMGQ== X-Gm-Message-State: AOUpUlHdfKb6lIBf8+bqHqYriZvl00bt7WUPS2TL4T6Ew2Tmk+Sxidio Z2Tew0Qd2hLpR7clk7Js/2MhYA== X-Google-Smtp-Source: AA+uWPxDI9n7e9U5Yj5OhGQkc/RvhWQp1bkPfLaA3qfifQUtVNVeWoFQw8wfGkgePwsJPBo2WNmuiw== X-Received: by 2002:a2e:8346:: with SMTP id l6-v6mr26109614ljh.72.1534970481505; Wed, 22 Aug 2018 13:41:21 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:20 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Arnd Bergmann , arm@kernel.org, Linus Walleij Subject: [PATCH 01/11] ARM/gpio: ep93xx: build standalone Date: Wed, 22 Aug 2018 22:41:01 +0200 Message-Id: <20180822204111.9581-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arnd Bergmann As a preparation for multiplatform support, this ensures that the ep93xx gpio driver can be built without any of the platform specific header files. We pass the IRQ numbers as a resource now, and use the virtual mmio base from the already existing resource, rather than relying on the hardwired virtual address from the header file. Some numbers are now hardcoded that came from macros in the past, but for all I can tell, the driver already relied on the specific values. Cc: arm@kernel.org Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Olof Johansson --- Arnd/other ARM SoC person: Please provide an ACK for this patch so I can merge it with the rest of the refactorings into the GPIO tree. --- arch/arm/mach-ep93xx/core.c | 9 +++++++ drivers/gpio/gpio-ep93xx.c | 48 ++++++++++++++++++------------------- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 574dfdc527ed..b82b632789f7 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -141,6 +141,15 @@ EXPORT_SYMBOL_GPL(ep93xx_chip_revision); *************************************************************************/ static struct resource ep93xx_gpio_resource[] = { DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), }; static struct platform_device ep93xx_gpio_device = { diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 45d384039e9b..654525d6a9f1 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -22,11 +22,20 @@ /* FIXME: this is here for gpio_to_irq() - get rid of this! */ #include -#include -#include - #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) +void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */ +#define EP93XX_GPIO_REG(x) (ep93xx_gpio_base + (x)) +#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) +#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) + +/* Maximum value for gpio line identifiers */ +#define EP93XX_GPIO_LINE_MAX 63 + +/* Maximum value for irq capable line identifiers */ +#define EP93XX_GPIO_LINE_MAX_IRQ 23 + struct ep93xx_gpio { void __iomem *mmio_base; struct gpio_chip gc[8]; @@ -87,7 +96,7 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) status = readb(EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; + int gpio_irq = gpio_to_irq(0) + i; generic_handle_irq(gpio_irq); } } @@ -95,7 +104,7 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) status = readb(EP93XX_GPIO_B_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; + int gpio_irq = gpio_to_irq(8) + i; generic_handle_irq(gpio_irq); } } @@ -110,7 +119,7 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) */ unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ - int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; + int gpio_irq = gpio_to_irq(16) + port_f_idx; generic_handle_irq(gpio_irq); } @@ -228,9 +237,10 @@ static struct irq_chip ep93xx_gpio_irq_chip = { .irq_set_type = ep93xx_gpio_irq_type, }; -static void ep93xx_gpio_init_irq(void) +static void ep93xx_gpio_init_irq(struct platform_device *pdev) { int gpio_irq; + int i; for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { @@ -239,24 +249,11 @@ static void ep93xx_gpio_init_irq(void) irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } - irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, + irq_set_chained_handler(platform_get_irq(pdev, 0), ep93xx_gpio_ab_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, - ep93xx_gpio_f_irq_handler); + for (i = 1; i <= 8; i++) + irq_set_chained_handler(platform_get_irq(pdev, i), + ep93xx_gpio_f_irq_handler); } @@ -362,6 +359,7 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res); if (IS_ERR(ep93xx_gpio->mmio_base)) return PTR_ERR(ep93xx_gpio->mmio_base); + ep93xx_gpio_base = ep93xx_gpio->mmio_base; for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { struct gpio_chip *gc = &ep93xx_gpio->gc[i]; @@ -373,7 +371,7 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) bank->label); } - ep93xx_gpio_init_irq(); + ep93xx_gpio_init_irq(pdev); return 0; } From patchwork Wed Aug 22 20:41:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961031 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="bCsRGdoN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbB5zWRz9s5c for ; Thu, 23 Aug 2018 06:41:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727285AbeHWAHt (ORCPT ); Wed, 22 Aug 2018 20:07:49 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:43702 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727331AbeHWAHt (ORCPT ); Wed, 22 Aug 2018 20:07:49 -0400 Received: by mail-lj1-f193.google.com with SMTP id m84-v6so2429773lje.10 for ; Wed, 22 Aug 2018 13:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uh0WbNXotrGv/LOuuP8ez/+FvQdmMcnLT3xmPJQ17Cs=; b=bCsRGdoNmAZHbv2xavWhPkrDaToTMw99ukokLw2irfs8XKw+eKmM7l8BEauVyT0Lx7 ugYUhJct5IgrERSmvMQDWiCwjDekhJinkgfke7XEUiNdNRVoFMJi8Fvbc9Uf1Th35SfC W1Vzu8vjDS1Wzrqsrw8hSobAvPDOkAs8G5xUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uh0WbNXotrGv/LOuuP8ez/+FvQdmMcnLT3xmPJQ17Cs=; b=ll2iuxmqNfgGdPGarksG/C9vShHLGLo7khWkhnEoyJLSzLTLJ/D27xMBLEPYNKxApW TllerivHnH2xdwPs5z+aKyQbHWiAdcPhgJfzE69U8jshtCK9+bdP/3HG9IGYfUlje9XP fHoQP7qnjQljzFvr1iI3M81GJbm+58QkRnlerF9NCvN/8uEfPdYCH9VDeUX9ziImeTXu uvLaoO18LfNAjtNy/Zr/tBgVw8SG6gLVrfc07tWUpEp9Z+g92OnR8qeX2sKYtVxCwAqz F0XgzY8DPy4d54xBPvBEwRPEXBqqkEBZskEI/cNJyRTgUG/3WK76/yUADA2tChgoCt55 /axQ== X-Gm-Message-State: AOUpUlGxrR6hHiNuY4jqWBP6bAk3a9JpVaR9O5Qxnjl6/7a5sq1iHt1C 1dDNF2QA6+DMvp29ViQL17Nphx8Z1nYVCA== X-Google-Smtp-Source: AA+uWPxCrWt2ayR1ZmSaipIaP/xabf3QezS05f1xKd+UokJE8iYZrGJ2warwHLF7GUa9cEG0nCdZuQ== X-Received: by 2002:a2e:534e:: with SMTP id t14-v6mr30103840ljd.26.1534970484301; Wed, 22 Aug 2018 13:41:24 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:23 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 02/11] gpio: ep93xx: Cut down variable names Date: Wed, 22 Aug 2018 22:41:02 +0200 Message-Id: <20180822204111.9581-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In order to clean up the driver I need to cut a few trees, sorry, variable names, so I can see the forest, sorry driver properly. Signed-off-by: Linus Walleij Tested-by: Alexander Sverdlin --- drivers/gpio/gpio-ep93xx.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 654525d6a9f1..3bfd0e46f7ed 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -37,7 +37,7 @@ void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 struct ep93xx_gpio { - void __iomem *mmio_base; + void __iomem *base; struct gpio_chip gc[8]; }; @@ -323,10 +323,10 @@ static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, - void __iomem *mmio_base, struct ep93xx_gpio_bank *bank) + void __iomem *base, struct ep93xx_gpio_bank *bank) { - void __iomem *data = mmio_base + bank->data; - void __iomem *dir = mmio_base + bank->dir; + void __iomem *data = base + bank->data; + void __iomem *dir = base + bank->dir; int err; err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); @@ -346,27 +346,27 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, static int ep93xx_gpio_probe(struct platform_device *pdev) { - struct ep93xx_gpio *ep93xx_gpio; + struct ep93xx_gpio *epg; struct resource *res; int i; struct device *dev = &pdev->dev; - ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL); - if (!ep93xx_gpio) + epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL); + if (!epg) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ep93xx_gpio->mmio_base)) - return PTR_ERR(ep93xx_gpio->mmio_base); - ep93xx_gpio_base = ep93xx_gpio->mmio_base; + epg->base = devm_ioremap_resource(dev, res); + if (IS_ERR(epg->base)) + return PTR_ERR(epg->base); + ep93xx_gpio_base = epg->base; for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct gpio_chip *gc = &ep93xx_gpio->gc[i]; + struct gpio_chip *gc = &epg->gc[i]; struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; if (ep93xx_gpio_add_bank(gc, &pdev->dev, - ep93xx_gpio->mmio_base, bank)) + epg->base, bank)) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", bank->label); } From patchwork Wed Aug 22 20:41:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961032 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="CQGW/1tq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbF53ybz9s3C for ; Thu, 23 Aug 2018 06:41:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727372AbeHWAHw (ORCPT ); Wed, 22 Aug 2018 20:07:52 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:44306 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727331AbeHWAHw (ORCPT ); Wed, 22 Aug 2018 20:07:52 -0400 Received: by mail-lf1-f67.google.com with SMTP id g6-v6so2376411lfb.11 for ; Wed, 22 Aug 2018 13:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O6WuP8qwseI7NYdNvQzo28H1LrcQOeUzubYHV0pnHVE=; b=CQGW/1tqOhJbkOr49Ekr6VWN51qcTZHL9M3VIL7m5POBEvgjOq3uGUZlDsE+CBEIin 7u7OMqjBlJX6TQS0ZjUvsH9qIgv4ntAcJ3hCWIzBT+KYT1wH6OzrAT6n24qfvjlvM1SY HPScrUTiNwsVPN8nzpda145phDqsnR32Sfwzk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O6WuP8qwseI7NYdNvQzo28H1LrcQOeUzubYHV0pnHVE=; b=NMiX2zxHs29Ed0HAo+bp1DtWOUIxv1qwH5zThz5ryTl5sl5POhxnhKYo4VSekcRLUB ckAQcvMhBVmPPq3C+91zqJ7lRAg2f6sIWWuxFFVKnzyJRMmv59dQPvUDPQuecRUv9Z2m 6eGTppqmQKjkRSel4VrmOKLZBDZRMEaTTnIA2VK3C4M7i/mmfuEeyv5P5QcKtGV2n5AO 0MXIAncMtdZyb8ngyR6Bp1o4qPQ0M2V5h10B/LR4I93uEmyqKXhO0rkBkzagKZKnbmt0 ouOMAw2JQzH79Xk99+kCUHP47aP8VEqlgUVeto2w5jzfXaFPQ3vD5kWwuVJlDmCniXao T56g== X-Gm-Message-State: AOUpUlFMu2/bdGtn9mKt6zLW31FORM2h9tcPgdVfgeGzTCAkwny6n3vm 4pXifTvEgKsxLPi1o1V+DnJRxA== X-Google-Smtp-Source: AA+uWPzcoYoKny3gN4drLCflieo1u/2Buj9zvI92dlsi7uboxrHq7YrcbBvevy8SxIaNVvIDXcObgg== X-Received: by 2002:a19:990d:: with SMTP id b13-v6mr19074225lfe.13.1534970487196; Wed, 22 Aug 2018 13:41:27 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:26 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 03/11] gpio: ep93xx: Switch to SPDX license tag Date: Wed, 22 Aug 2018 22:41:03 +0200 Message-Id: <20180822204111.9581-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The subject says it all. Cut down on boilerplate. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3bfd0e46f7ed..3822d11e90ac 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Generic EP93xx GPIO handling * @@ -6,10 +7,6 @@ * * Based on code originally from: * linux/arch/arm/mach-ep93xx/core.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include From patchwork Wed Aug 22 20:41:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961033 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="EPke5zQ+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbJ6tSLz9s3C for ; Thu, 23 Aug 2018 06:41:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727453AbeHWAHz (ORCPT ); Wed, 22 Aug 2018 20:07:55 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:41639 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727331AbeHWAHz (ORCPT ); Wed, 22 Aug 2018 20:07:55 -0400 Received: by mail-lj1-f193.google.com with SMTP id y17-v6so2437860ljy.8 for ; Wed, 22 Aug 2018 13:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CNNg5YSFxUgNMgU8iF4QVIUBRAAvk8zwjvj3+dqCUUU=; b=EPke5zQ+LDfbSOkyBZNSr8jP9rpUPUh6JHSnnY6ZLxFnZ5Em9myS6YnIuJmJpkCJ0C 67295INGw1lPvtwUrC4kV7liv9x+zJh4zQfEllDIUQSBIwyrs7fyuEW/2xuWj046Wgq5 OzVSe0GKxzZc/FBy46zsXzPtGSkqodWCiMigc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CNNg5YSFxUgNMgU8iF4QVIUBRAAvk8zwjvj3+dqCUUU=; b=ToGPRBd+Ud55/BhXP6xWed+Vjsm2FCLQHvV3o0DXD0tdpd1gCxbJyuWtbZZKo26FBf g8Hlgqi3LrrN37+zt4q4Fci0SHSR7odIKWVF/GBRdy0PQR1BOVYTiu0INL+QLSS0SDfO gfT0n/XpNUNgW/pbOuN7g8PmR1l0pHENjb9EIqZs558mFeUWXrJk8rxcMQyuYLXt2PdE kTIIpTtYx4BS34ZvZK1vSVYzWHAKmafwnBzE/q48Fm070aRN+r+mtPdueXwGoK3CiFZa lNKMxDxMXN7KVGW5tuv+njlnYeIcKE9kBKkbv3ft/vLzY1JXiT4HiQbYBqe/wd4eRZ59 JRew== X-Gm-Message-State: APzg51C6g4IEWoF21MYwUuwFLCLrGs2RwyhXJlU9ibvqxdFhWvxj+TJF jll+DCZRmHNfZGZSaKX2wtC1tzevWPxIcA== X-Google-Smtp-Source: ANB0VdZpSPTt49mmiQx+88CgxDc8RkgiZEmxNfdYF2OKexfrfUzPdhK62xtl+81bkGQEEYsvhg6/DQ== X-Received: by 2002:a2e:9a16:: with SMTP id o22-v6mr3063545lji.17.1534970489203; Wed, 22 Aug 2018 13:41:29 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:28 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 04/11] gpio: ep93xx: Pass around struct gpio_chip Date: Wed, 22 Aug 2018 22:41:04 +0200 Message-Id: <20180822204111.9581-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Instead of using a global variable, pass around the struct gpio_chip * pointer and dereference to the state container struct ep93xx_gpio as needed, like all other drivers do. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 111 ++++++++++++++++++++++++------------- 1 file changed, 73 insertions(+), 38 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3822d11e90ac..379f2573f794 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -21,11 +21,9 @@ #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) -void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */ -#define EP93XX_GPIO_REG(x) (ep93xx_gpio_base + (x)) -#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) -#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) -#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) +#define EP93XX_GPIO_F_INT_STATUS 0x5c +#define EP93XX_GPIO_A_INT_STATUS 0xa0 +#define EP93XX_GPIO_B_INT_STATUS 0xbc /* Maximum value for gpio line identifiers */ #define EP93XX_GPIO_LINE_MAX 63 @@ -54,23 +52,24 @@ static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; -static void ep93xx_gpio_update_int_params(unsigned port) +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port) { BUG_ON(port > 2); - writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port])); + writeb_relaxed(0, epg->base + int_en_register_offset[port]); writeb_relaxed(gpio_int_type2[port], - EP93XX_GPIO_REG(int_type2_register_offset[port])); + epg->base + int_type2_register_offset[port]); writeb_relaxed(gpio_int_type1[port], - EP93XX_GPIO_REG(int_type1_register_offset[port])); + epg->base + int_type1_register_offset[port]); writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], - EP93XX_GPIO_REG(int_en_register_offset[port])); + epg->base + int_en_register_offset[port]); } -static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) +static void ep93xx_gpio_int_debounce(struct ep93xx_gpio *epg, + unsigned int irq, bool enable) { int line = irq_to_gpio(irq); int port = line >> 3; @@ -82,15 +81,17 @@ static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) gpio_int_debounce[port] &= ~port_mask; writeb(gpio_int_debounce[port], - EP93XX_GPIO_REG(int_debounce_register_offset[port])); + epg->base + int_debounce_register_offset[port]); } static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) { + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); unsigned char status; int i; - status = readb(EP93XX_GPIO_A_INT_STATUS); + status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { int gpio_irq = gpio_to_irq(0) + i; @@ -98,7 +99,7 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) } } - status = readb(EP93XX_GPIO_B_INT_STATUS); + status = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { int gpio_irq = gpio_to_irq(8) + i; @@ -123,20 +124,24 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) static void ep93xx_gpio_irq_ack(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); } - writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); + writeb(port_mask, epg->base + eoi_register_offset[port]); } static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); @@ -145,27 +150,31 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ gpio_int_unmasked[port] &= ~port_mask; - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); - writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); + writeb(port_mask, epg->base + eoi_register_offset[port]); } static void ep93xx_gpio_irq_mask(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; gpio_int_unmasked[port] &= ~(1 << (line & 7)); - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); } static void ep93xx_gpio_irq_unmask(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; gpio_int_unmasked[port] |= 1 << (line & 7); - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); } /* @@ -175,6 +184,8 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) */ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); const int gpio = irq_to_gpio(d->irq); const int port = gpio >> 3; const int port_mask = 1 << (gpio & 7); @@ -220,7 +231,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) gpio_int_enabled[port] |= port_mask; - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); return 0; } @@ -234,23 +245,47 @@ static struct irq_chip ep93xx_gpio_irq_chip = { .irq_set_type = ep93xx_gpio_irq_type, }; -static void ep93xx_gpio_init_irq(struct platform_device *pdev) +static void ep93xx_gpio_init_irq(struct platform_device *pdev, + struct ep93xx_gpio *epg) { int gpio_irq; int i; + /* The A bank */ for (gpio_irq = gpio_to_irq(0); - gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { + gpio_irq < gpio_to_irq(8); + gpio_irq++) { + irq_set_chip_data(gpio_irq, &epg->gc[0]); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); + irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + } + /* The B bank */ + for (gpio_irq = gpio_to_irq(8); + gpio_irq < gpio_to_irq(16); + gpio_irq++) { + irq_set_chip_data(gpio_irq, &epg->gc[1]); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); + irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + } + /* The F bank */ + for (gpio_irq = gpio_to_irq(16); + gpio_irq < gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); + gpio_irq++) { + irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } - irq_set_chained_handler(platform_get_irq(pdev, 0), - ep93xx_gpio_ab_irq_handler); + irq_set_chained_handler_and_data(platform_get_irq(pdev, 0), + ep93xx_gpio_ab_irq_handler, + &epg->gc[0]); for (i = 1; i <= 8; i++) - irq_set_chained_handler(platform_get_irq(pdev, i), - ep93xx_gpio_f_irq_handler); + irq_set_chained_handler_and_data(platform_get_irq(pdev, i), + ep93xx_gpio_f_irq_handler, + &epg->gc[i]); } @@ -285,10 +320,11 @@ static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false), }; -static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset, +static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { - int gpio = chip->base + offset; + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int gpio = gc->base + offset; int irq = gpio_to_irq(gpio); u32 debounce; @@ -299,7 +335,7 @@ static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset, return -EINVAL; debounce = pinconf_to_config_argument(config); - ep93xx_gpio_int_debounce(irq, debounce ? true : false); + ep93xx_gpio_int_debounce(epg, irq, debounce ? true : false); return 0; } @@ -320,10 +356,11 @@ static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, - void __iomem *base, struct ep93xx_gpio_bank *bank) + struct ep93xx_gpio *epg, + struct ep93xx_gpio_bank *bank) { - void __iomem *data = base + bank->data; - void __iomem *dir = base + bank->dir; + void __iomem *data = epg->base + bank->data; + void __iomem *dir = epg->base + bank->dir; int err; err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); @@ -338,7 +375,7 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, gc->to_irq = ep93xx_gpio_to_irq; } - return devm_gpiochip_add_data(dev, gc, NULL); + return devm_gpiochip_add_data(dev, gc, epg); } static int ep93xx_gpio_probe(struct platform_device *pdev) @@ -356,19 +393,17 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) epg->base = devm_ioremap_resource(dev, res); if (IS_ERR(epg->base)) return PTR_ERR(epg->base); - ep93xx_gpio_base = epg->base; for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { struct gpio_chip *gc = &epg->gc[i]; struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; - if (ep93xx_gpio_add_bank(gc, &pdev->dev, - epg->base, bank)) + if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank)) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", bank->label); } - ep93xx_gpio_init_irq(pdev); + ep93xx_gpio_init_irq(pdev, epg); return 0; } From patchwork Wed Aug 22 20:41:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961034 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="MiSkPQaA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbL20hyz9s4V for ; Thu, 23 Aug 2018 06:41:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727331AbeHWAH4 (ORCPT ); Wed, 22 Aug 2018 20:07:56 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:34232 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAH4 (ORCPT ); Wed, 22 Aug 2018 20:07:56 -0400 Received: by mail-lf1-f68.google.com with SMTP id g9-v6so2411650lfh.1 for ; Wed, 22 Aug 2018 13:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KhRH1Uj6E5YD9xU+yQMHc2pspnoZe4NMLGmDDUJ+OXs=; b=MiSkPQaA+atC4Mru5wddwetAqLpTOK2b1KErUlne2CbAQXVqoA0Q1naKuDFUpbcbB1 feVMj6P8Vz1rW1jBcSCLdNNHrSOK6PqXNkmVvLK3kr6EMne4f1Nhsg5P9uySAzrV7rSM OcLo8856LXJgZE0b+xlXLUySExAsb9vBQ+BVs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KhRH1Uj6E5YD9xU+yQMHc2pspnoZe4NMLGmDDUJ+OXs=; b=nrQ/3MaNm3QbuC72y89Ppsfh1L7j9pA+miMzBUnjm+3JpGlcBCHz5PerMDoszmjrCM 8DcCoulrlEeJ2M7bK5Awv0xq79HUh2fkvouH4L3yFB2oZvyxV7C7c+TcU3GMOFJzAXzP 5gtuDixrvO5DuwVLOZCrmoM6Q6DLZr0ZSC898lpsU2vlosckC7uEzhF3KJPfA/4GWVcX EHAgDUPikX4SRXtdxU4vfh0JUaw+9W/3EZmOqkDkJcg45D56eTltpncIZjoR5+Dd2Ofp jGHPhMl33g/VKDz0h3H8/G6bHxUaSmP2PjnFTWh72EZpd8j87730U3npApQWY2DW9QZH MIvQ== X-Gm-Message-State: APzg51B/GRBEh88Ox6RhFtokcpfKYjRhyi/bWb+pBUoD6YxG2L/iVPrK dVtrhqU8HufpFFGSj8bSjUYPdFXcPy/yWQ== X-Google-Smtp-Source: ANB0VdbNP1fQ72PpfDiaHG/O0BMhFUwrYO36yzUokl9cLOXMxrYXzHjQlBoYhycV7Ud9B5n6iGPDXw== X-Received: by 2002:a19:96c3:: with SMTP id y186-v6mr5208479lfd.91.1534970491538; Wed, 22 Aug 2018 13:41:31 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:30 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 05/11] gpio: ep93xx: Rename has_debounce to has_irq Date: Wed, 22 Aug 2018 22:41:05 +0200 Message-Id: <20180822204111.9581-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This is closer to what the variable (per bank) actually means. We have the .gpio_to_irq() hook registered only when this is true. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 379f2573f794..a81d1e796912 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -297,25 +297,25 @@ struct ep93xx_gpio_bank { int data; int dir; int base; - bool has_debounce; + bool has_irq; }; -#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \ +#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \ { \ .label = _label, \ .data = _data, \ .dir = _dir, \ .base = _base, \ - .has_debounce = _debounce, \ + .has_irq = _has_irq, \ } static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), - EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */ + EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */ EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false), EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false), EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false), - EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */ EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false), EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false), }; @@ -370,7 +370,7 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, gc->label = bank->label; gc->base = bank->base; - if (bank->has_debounce) { + if (bank->has_irq) { gc->set_config = ep93xx_gpio_set_config; gc->to_irq = ep93xx_gpio_to_irq; } From patchwork Wed Aug 22 20:41:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961035 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UdBy42H8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbN6wSkz9s3C for ; Thu, 23 Aug 2018 06:41:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727467AbeHWAH7 (ORCPT ); Wed, 22 Aug 2018 20:07:59 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:46699 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAH7 (ORCPT ); Wed, 22 Aug 2018 20:07:59 -0400 Received: by mail-lj1-f193.google.com with SMTP id 203-v6so2428066ljj.13 for ; Wed, 22 Aug 2018 13:41:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+UwefDXh4P3wfTzsSfvtpWRGxLEovImVzBLhuTW/X0U=; b=UdBy42H8OeFnQDXC+PD47SlY612ms/viUbekBtgBeiJsRnBk6TYdldMVmkqDrw1nVx VdKHtbNUPmeWKIvuXVXKdaJXmkZmlQ/sa3n1yR7y2G14lZHnRA45C1v9nXuRNUpsDOhp bQKrg+O4YSvhqDxG4Lt1Up/LqpBmZXV92X7HQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+UwefDXh4P3wfTzsSfvtpWRGxLEovImVzBLhuTW/X0U=; b=oQi5DE11Hh0NdyzAO3kZoqA0r2qYd9n7nmjLA9UF5T0Nk2izd/UdpZf8sX07tLSKo8 hn+P+O1cJQ0vUy6+xzyOvGS6Q8F0nocQOvSMYbXa5egMyeDoQaKvirGI7JvS6VPTWUdQ jFY2ZMiQVmJWDsgych+hwxg7tSBBzPkZrEsTjtbr5hWS+2GWWAciHuR0agkOr2iLakDk z0IJYYiX1MZlWmLx5QYxIJd5clI0WMjMXf5AfSWfD+2kxpy4rkfzQPxyutDIPN36phyo Z82Q8BTs5/usoYDfaekI+LkzJJALc0ouNDzs/znFUNBAzO5gHhsSiHYza2ewmsiUpOm8 d2qA== X-Gm-Message-State: AOUpUlFKj0yPCPvRiYdKVIj+esUnwyWFip9aIp6krCLbA2wCN092xeKe oyGCO61ydmSdsICmUwvIzw77uw== X-Google-Smtp-Source: AA+uWPz9FROLpQzop+ZN1nW7ZT4FEeG5LtsAfw1Gut878LwhFN1Kd+8u95t1B1fL8BuHPNf2zZjj+A== X-Received: by 2002:a2e:9d45:: with SMTP id y5-v6mr40376932ljj.136.1534970494348; Wed, 22 Aug 2018 13:41:34 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:33 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 06/11] gpio: ep93xx: Properly call the chained IRQ handler Date: Wed, 22 Aug 2018 22:41:06 +0200 Message-Id: <20180822204111.9581-7-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The chained irq handler should call chained_irq_enter() and chained_irq_exit() before/after handling the chained IRQ. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index a81d1e796912..ce7e88df9cc5 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -88,9 +88,12 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned char status; int i; + chained_irq_enter(irqchip, desc); + status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { @@ -106,6 +109,8 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) generic_handle_irq(gpio_irq); } } + + chained_irq_exit(irqchip, desc); } static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) @@ -115,11 +120,14 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) * * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) */ + struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ int gpio_irq = gpio_to_irq(16) + port_f_idx; + chained_irq_enter(irqchip, desc); generic_handle_irq(gpio_irq); + chained_irq_exit(irqchip, desc); } static void ep93xx_gpio_irq_ack(struct irq_data *d) From patchwork Wed Aug 22 20:41:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961036 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="b+pdPFNF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbR2JKbz9s47 for ; Thu, 23 Aug 2018 06:41:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727478AbeHWAIC (ORCPT ); Wed, 22 Aug 2018 20:08:02 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:34234 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAIC (ORCPT ); Wed, 22 Aug 2018 20:08:02 -0400 Received: by mail-lf1-f65.google.com with SMTP id g9-v6so2411833lfh.1 for ; Wed, 22 Aug 2018 13:41:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AhUgbQTMYNb/DXLEkmtHE8Vl0sdfXM4cpGNlHdpUM0M=; b=b+pdPFNFHSRq9j5dq1jPj53Wj4vPjXnmzzn5Bc+5dr/A4pqCY5cN7n2EUO2yyOXt68 c+w5X3BndHuoWeQJIHSPHsOSoFN6BOTaY8R+nNJjeS/wSzGRX+FBCI74rGdAbc1XRcMG zmVrpftE4cRx1joWO+F2vwSDS1/V2/Mo5jchU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AhUgbQTMYNb/DXLEkmtHE8Vl0sdfXM4cpGNlHdpUM0M=; b=qtgU2EKMQZ7VubGTzEI9TQxduqH/fk9Ep/iC1wvniSUDXVxwDnmmJfbQiYUVrek8HY 5HKzkjv+0SKKmKzpnPCp2t1lpv/DDI2c+Q1uiHhk7EmFWMhan9/I6VYzlBR2MqIHsrAH 6W366vYXdeFfBvI4nyre51eyN1mRGtjikvQxp8hsVCmeoiD7CMxpNMWd6Osbv0o9BaVi pq8IH/1BAJNQUqDDx0luopxOSWfXRxZJEIOVHpZT6mdqK4Qe4Z2h7jrDhY52/sjUpNem 81XasKyl2ex/UvJEm/fhUg1p72maaN/tRgs3nM6scNSQdGahVk9+uvxIwyZFf1mWK0wc OCjw== X-Gm-Message-State: APzg51Bvaz81YMwxvw8TwtdRVtp0LxOQR3JPjmUJ4amps5scGxigu0t+ EjKR4e0tabuF52+154DFQ/Y5Zw== X-Google-Smtp-Source: ANB0VdbdtoVjiAGI23ZOAyVtmpAMq0B6O0yBRmp9vKjw7nniTiUDcXYfjU6Zxoan5mET8z7vUicBqQ== X-Received: by 2002:a19:9d51:: with SMTP id g78-v6mr1948278lfe.121.1534970497107; Wed, 22 Aug 2018 13:41:37 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:35 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 07/11] gpio: ep93xx: Do not pingpong irq numbers Date: Wed, 22 Aug 2018 22:41:07 +0200 Message-Id: <20180822204111.9581-8-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org For setting debounce config we want to write an offset in a per-gpiochip register, and we know which gpiochip we are on. Instead of a roundtrip over the IRQ number, figure out what port we are on for this GPIO chip, then index to the right register and write the value. This adds the ep93xx_gpio_port() that finds the port index from a struct gpio_chip * that we can later exploit to simplify more code. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index ce7e88df9cc5..3b235b25c028 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -68,12 +68,29 @@ static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port epg->base + int_en_register_offset[port]); } -static void ep93xx_gpio_int_debounce(struct ep93xx_gpio *epg, - unsigned int irq, bool enable) +static int ep93xx_gpio_port(struct gpio_chip *gc) { - int line = irq_to_gpio(irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int port = 0; + + while (gc != &epg->gc[port] && port < sizeof(epg->gc)) + port++; + + /* This should not happen but is there as a last safeguard */ + if (gc != &epg->gc[port]) { + pr_crit("can't find the GPIO port\n"); + return 0; + } + + return port; +} + +static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) +{ + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(offset); if (enable) gpio_int_debounce[port] |= port_mask; @@ -331,19 +348,13 @@ static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { - struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int gpio = gc->base + offset; - int irq = gpio_to_irq(gpio); u32 debounce; if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) return -ENOTSUPP; - if (irq < 0) - return -EINVAL; - debounce = pinconf_to_config_argument(config); - ep93xx_gpio_int_debounce(epg, irq, debounce ? true : false); + ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false); return 0; } From patchwork Wed Aug 22 20:41:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="TCMv3sVD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbV3XqZz9s3C for ; Thu, 23 Aug 2018 06:41:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727499AbeHWAIF (ORCPT ); Wed, 22 Aug 2018 20:08:05 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:46189 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAIF (ORCPT ); Wed, 22 Aug 2018 20:08:05 -0400 Received: by mail-lf1-f66.google.com with SMTP id e23-v6so2370180lfc.13 for ; Wed, 22 Aug 2018 13:41:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5jyCrEmH3jOgnJsJFUlr60/lZCJAbMRBBSgurEP30XM=; b=TCMv3sVDKGfy8VDf6PYFdYN4ITslozXIzuuYU7BPCy9WrQ6tceXUz9xeTajtpIZ0+Q /MbdyrFaAP93uP5U9goS+mfySSlehmkQLTvGuDcJewFveArJdt5JQzSmu0R6mTMUb6Go TACzAchTt6lU/4Gyz24YD++252DVAet+pjlWQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5jyCrEmH3jOgnJsJFUlr60/lZCJAbMRBBSgurEP30XM=; b=ATDzVN4PCb5Js+Ao6/5BQbJvyCDgdVkfQ4hzPKRSWaG+yhzeYS6SWxwHmKxf9+pj9a Kt1/i34iLU4tPDIU+RBnHK9y6G2H6QP1VwwhosGdWUnXkPDQjdozHOh7DlYo9gIVxTEZ XzWyM4iHp7h6/EHIOXcHWQ3+Fs7WDJdYRnLPAihRLP61akq7Dw9BD9O5js0EsnAzk/5X m/qKP3aR2jkUf2Y2VasMazO7tEWd2e2VRnroZ9WN/dvVkciKwJuQGU9AwuPsaDl6JG+f PObOKrLQuuEtKNp/3OJukKmsgUeqthw3KCC0VpZRKjliA+FjU3u7HBvoFo5aHVFA+V59 D4sw== X-Gm-Message-State: AOUpUlH2twsk/0mcndkt5dsn1tHNivkNneBNAXDYSS6kqSBMvjhianRj XVXHjIw9lVPwLxg+iMhEhCx3cg== X-Google-Smtp-Source: AA+uWPwqRI2Woo9eYNBpL71dBZD2cUUUv9cTQ7HhMNpRtuZvXW7SmzNpaADQISdwLdj5PS2hu2wJUQ== X-Received: by 2002:a19:c5:: with SMTP id 188-v6mr17605146lfa.45.1534970499762; Wed, 22 Aug 2018 13:41:39 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:38 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 08/11] gpio: ep93xx: Use the hwirq and port Date: Wed, 22 Aug 2018 22:41:08 +0200 Message-Id: <20180822204111.9581-9-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In the IRQ-related functions, switch to using the hwirq and port number found from the current struct gpio_chip * As the lower 3 bits of the IRQ number is identical to the lower 3 bits of the GPIO number we can cut some corners. Call directly into the gpiochip to set up the direction and read the input instead of using the consumer API. This enabled us to cut the confusing irq_to_gpio() macro that is a remnant of the old generic GPIO API as well. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3b235b25c028..b2139ec43ce2 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -16,11 +16,10 @@ #include #include #include +#include /* FIXME: this is here for gpio_to_irq() - get rid of this! */ #include -#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) - #define EP93XX_GPIO_F_INT_STATUS 0x5c #define EP93XX_GPIO_A_INT_STATUS 0xa0 #define EP93XX_GPIO_B_INT_STATUS 0xbc @@ -151,9 +150,8 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ @@ -167,9 +165,8 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ @@ -184,10 +181,9 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; + int port = ep93xx_gpio_port(gc); - gpio_int_unmasked[port] &= ~(1 << (line & 7)); + gpio_int_unmasked[port] &= ~BIT(d->irq & 7); ep93xx_gpio_update_int_params(epg, port); } @@ -195,10 +191,9 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; + int port = ep93xx_gpio_port(gc); - gpio_int_unmasked[port] |= 1 << (line & 7); + gpio_int_unmasked[port] |= BIT(d->irq & 7); ep93xx_gpio_update_int_params(epg, port); } @@ -211,12 +206,12 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - const int gpio = irq_to_gpio(d->irq); - const int port = gpio >> 3; - const int port_mask = 1 << (gpio & 7); + int port = ep93xx_gpio_port(gc); + int offset = d->irq & 7; + int port_mask = BIT(offset); irq_flow_handler_t handler; - gpio_direction_input(gpio); + gc->direction_input(gc, offset); switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -242,7 +237,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_BOTH: gpio_int_type1[port] |= port_mask; /* set initial polarity based on current input level */ - if (gpio_get_value(gpio)) + if (gc->get(gc, offset)) gpio_int_type2[port] &= ~port_mask; /* falling */ else gpio_int_type2[port] |= port_mask; /* rising */ From patchwork Wed Aug 22 20:41:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="El9C+R3N"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbY16QXz9s4Z for ; Thu, 23 Aug 2018 06:41:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727522AbeHWAII (ORCPT ); Wed, 22 Aug 2018 20:08:08 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:41574 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAIH (ORCPT ); Wed, 22 Aug 2018 20:08:07 -0400 Received: by mail-lf1-f68.google.com with SMTP id l26-v6so2388728lfc.8 for ; Wed, 22 Aug 2018 13:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RuBTtzm/UACCjyh36nPIVMHxuB2LtQV4+pKeChy29wY=; b=El9C+R3N9qsXXXgiWYSqhagvhsffXxkAjPynu3W28+DHZSQoeePZ9pz/nt8VZ0r2VV QPu2+KjQMpgHapuP5Fdik9NXHsypJ3u+s2cTtx83UZgtWDIvlkI4oBp+KJSQik7LmDy/ SCA3aVdpuXg7OZpOhUkbrB7uXb42dV3HhpPig= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RuBTtzm/UACCjyh36nPIVMHxuB2LtQV4+pKeChy29wY=; b=fHAYJd+yf5zWa4FuipNQj6jJ3ATNA+VbyGQj0oWyRRMMbttrBZU7g+nnh6wTQAyzi0 PPQ6cD7h+yTSICnTGihENC/bbWNovp/MAPBx8wTsD5M5K3HhJPSgNupZQMYOiewo0a81 lScREHeRAG71SFRtMZ+WIXytBuImkkkIw8nqag08KAQ4yp9D/AlaX7FTUQJ5VofaB95s BalJcs9XIjhO1cUw+2SLVyMeKALWSsFxmDmID06kvD/XqGgJe5smNx2VbdbG1zJt4LsX SR7aS5AXjSWq7W9jlHmZqmz/D+HApZTVu3Il6DySPYmUZdf+c/Bmlg5mF87g+5xi8LJ7 qQeQ== X-Gm-Message-State: AOUpUlGDPBcvm5b4hu6byJL98TBDR99F5iE/na+od5mDztohkvBN3Vbu XJG+myXSFcxDpm+gBsOPGrbGrA== X-Google-Smtp-Source: AA+uWPw2vjE7GPTwvor2RIQo7R6PH0yPZlUyZUcUl4f27SaQGPb7CLEhuFZ4zvcUgYXORPGsVr3QDw== X-Received: by 2002:a19:8f10:: with SMTP id r16-v6mr22306289lfd.1.1534970502674; Wed, 22 Aug 2018 13:41:42 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:41 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 09/11] gpio: ep93xx: Use for_each_set_bit() in IRQ handler Date: Wed, 22 Aug 2018 22:41:09 +0200 Message-Id: <20180822204111.9581-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This simplifies and standardizes the AB IRQ handler by using the for_each_set_bit() library function. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index b2139ec43ce2..1248d83f860b 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -105,25 +105,21 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); struct irq_chip *irqchip = irq_desc_get_chip(desc); - unsigned char status; - int i; + unsigned long stat; + int offset; chained_irq_enter(irqchip, desc); - status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); - for (i = 0; i < 8; i++) { - if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(0) + i; - generic_handle_irq(gpio_irq); - } + stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + for_each_set_bit(offset, &stat, 8) { + int gpio_irq = gpio_to_irq(0) + offset; + generic_handle_irq(gpio_irq); } - status = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for (i = 0; i < 8; i++) { - if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(8) + i; - generic_handle_irq(gpio_irq); - } + stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); + for_each_set_bit(offset, &stat, 8) { + int gpio_irq = gpio_to_irq(8) + offset; + generic_handle_irq(gpio_irq); } chained_irq_exit(irqchip, desc); From patchwork Wed Aug 22 20:41:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961039 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RhrllJJ+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbc5zwLz9s3C for ; Thu, 23 Aug 2018 06:41:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727545AbeHWAIL (ORCPT ); Wed, 22 Aug 2018 20:08:11 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:46708 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAIL (ORCPT ); Wed, 22 Aug 2018 20:08:11 -0400 Received: by mail-lj1-f193.google.com with SMTP id 203-v6so2428412ljj.13 for ; Wed, 22 Aug 2018 13:41:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=og9F5K3DV5Z4i7H1Ak0q8ntuvtl8V20+7qYiuklDr38=; b=RhrllJJ+9MgmonM/Nii3ozuXN1a5eVF3XqE+RI4BvRt4qpkklcpUpCa/IOPoaCsxzo sTgggxF7VZD5kdzcYqcO8yz6i/alvi/QwUt+QTF7EnS4zDwWFy4Bh6NZCZWnb9SqYJWz 0vx/zUiu8erdapj1IwZ5UO4ZB6eiwGQ71FSl8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=og9F5K3DV5Z4i7H1Ak0q8ntuvtl8V20+7qYiuklDr38=; b=UrrR28xobc+Ei5ciVD1SmjZH/Rh9MQ63wQSAPMotEtRAUFAyNk25il6hgc2X8xU0ey RuX9j1hQcEzKEjBnxUFC05CDyJQchD26Ygf+pISX0XlMw9fMPpQAQ9qdTul0QE5CAJCQ EEW8m62snBv1yjPXRCZvZkkOVfZYMVGMuSG5YUtdZ1+C8lydTgez3K2g6wAQK6GRBzkV v8CX8tc4Jc5D+CrQWlmnFlnC9CIBYIIJ+q5C71fqmYnZj0Xl8JsSDtnNyK1S4w97sGcA mXDdDrNAuhfJuzp+ym7dxwg0DedUhm/95ylZ/owW4woYRIYuMUg5Mg4C94+nryGJZIoa AJMw== X-Gm-Message-State: AOUpUlFRnPnclvgOqtPiMf88Tlr/+d85+c9qgrJdK7WtrVjqLBY0u6HO 4PZnHpQlM5Rey8Bjy6rC30CTug== X-Google-Smtp-Source: AA+uWPyIVNDk7CBc9xAkzNzDFR13RC3Dyw3Sh/ypCYAWdDapuTf+tyPxnjjF+V1fxEQ3ab78ZjbLiw== X-Received: by 2002:a2e:9bc9:: with SMTP id w9-v6mr32551315ljj.33.1534970505401; Wed, 22 Aug 2018 13:41:45 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:44 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 10/11] gpio: ep93xx: Cut gpio_to_irq() usage Date: Wed, 22 Aug 2018 22:41:10 +0200 Message-Id: <20180822204111.9581-11-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This removes the callback into the gpiolib creating a circular call to convert between GPIO numbers and IRQs and pushes the whole business into the driver, just using an array of IRQ bases for the three IRQ capable ports. This way we get rid of including that no driver should include. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 48 +++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 1248d83f860b..d45d8ac3b525 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -17,8 +17,6 @@ #include #include #include -/* FIXME: this is here for gpio_to_irq() - get rid of this! */ -#include #define EP93XX_GPIO_F_INT_STATUS 0x5c #define EP93XX_GPIO_A_INT_STATUS 0xa0 @@ -30,6 +28,15 @@ /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 +/* + * IRQ numbers used by this driver is 64 ..87 + * + * Map GPIO A0..A7 (0..7) to irq 64..71, + * B0..B7 (7..15) to irq 72..79, and + * F0..F7 (16..24) to irq 80..87. + */ +static unsigned int ep93xx_gpio_irq_base[3] = { 64, 72, 80 }; + struct ep93xx_gpio { void __iomem *base; struct gpio_chip gc[8]; @@ -112,13 +119,13 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for_each_set_bit(offset, &stat, 8) { - int gpio_irq = gpio_to_irq(0) + offset; + int gpio_irq = ep93xx_gpio_irq_base[0] + offset; generic_handle_irq(gpio_irq); } stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for_each_set_bit(offset, &stat, 8) { - int gpio_irq = gpio_to_irq(8) + offset; + int gpio_irq = ep93xx_gpio_irq_base[1] + offset; generic_handle_irq(gpio_irq); } @@ -130,12 +137,12 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) /* * map discontiguous hw irq range to continuous sw irq range: * - * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) + * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} */ struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ - int gpio_irq = gpio_to_irq(16) + port_f_idx; + int gpio_irq = ep93xx_gpio_irq_base[2] + port_f_idx; chained_irq_enter(irqchip, desc); generic_handle_irq(gpio_irq); @@ -268,27 +275,24 @@ static void ep93xx_gpio_init_irq(struct platform_device *pdev, int i; /* The A bank */ - for (gpio_irq = gpio_to_irq(0); - gpio_irq < gpio_to_irq(8); - gpio_irq++) { + for (i = 0; i < 8; i++) { + gpio_irq = ep93xx_gpio_irq_base[0] + i; irq_set_chip_data(gpio_irq, &epg->gc[0]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } /* The B bank */ - for (gpio_irq = gpio_to_irq(8); - gpio_irq < gpio_to_irq(16); - gpio_irq++) { + for (i = 0; i < 8; i++) { + gpio_irq = ep93xx_gpio_irq_base[1] + i; irq_set_chip_data(gpio_irq, &epg->gc[1]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } /* The F bank */ - for (gpio_irq = gpio_to_irq(16); - gpio_irq < gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); - gpio_irq++) { + for (i = 0; i < 8; i++) { + gpio_irq = ep93xx_gpio_irq_base[2] + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); @@ -350,19 +354,15 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, return 0; } -/* - * Map GPIO A0..A7 (0..7) to irq 64..71, - * B0..B7 (7..15) to irq 72..79, and - * F0..F7 (16..24) to irq 80..87. - */ -static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +static int ep93xx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { - int gpio = chip->base + offset; + int port = ep93xx_gpio_port(gc); - if (gpio > EP93XX_GPIO_LINE_MAX_IRQ) + /* Those are the ports supporting IRQ */ + if (port != 0 && port != 1 && port != 5) return -EINVAL; - return 64 + gpio; + return ep93xx_gpio_irq_base[port] + offset; } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, From patchwork Wed Aug 22 20:41:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 961040 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="XOzdbpjn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41wfbg1pKHz9s4Z for ; Thu, 23 Aug 2018 06:41:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727596AbeHWAIO (ORCPT ); Wed, 22 Aug 2018 20:08:14 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:35720 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727395AbeHWAIO (ORCPT ); Wed, 22 Aug 2018 20:08:14 -0400 Received: by mail-lj1-f193.google.com with SMTP id p10-v6so2459246ljg.2 for ; Wed, 22 Aug 2018 13:41:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3kMzcsDmjehMeekeRJxg79ESOEEpqoYxNeMq7Vevx4U=; b=XOzdbpjnNJwsf4eVftb2jgIXiAtMO//8SWCEP7uVAsdBujMXI0N5Fe2FB9PwqfVBJp HpUTL2zq6UERGFggBKcw6qQXCN/n6jAMCrFJGOg6ZxDQ+YMi/CoQLNzJc8GyEoyY6r8H IFXyQ9an0A73QTFEG1naYQRTl0a1SJbDxcapI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3kMzcsDmjehMeekeRJxg79ESOEEpqoYxNeMq7Vevx4U=; b=XqPS6a6sfv+xssaL4hWnLp/Guxt9FsGc0GGsDpMxYtjFGIBnueq/ez5mGA8TzxbbuW 9NPxaBSAAUcIpq+BpksqaRSJGFHdScu054dsnuv2x5u0xsorPL38SAj7XT7Y1RMzzn8N 2uzDtvJG4/4fHeCeshkOziZweNeEnkP+VGW6wIMMn48ThgqTZvAXEFxytg77+2mzt1h5 BGu0ih+Rdjd5uZvglxvTDJfdyFPnGRLCK06ap19yjkIvS3T369DTzb30Rd+EQDZixJpL 0D0+2NwA8aX5Bg86HK6i07WjapdQdOi76A5cw8uklcSPzBnhzrYRw2MPlXY1kTWvvVBE zhpw== X-Gm-Message-State: AOUpUlFrE1W6RFUKimbPOSIdbKGHEru45h9iqVymVg3NJIbSjM7ZuOzG XRmcy0GLyrNdbEecCB9OVk3gTHptkwjJbQ== X-Google-Smtp-Source: AA+uWPwizN5SKz4Du7jn+Gd4BTrIltHWlm0s93DA4kV5A1xFWvFuXaU7oG1QukJT0rZ6pyWutHF4yg== X-Received: by 2002:a2e:29da:: with SMTP id p87-v6mr36696887ljp.12.1534970508105; Wed, 22 Aug 2018 13:41:48 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:46 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 11/11] gpio: ep93xx: Switch A and B to use GPIOLIB_IRQCHIP Date: Wed, 22 Aug 2018 22:41:11 +0200 Message-Id: <20180822204111.9581-12-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We can quite easily switch banks/ports A and B to use GPIOLIB_IRQCHIP which is code that will be more careful about handling interrupt descriptors and use a proper irqdomain for translating the IRQs. This cuts down some code in favor of using the implementation inside gpiolib. Signed-off-by: Linus Walleij --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-ep93xx.c | 95 ++++++++++++++++++++------------------ 2 files changed, 51 insertions(+), 45 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 71c0ab46f216..afcd94613017 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -200,6 +200,7 @@ config GPIO_EP93XX def_bool y depends on ARCH_EP93XX select GPIO_GENERIC + select GPIOLIB_IRQCHIP config GPIO_EXAR tristate "Support for GPIO pins on XR17V352/354/358" diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index d45d8ac3b525..68a416fc3141 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -29,13 +29,10 @@ #define EP93XX_GPIO_LINE_MAX_IRQ 23 /* - * IRQ numbers used by this driver is 64 ..87 - * - * Map GPIO A0..A7 (0..7) to irq 64..71, - * B0..B7 (7..15) to irq 72..79, and - * F0..F7 (16..24) to irq 80..87. + * Static mapping of GPIO bank F IRQS: + * F0..F7 (16..24) to irq 80..87. */ -static unsigned int ep93xx_gpio_irq_base[3] = { 64, 72, 80 }; +#define EP93XX_GPIO_F_IRQ_BASE 80 struct ep93xx_gpio { void __iomem *base; @@ -117,17 +114,21 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) chained_irq_enter(irqchip, desc); + /* + * Dispatch the IRQs to the irqdomain of each A and B + * gpiochip irqdomains depending on what has fired. + * The tricky part is that the IRQ line is shared + * between bank A and B and each has their own gpiochip. + */ stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); - for_each_set_bit(offset, &stat, 8) { - int gpio_irq = ep93xx_gpio_irq_base[0] + offset; - generic_handle_irq(gpio_irq); - } + for_each_set_bit(offset, &stat, 8) + generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, + offset)); stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for_each_set_bit(offset, &stat, 8) { - int gpio_irq = ep93xx_gpio_irq_base[1] + offset; - generic_handle_irq(gpio_irq); - } + for_each_set_bit(offset, &stat, 8) + generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, + offset)); chained_irq_exit(irqchip, desc); } @@ -142,7 +143,7 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ - int gpio_irq = ep93xx_gpio_irq_base[2] + port_f_idx; + int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx; chained_irq_enter(irqchip, desc); generic_handle_irq(gpio_irq); @@ -268,44 +269,53 @@ static struct irq_chip ep93xx_gpio_irq_chip = { .irq_set_type = ep93xx_gpio_irq_type, }; -static void ep93xx_gpio_init_irq(struct platform_device *pdev, - struct ep93xx_gpio *epg) +static int ep93xx_gpio_init_irq(struct platform_device *pdev, + struct ep93xx_gpio *epg) { + int ab_parent_irq = platform_get_irq(pdev, 0); + struct device *dev = &pdev->dev; int gpio_irq; + int ret; int i; /* The A bank */ - for (i = 0; i < 8; i++) { - gpio_irq = ep93xx_gpio_irq_base[0] + i; - irq_set_chip_data(gpio_irq, &epg->gc[0]); - irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + ret = gpiochip_irqchip_add(&epg->gc[0], &ep93xx_gpio_irq_chip, + 64, handle_level_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "Could not add irqchip 0\n"); + return ret; } + gpiochip_set_chained_irqchip(&epg->gc[0], &ep93xx_gpio_irq_chip, + ab_parent_irq, + ep93xx_gpio_ab_irq_handler); + /* The B bank */ - for (i = 0; i < 8; i++) { - gpio_irq = ep93xx_gpio_irq_base[1] + i; - irq_set_chip_data(gpio_irq, &epg->gc[1]); - irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + ret = gpiochip_irqchip_add(&epg->gc[1], &ep93xx_gpio_irq_chip, + 72, handle_level_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "Could not add irqchip 1\n"); + return ret; } + gpiochip_set_chained_irqchip(&epg->gc[1], &ep93xx_gpio_irq_chip, + ab_parent_irq, + ep93xx_gpio_ab_irq_handler); + /* The F bank */ for (i = 0; i < 8; i++) { - gpio_irq = ep93xx_gpio_irq_base[2] + i; + gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } - irq_set_chained_handler_and_data(platform_get_irq(pdev, 0), - ep93xx_gpio_ab_irq_handler, - &epg->gc[0]); for (i = 1; i <= 8; i++) irq_set_chained_handler_and_data(platform_get_irq(pdev, i), ep93xx_gpio_f_irq_handler, &epg->gc[i]); + return 0; } @@ -354,15 +364,9 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, return 0; } -static int ep93xx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) { - int port = ep93xx_gpio_port(gc); - - /* Those are the ports supporting IRQ */ - if (port != 0 && port != 1 && port != 5) - return -EINVAL; - - return ep93xx_gpio_irq_base[port] + offset; + return EP93XX_GPIO_F_IRQ_BASE + offset; } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, @@ -380,10 +384,8 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, gc->label = bank->label; gc->base = bank->base; - if (bank->has_irq) { + if (bank->has_irq) gc->set_config = ep93xx_gpio_set_config; - gc->to_irq = ep93xx_gpio_to_irq; - } return devm_gpiochip_add_data(dev, gc, epg); } @@ -410,7 +412,10 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank)) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", - bank->label); + bank->label); + /* Only bank F has especially funky IRQ handling */ + if (i == 5) + gc->to_irq = ep93xx_gpio_f_to_irq; } ep93xx_gpio_init_irq(pdev, epg);