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[78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:08 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:31 +0200 Message-Id: <20171003134540.21625-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH 01/10] i386: hvf: move all hvf files in the same directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Just call it hvf/, no need for the "utils" suffix. Signed-off-by: Paolo Bonzini --- target/i386/Makefile.objs | 2 +- target/i386/cpu.h | 2 +- target/i386/{hvf-utils => hvf}/Makefile.objs | 1 + target/i386/{hvf-utils => hvf}/README.md | 0 target/i386/{ => hvf}/hvf-i386.h | 2 +- target/i386/{hvf-all.c => hvf/hvf.c} | 20 ++++++++++---------- target/i386/{hvf-utils => hvf}/vmcs.h | 0 target/i386/{hvf-utils => hvf}/vmx.h | 0 target/i386/{hvf-utils => hvf}/x86.c | 0 target/i386/{hvf-utils => hvf}/x86.h | 0 target/i386/{hvf-utils => hvf}/x86_cpuid.c | 0 target/i386/{hvf-utils => hvf}/x86_cpuid.h | 0 target/i386/{hvf-utils => hvf}/x86_decode.c | 0 target/i386/{hvf-utils => hvf}/x86_decode.h | 0 target/i386/{hvf-utils => hvf}/x86_descr.c | 0 target/i386/{hvf-utils => hvf}/x86_descr.h | 0 target/i386/{hvf-utils => hvf}/x86_emu.c | 0 target/i386/{hvf-utils => hvf}/x86_emu.h | 0 target/i386/{hvf-utils => hvf}/x86_flags.c | 0 target/i386/{hvf-utils => hvf}/x86_flags.h | 0 target/i386/{hvf-utils => hvf}/x86_gen.h | 0 target/i386/{hvf-utils => hvf}/x86_mmu.c | 0 target/i386/{hvf-utils => hvf}/x86_mmu.h | 0 target/i386/{hvf-utils => hvf}/x86_task.c | 20 ++++++++++---------- target/i386/{hvf-utils => hvf}/x86_task.h | 0 target/i386/{hvf-utils => hvf}/x86hvf.c | 0 target/i386/{hvf-utils => hvf}/x86hvf.h | 0 27 files changed, 24 insertions(+), 23 deletions(-) rename target/i386/{hvf-utils => hvf}/Makefile.objs (87%) rename target/i386/{hvf-utils => hvf}/README.md (100%) rename target/i386/{ => hvf}/hvf-i386.h (97%) rename target/i386/{hvf-all.c => hvf/hvf.c} (98%) rename target/i386/{hvf-utils => hvf}/vmcs.h (100%) rename target/i386/{hvf-utils => hvf}/vmx.h (100%) rename target/i386/{hvf-utils => hvf}/x86.c (100%) rename target/i386/{hvf-utils => hvf}/x86.h (100%) rename target/i386/{hvf-utils => hvf}/x86_cpuid.c (100%) rename target/i386/{hvf-utils => hvf}/x86_cpuid.h (100%) rename target/i386/{hvf-utils => hvf}/x86_decode.c (100%) rename target/i386/{hvf-utils => hvf}/x86_decode.h (100%) rename target/i386/{hvf-utils => hvf}/x86_descr.c (100%) rename target/i386/{hvf-utils => hvf}/x86_descr.h (100%) rename target/i386/{hvf-utils => hvf}/x86_emu.c (100%) rename target/i386/{hvf-utils => hvf}/x86_emu.h (100%) rename target/i386/{hvf-utils => hvf}/x86_flags.c (100%) rename target/i386/{hvf-utils => hvf}/x86_flags.h (100%) rename target/i386/{hvf-utils => hvf}/x86_gen.h (100%) rename target/i386/{hvf-utils => hvf}/x86_mmu.c (100%) rename target/i386/{hvf-utils => hvf}/x86_mmu.h (100%) rename target/i386/{hvf-utils => hvf}/x86_task.c (95%) rename target/i386/{hvf-utils => hvf}/x86_task.h (100%) rename target/i386/{hvf-utils => hvf}/x86hvf.c (100%) rename target/i386/{hvf-utils => hvf}/x86hvf.h (100%) diff --git a/target/i386/Makefile.objs b/target/i386/Makefile.objs index 0bef89c099..44103a693b 100644 --- a/target/i386/Makefile.objs +++ b/target/i386/Makefile.objs @@ -12,5 +12,5 @@ obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-windows.o endif ifdef CONFIG_DARWIN obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-darwin.o -obj-$(CONFIG_HVF) += hvf-utils/ hvf-all.o +obj-$(CONFIG_HVF) += hvf/ endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0ae99ef424..238d3e3535 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,7 +24,7 @@ #include "cpu-qom.h" #include "hyperv-proto.h" #if defined(CONFIG_HVF) -#include "target/i386/hvf-utils/x86.h" +#include "target/i386/hvf/x86.h" #endif #ifdef TARGET_X86_64 diff --git a/target/i386/hvf-utils/Makefile.objs b/target/i386/hvf/Makefile.objs similarity index 87% rename from target/i386/hvf-utils/Makefile.objs rename to target/i386/hvf/Makefile.objs index 79d8969ca8..927b86bc67 100644 --- a/target/i386/hvf-utils/Makefile.objs +++ b/target/i386/hvf/Makefile.objs @@ -1 +1,2 @@ +obj-y += hvf.o obj-y += x86.o x86_cpuid.o x86_decode.o x86_descr.o x86_emu.o x86_flags.o x86_mmu.o x86hvf.o x86_task.o diff --git a/target/i386/hvf-utils/README.md b/target/i386/hvf/README.md similarity index 100% rename from target/i386/hvf-utils/README.md rename to target/i386/hvf/README.md diff --git a/target/i386/hvf-i386.h b/target/i386/hvf/hvf-i386.h similarity index 97% rename from target/i386/hvf-i386.h rename to target/i386/hvf/hvf-i386.h index 797718ce34..2232501552 100644 --- a/target/i386/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -18,7 +18,7 @@ #include "sysemu/hvf.h" #include "cpu.h" -#include "hvf-utils/x86.h" +#include "x86.h" #define HVF_MAX_VCPU 0x10 #define MAX_VM_ID 0x40 diff --git a/target/i386/hvf-all.c b/target/i386/hvf/hvf.c similarity index 98% rename from target/i386/hvf-all.c rename to target/i386/hvf/hvf.c index 81d9b64eae..863226cc9a 100644 --- a/target/i386/hvf-all.c +++ b/target/i386/hvf/hvf.c @@ -24,16 +24,16 @@ #include "sysemu/hvf.h" #include "hvf-i386.h" -#include "hvf-utils/vmcs.h" -#include "hvf-utils/vmx.h" -#include "hvf-utils/x86.h" -#include "hvf-utils/x86_descr.h" -#include "hvf-utils/x86_mmu.h" -#include "hvf-utils/x86_decode.h" -#include "hvf-utils/x86_emu.h" -#include "hvf-utils/x86_cpuid.h" -#include "hvf-utils/x86_task.h" -#include "hvf-utils/x86hvf.h" +#include "vmcs.h" +#include "vmx.h" +#include "x86.h" +#include "x86_descr.h" +#include "x86_mmu.h" +#include "x86_decode.h" +#include "x86_emu.h" +#include "x86_cpuid.h" +#include "x86_task.h" +#include "x86hvf.h" #include #include diff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf/vmcs.h similarity index 100% rename from target/i386/hvf-utils/vmcs.h rename to target/i386/hvf/vmcs.h diff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf/vmx.h similarity index 100% rename from target/i386/hvf-utils/vmx.h rename to target/i386/hvf/vmx.h diff --git a/target/i386/hvf-utils/x86.c b/target/i386/hvf/x86.c similarity index 100% rename from target/i386/hvf-utils/x86.c rename to target/i386/hvf/x86.c diff --git a/target/i386/hvf-utils/x86.h b/target/i386/hvf/x86.h similarity index 100% rename from target/i386/hvf-utils/x86.h rename to target/i386/hvf/x86.h diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c similarity index 100% rename from target/i386/hvf-utils/x86_cpuid.c rename to target/i386/hvf/x86_cpuid.c diff --git a/target/i386/hvf-utils/x86_cpuid.h b/target/i386/hvf/x86_cpuid.h similarity index 100% rename from target/i386/hvf-utils/x86_cpuid.h rename to target/i386/hvf/x86_cpuid.h diff --git a/target/i386/hvf-utils/x86_decode.c b/target/i386/hvf/x86_decode.c similarity index 100% rename from target/i386/hvf-utils/x86_decode.c rename to target/i386/hvf/x86_decode.c diff --git a/target/i386/hvf-utils/x86_decode.h b/target/i386/hvf/x86_decode.h similarity index 100% rename from target/i386/hvf-utils/x86_decode.h rename to target/i386/hvf/x86_decode.h diff --git a/target/i386/hvf-utils/x86_descr.c b/target/i386/hvf/x86_descr.c similarity index 100% rename from target/i386/hvf-utils/x86_descr.c rename to target/i386/hvf/x86_descr.c diff --git a/target/i386/hvf-utils/x86_descr.h b/target/i386/hvf/x86_descr.h similarity index 100% rename from target/i386/hvf-utils/x86_descr.h rename to target/i386/hvf/x86_descr.h diff --git a/target/i386/hvf-utils/x86_emu.c b/target/i386/hvf/x86_emu.c similarity index 100% rename from target/i386/hvf-utils/x86_emu.c rename to target/i386/hvf/x86_emu.c diff --git a/target/i386/hvf-utils/x86_emu.h b/target/i386/hvf/x86_emu.h similarity index 100% rename from target/i386/hvf-utils/x86_emu.h rename to target/i386/hvf/x86_emu.h diff --git a/target/i386/hvf-utils/x86_flags.c b/target/i386/hvf/x86_flags.c similarity index 100% rename from target/i386/hvf-utils/x86_flags.c rename to target/i386/hvf/x86_flags.c diff --git a/target/i386/hvf-utils/x86_flags.h b/target/i386/hvf/x86_flags.h similarity index 100% rename from target/i386/hvf-utils/x86_flags.h rename to target/i386/hvf/x86_flags.h diff --git a/target/i386/hvf-utils/x86_gen.h b/target/i386/hvf/x86_gen.h similarity index 100% rename from target/i386/hvf-utils/x86_gen.h rename to target/i386/hvf/x86_gen.h diff --git a/target/i386/hvf-utils/x86_mmu.c b/target/i386/hvf/x86_mmu.c similarity index 100% rename from target/i386/hvf-utils/x86_mmu.c rename to target/i386/hvf/x86_mmu.c diff --git a/target/i386/hvf-utils/x86_mmu.h b/target/i386/hvf/x86_mmu.h similarity index 100% rename from target/i386/hvf-utils/x86_mmu.h rename to target/i386/hvf/x86_mmu.h diff --git a/target/i386/hvf-utils/x86_task.c b/target/i386/hvf/x86_task.c similarity index 95% rename from target/i386/hvf-utils/x86_task.c rename to target/i386/hvf/x86_task.c index 1a2646437a..22fde7fc39 100644 --- a/target/i386/hvf-utils/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -12,16 +12,16 @@ #include "sysemu/hvf.h" #include "hvf-i386.h" -#include "hvf-utils/vmcs.h" -#include "hvf-utils/vmx.h" -#include "hvf-utils/x86.h" -#include "hvf-utils/x86_descr.h" -#include "hvf-utils/x86_mmu.h" -#include "hvf-utils/x86_decode.h" -#include "hvf-utils/x86_emu.h" -#include "hvf-utils/x86_cpuid.h" -#include "hvf-utils/x86_task.h" -#include "hvf-utils/x86hvf.h" +#include "vmcs.h" +#include "vmx.h" +#include "x86.h" +#include "x86_descr.h" +#include "x86_mmu.h" +#include "x86_decode.h" +#include "x86_emu.h" +#include "x86_cpuid.h" +#include "x86_task.h" +#include "x86hvf.h" #include #include diff --git a/target/i386/hvf-utils/x86_task.h b/target/i386/hvf/x86_task.h similarity index 100% rename from target/i386/hvf-utils/x86_task.h rename to target/i386/hvf/x86_task.h diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf/x86hvf.c similarity index 100% rename from target/i386/hvf-utils/x86hvf.c rename to target/i386/hvf/x86hvf.c diff --git a/target/i386/hvf-utils/x86hvf.h b/target/i386/hvf/x86hvf.h similarity index 100% rename from target/i386/hvf-utils/x86hvf.h rename to target/i386/hvf/x86hvf.h From patchwork Tue Oct 3 13:45:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820889 Return-Path: X-Original-To: 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[78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:09 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:32 +0200 Message-Id: <20171003134540.21625-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH 02/10] i386: hvf: header cleanup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Remove inclusions of system headers and avoid "pragma once". Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86.h | 8 +++----- target/i386/hvf/x86_decode.h | 9 ++++----- target/i386/hvf/x86_descr.h | 5 ++++- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index 7fd8fede80..ae957fc895 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -16,12 +16,9 @@ * License along with this program; if not, see . */ -#pragma once +#ifndef HVF_X86_H +#define HVF_X86_H 1 -#include -#include -#include -#include #include "qemu-common.h" #include "x86_gen.h" @@ -474,3 +471,4 @@ static inline uint64_t rdtscp(void) return tsc; } +#endif diff --git a/target/i386/hvf/x86_decode.h b/target/i386/hvf/x86_decode.h index 329131360f..50957819f6 100644 --- a/target/i386/hvf/x86_decode.h +++ b/target/i386/hvf/x86_decode.h @@ -15,12 +15,9 @@ * License along with this program; if not, see . */ -#pragma once +#ifndef HVF_X86_DECODE_H +#define HVF_X86_DECODE_H 1 -#include -#include -#include -#include #include "qemu-common.h" #include "x86.h" #include "cpu.h" @@ -323,3 +320,5 @@ void calc_modrm_operand64(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op); void set_addressing_size(CPUX86State *env, struct x86_decode *decode); void set_operand_size(CPUX86State *env, struct x86_decode *decode); + +#endif diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h index 1285dd3897..034d8e95c5 100644 --- a/target/i386/hvf/x86_descr.h +++ b/target/i386/hvf/x86_descr.h @@ -16,7 +16,8 @@ * License along with this program; if not, see . */ -#pragma once +#ifndef HVF_X86_DESCR_H +#define HVF_X86_DESCR_H 1 #include "x86.h" @@ -53,3 +54,5 @@ uint32_t vmx_read_segment_ar(CPUState *cpu, x86_reg_segment seg); void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc); + +#endif From patchwork Tue Oct 3 13:45:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820892 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:33 +0200 Message-Id: <20171003134540.21625-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH 03/10] i386: hvf: unify register enums between HVF and the rest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 60 +++++++++++------- target/i386/hvf/vmx.h | 10 +-- target/i386/hvf/x86.c | 10 +-- target/i386/hvf/x86.h | 145 +++++++++++++------------------------------ target/i386/hvf/x86_decode.c | 80 ++++++++++++------------ target/i386/hvf/x86_decode.h | 2 +- target/i386/hvf/x86_descr.c | 26 ++++---- target/i386/hvf/x86_descr.h | 16 ++--- target/i386/hvf/x86_emu.c | 66 ++++++++++---------- target/i386/hvf/x86_task.c | 48 +++++++------- target/i386/hvf/x86hvf.c | 32 +++++----- 11 files changed, 224 insertions(+), 271 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 238d3e3535..fb38de7b0e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -59,30 +59,42 @@ #include "fpu/softfloat.h" #endif -#define R_EAX 0 -#define R_ECX 1 -#define R_EDX 2 -#define R_EBX 3 -#define R_ESP 4 -#define R_EBP 5 -#define R_ESI 6 -#define R_EDI 7 - -#define R_AL 0 -#define R_CL 1 -#define R_DL 2 -#define R_BL 3 -#define R_AH 4 -#define R_CH 5 -#define R_DH 6 -#define R_BH 7 - -#define R_ES 0 -#define R_CS 1 -#define R_SS 2 -#define R_DS 3 -#define R_FS 4 -#define R_GS 5 +enum { + R_RAX = 0, + R_RCX = 1, + R_RDX = 2, + R_RBX = 3, + R_RSP = 4, + R_RBP = 5, + R_RSI = 6, + R_RDI = 7, + R_R8 = 8, + R_R9 = 9, + R_R10 = 10, + R_R11 = 11, + R_R12 = 12, + R_R13 = 13, + R_R14 = 14, + R_R15 = 15, + + R_AL = 0, + R_CL = 1, + R_DL = 2, + R_BL = 3, + R_AH = 4, + R_CH = 5, + R_DH = 6, + R_BH = 7, +}; + +typedef enum X86Seg { + R_ES = 0, + R_CS = 1, + R_SS = 2, + R_DS = 3, + R_FS = 4, + R_GS = 5, +} X86Seg; /* segment descriptor fields */ #define DESC_G_SHIFT 23 diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 102075d0d4..9dfcd2f2eb 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -88,14 +88,14 @@ static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer) { uint64_t entry_ctls; - efer |= EFER_LMA; + efer |= MSR_EFER_LMA; wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | VM_ENTRY_GUEST_LMA); uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS); - if ((efer & EFER_LME) && + if ((efer & MSR_EFER_LME) && (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS); @@ -109,7 +109,7 @@ static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer) entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA); - efer &= ~EFER_LMA; + efer &= ~MSR_EFER_LMA; wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); } @@ -121,7 +121,7 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0) uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0); if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && - !(efer & EFER_LME)) { + !(efer & MSR_EFER_LME)) { address_space_rw(&address_space_memory, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, MEMTXATTRS_UNSPECIFIED, @@ -138,7 +138,7 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0) cr0 &= ~CR0_CD; wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE | CR0_ET); - if (efer & EFER_LME) { + if (efer & MSR_EFER_LME) { if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG)) { enter_long_mode(vcpu, cr0, efer); } diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 625ea6cac0..ca0ec2968a 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -134,13 +134,13 @@ bool x86_is_v8086(struct CPUState *cpu) bool x86_is_long_mode(struct CPUState *cpu) { - return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & EFER_LMA; + return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } bool x86_is_long64_mode(struct CPUState *cpu) { struct vmx_segment desc; - vmx_read_segment_descriptor(cpu, &desc, REG_SEG_CS); + vmx_read_segment_descriptor(cpu, &desc, R_CS); return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1); } @@ -157,13 +157,13 @@ bool x86_is_pae_enabled(struct CPUState *cpu) return cr4 & CR4_PAE; } -addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg) +addr_t linear_addr(struct CPUState *cpu, addr_t addr, X86Seg seg) { return vmx_read_segment_base(cpu, seg) + addr; } addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, - x86_reg_segment seg) + X86Seg seg) { switch (size) { case 2: @@ -180,5 +180,5 @@ addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, addr_t linear_rip(struct CPUState *cpu, addr_t rip) { - return linear_addr(cpu, rip, REG_SEG_CS); + return linear_addr(cpu, rip, R_CS); } diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index ae957fc895..650bb718bf 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -22,57 +22,6 @@ #include "qemu-common.h" #include "x86_gen.h" -/* exceptions */ -typedef enum x86_exception { - EXCEPTION_DE, /* divide error */ - EXCEPTION_DB, /* debug fault */ - EXCEPTION_NMI, /* non-maskable interrupt */ - EXCEPTION_BP, /* breakpoint trap */ - EXCEPTION_OF, /* overflow trap */ - EXCEPTION_BR, /* boundary range exceeded fault */ - EXCEPTION_UD, /* undefined opcode */ - EXCEPTION_NM, /* device not available */ - EXCEPTION_DF, /* double fault */ - EXCEPTION_RSVD, /* not defined */ - EXCEPTION_TS, /* invalid TSS fault */ - EXCEPTION_NP, /* not present fault */ - EXCEPTION_GP, /* general protection fault */ - EXCEPTION_PF, /* page fault */ - EXCEPTION_RSVD2, /* not defined */ -} x86_exception; - -/* general purpose regs */ -typedef enum x86_reg_name { - REG_RAX = 0, - REG_RCX = 1, - REG_RDX = 2, - REG_RBX = 3, - REG_RSP = 4, - REG_RBP = 5, - REG_RSI = 6, - REG_RDI = 7, - REG_R8 = 8, - REG_R9 = 9, - REG_R10 = 10, - REG_R11 = 11, - REG_R12 = 12, - REG_R13 = 13, - REG_R14 = 14, - REG_R15 = 15, -} x86_reg_name; - -/* segment regs */ -typedef enum x86_reg_segment { - REG_SEG_ES = 0, - REG_SEG_CS = 1, - REG_SEG_SS = 2, - REG_SEG_DS = 3, - REG_SEG_FS = 4, - REG_SEG_GS = 5, - REG_SEG_LDTR = 6, - REG_SEG_TR = 7, -} x86_reg_segment; - typedef struct x86_register { union { struct { @@ -154,15 +103,6 @@ typedef struct x86_reg_flags { }; } __attribute__ ((__packed__)) x86_reg_flags; -typedef enum x86_reg_efer { - EFER_SCE = (1L << 0), - EFER_LME = (1L << 8), - EFER_LMA = (1L << 10), - EFER_NXE = (1L << 11), - EFER_SVME = (1L << 12), - EFER_FXSR = (1L << 14), -} x86_reg_efer; - typedef struct x86_efer { uint64_t efer; } __attribute__ ((__packed__)) x86_efer; @@ -384,54 +324,54 @@ struct hvf_xsave_buf { #define EFLAGS(cpu) (cpu->hvf_emul->rflags.eflags) #define RRX(cpu, reg) (cpu->hvf_emul->regs[reg].rrx) -#define RAX(cpu) RRX(cpu, REG_RAX) -#define RCX(cpu) RRX(cpu, REG_RCX) -#define RDX(cpu) RRX(cpu, REG_RDX) -#define RBX(cpu) RRX(cpu, REG_RBX) -#define RSP(cpu) RRX(cpu, REG_RSP) -#define RBP(cpu) RRX(cpu, REG_RBP) -#define RSI(cpu) RRX(cpu, REG_RSI) -#define RDI(cpu) RRX(cpu, REG_RDI) -#define R8(cpu) RRX(cpu, REG_R8) -#define R9(cpu) RRX(cpu, REG_R9) -#define R10(cpu) RRX(cpu, REG_R10) -#define R11(cpu) RRX(cpu, REG_R11) -#define R12(cpu) RRX(cpu, REG_R12) -#define R13(cpu) RRX(cpu, REG_R13) -#define R14(cpu) RRX(cpu, REG_R14) -#define R15(cpu) RRX(cpu, REG_R15) +#define RAX(cpu) RRX(cpu, R_RAX) +#define RCX(cpu) RRX(cpu, R_RCX) +#define RDX(cpu) RRX(cpu, R_RDX) +#define RBX(cpu) RRX(cpu, R_RBX) +#define RSP(cpu) RRX(cpu, R_RSP) +#define RBP(cpu) RRX(cpu, R_RBP) +#define RSI(cpu) RRX(cpu, R_RSI) +#define RDI(cpu) RRX(cpu, R_RDI) +#define R8(cpu) RRX(cpu, R_R8) +#define R9(cpu) RRX(cpu, R_R9) +#define R10(cpu) RRX(cpu, R_R10) +#define R11(cpu) RRX(cpu, R_R11) +#define R12(cpu) RRX(cpu, R_R12) +#define R13(cpu) RRX(cpu, R_R13) +#define R14(cpu) RRX(cpu, R_R14) +#define R15(cpu) RRX(cpu, R_R15) #define ERX(cpu, reg) (cpu->hvf_emul->regs[reg].erx) -#define EAX(cpu) ERX(cpu, REG_RAX) -#define ECX(cpu) ERX(cpu, REG_RCX) -#define EDX(cpu) ERX(cpu, REG_RDX) -#define EBX(cpu) ERX(cpu, REG_RBX) -#define ESP(cpu) ERX(cpu, REG_RSP) -#define EBP(cpu) ERX(cpu, REG_RBP) -#define ESI(cpu) ERX(cpu, REG_RSI) -#define EDI(cpu) ERX(cpu, REG_RDI) +#define EAX(cpu) ERX(cpu, R_RAX) +#define ECX(cpu) ERX(cpu, R_RCX) +#define EDX(cpu) ERX(cpu, R_RDX) +#define EBX(cpu) ERX(cpu, R_RBX) +#define ESP(cpu) ERX(cpu, R_RSP) +#define EBP(cpu) ERX(cpu, R_RBP) +#define ESI(cpu) ERX(cpu, R_RSI) +#define EDI(cpu) ERX(cpu, R_RDI) #define RX(cpu, reg) (cpu->hvf_emul->regs[reg].rx) -#define AX(cpu) RX(cpu, REG_RAX) -#define CX(cpu) RX(cpu, REG_RCX) -#define DX(cpu) RX(cpu, REG_RDX) -#define BP(cpu) RX(cpu, REG_RBP) -#define SP(cpu) RX(cpu, REG_RSP) -#define BX(cpu) RX(cpu, REG_RBX) -#define SI(cpu) RX(cpu, REG_RSI) -#define DI(cpu) RX(cpu, REG_RDI) +#define AX(cpu) RX(cpu, R_RAX) +#define CX(cpu) RX(cpu, R_RCX) +#define DX(cpu) RX(cpu, R_RDX) +#define BP(cpu) RX(cpu, R_RBP) +#define SP(cpu) RX(cpu, R_RSP) +#define BX(cpu) RX(cpu, R_RBX) +#define SI(cpu) RX(cpu, R_RSI) +#define DI(cpu) RX(cpu, R_RDI) #define RL(cpu, reg) (cpu->hvf_emul->regs[reg].lx) -#define AL(cpu) RL(cpu, REG_RAX) -#define CL(cpu) RL(cpu, REG_RCX) -#define DL(cpu) RL(cpu, REG_RDX) -#define BL(cpu) RL(cpu, REG_RBX) +#define AL(cpu) RL(cpu, R_RAX) +#define CL(cpu) RL(cpu, R_RCX) +#define DL(cpu) RL(cpu, R_RDX) +#define BL(cpu) RL(cpu, R_RBX) #define RH(cpu, reg) (cpu->hvf_emul->regs[reg].hx) -#define AH(cpu) RH(cpu, REG_RAX) -#define CH(cpu) RH(cpu, REG_RCX) -#define DH(cpu) RH(cpu, REG_RDX) -#define BH(cpu) RH(cpu, REG_RBX) +#define AH(cpu) RH(cpu, R_RAX) +#define CH(cpu) RH(cpu, R_RCX) +#define DH(cpu) RH(cpu, R_RDX) +#define BH(cpu) RH(cpu, R_RBX) /* deal with GDT/LDT descriptors in memory */ bool x86_read_segment_descriptor(struct CPUState *cpu, @@ -453,9 +393,10 @@ bool x86_is_long64_mode(struct CPUState *cpu); bool x86_is_paging_mode(struct CPUState *cpu); bool x86_is_pae_enabled(struct CPUState *cpu); -addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg); +enum X86Seg; +addr_t linear_addr(struct CPUState *cpu, addr_t addr, enum X86Seg seg); addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, - x86_reg_segment seg); + enum X86Seg seg); addr_t linear_rip(struct CPUState *cpu, addr_t rip); static inline uint64_t rdtscp(void) diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 623c051339..86e7c4ee7a 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -120,7 +120,7 @@ static void decode_rax(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op) { op->type = X86_VAR_REG; - op->reg = REG_RAX; + op->reg = R_RAX; op->ptr = get_reg_ref(env, op->reg, 0, decode->operand_size); } @@ -212,22 +212,22 @@ static void decode_pushseg(CPUX86State *env, struct x86_decode *decode) decode->op[0].type = X86_VAR_REG; switch (op) { case 0xe: - decode->op[0].reg = REG_SEG_CS; + decode->op[0].reg = R_CS; break; case 0x16: - decode->op[0].reg = REG_SEG_SS; + decode->op[0].reg = R_SS; break; case 0x1e: - decode->op[0].reg = REG_SEG_DS; + decode->op[0].reg = R_DS; break; case 0x06: - decode->op[0].reg = REG_SEG_ES; + decode->op[0].reg = R_ES; break; case 0xa0: - decode->op[0].reg = REG_SEG_FS; + decode->op[0].reg = R_FS; break; case 0xa8: - decode->op[0].reg = REG_SEG_GS; + decode->op[0].reg = R_GS; break; } } @@ -239,22 +239,22 @@ static void decode_popseg(CPUX86State *env, struct x86_decode *decode) decode->op[0].type = X86_VAR_REG; switch (op) { case 0xf: - decode->op[0].reg = REG_SEG_CS; + decode->op[0].reg = R_CS; break; case 0x17: - decode->op[0].reg = REG_SEG_SS; + decode->op[0].reg = R_SS; break; case 0x1f: - decode->op[0].reg = REG_SEG_DS; + decode->op[0].reg = R_DS; break; case 0x07: - decode->op[0].reg = REG_SEG_ES; + decode->op[0].reg = R_ES; break; case 0xa1: - decode->op[0].reg = REG_SEG_FS; + decode->op[0].reg = R_FS; break; case 0xa9: - decode->op[0].reg = REG_SEG_GS; + decode->op[0].reg = R_GS; break; } } @@ -411,7 +411,7 @@ static void decode_rcx(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op) { op->type = X86_VAR_REG; - op->reg = REG_RCX; + op->reg = R_RCX; op->ptr = get_reg_ref(env, op->reg, decode->rex.b, decode->operand_size); } @@ -1638,7 +1638,7 @@ void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op) { addr_t ptr = 0; - x86_reg_segment seg = REG_SEG_DS; + X86Seg seg = R_DS; if (!decode->modrm.mod && 6 == decode->modrm.rm) { op->ptr = (uint16_t)decode->displacement; @@ -1658,11 +1658,11 @@ void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode, break; case 2: ptr += BP(env) + SI(env); - seg = REG_SEG_SS; + seg = R_SS; break; case 3: ptr += BP(env) + DI(env); - seg = REG_SEG_SS; + seg = R_SS; break; case 4: ptr += SI(env); @@ -1672,7 +1672,7 @@ void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode, break; case 6: ptr += BP(env); - seg = REG_SEG_SS; + seg = R_SS; break; case 7: ptr += BX(env); @@ -1692,7 +1692,7 @@ addr_t get_reg_ref(CPUX86State *env, int reg, int is_extended, int size) int which = 0; if (is_extended) { - reg |= REG_R8; + reg |= R_R8; } @@ -1722,7 +1722,7 @@ addr_t get_reg_val(CPUX86State *env, int reg, int is_extended, int size) } static addr_t get_sib_val(CPUX86State *env, struct x86_decode *decode, - x86_reg_segment *sel) + X86Seg *sel) { addr_t base = 0; addr_t scaled_index = 0; @@ -1730,23 +1730,23 @@ static addr_t get_sib_val(CPUX86State *env, struct x86_decode *decode, int base_reg = decode->sib.base; int index_reg = decode->sib.index; - *sel = REG_SEG_DS; + *sel = R_DS; - if (decode->modrm.mod || base_reg != REG_RBP) { + if (decode->modrm.mod || base_reg != R_RBP) { if (decode->rex.b) { - base_reg |= REG_R8; + base_reg |= R_R8; } - if (REG_RSP == base_reg || REG_RBP == base_reg) { - *sel = REG_SEG_SS; + if (base_reg == R_RSP || base_reg == R_RBP) { + *sel = R_SS; } base = get_reg_val(env, decode->sib.base, decode->rex.b, addr_size); } if (decode->rex.x) { - index_reg |= REG_R8; + index_reg |= R_R8; } - if (index_reg != REG_RSP) { + if (index_reg != R_RSP) { scaled_index = get_reg_val(env, index_reg, decode->rex.x, addr_size) << decode->sib.scale; } @@ -1756,7 +1756,7 @@ static addr_t get_sib_val(CPUX86State *env, struct x86_decode *decode, void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op) { - x86_reg_segment seg = REG_SEG_DS; + X86Seg seg = R_DS; addr_t ptr = 0; int addr_size = decode->addressing_size; @@ -1773,8 +1773,8 @@ void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode, ptr = decode->displacement; } } else { - if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm) { - seg = REG_SEG_SS; + if (decode->modrm.rm == R_RBP || decode->modrm.rm == R_RSP) { + seg = R_SS; } ptr += get_reg_val(env, decode->modrm.rm, decode->rex.b, addr_size); } @@ -1789,7 +1789,7 @@ void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode, void calc_modrm_operand64(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op) { - x86_reg_segment seg = REG_SEG_DS; + X86Seg seg = R_DS; int32_t offset = 0; int mod = decode->modrm.mod; int rm = decode->modrm.rm; @@ -1894,7 +1894,7 @@ void set_addressing_size(CPUX86State *env, struct x86_decode *decode) } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, REG_SEG_CS); + vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->addr_size_override) { @@ -1931,7 +1931,7 @@ void set_operand_size(CPUX86State *env, struct x86_decode *decode) } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, REG_SEG_CS); + vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->op_size_override) { @@ -2158,26 +2158,26 @@ const char *decode_cmd_to_string(enum x86_decode_cmd cmd) } addr_t decode_linear_addr(CPUX86State *env, struct x86_decode *decode, - addr_t addr, x86_reg_segment seg) + addr_t addr, X86Seg seg) { switch (decode->segment_override) { case PREFIX_CS_SEG_OVEERIDE: - seg = REG_SEG_CS; + seg = R_CS; break; case PREFIX_SS_SEG_OVEERIDE: - seg = REG_SEG_SS; + seg = R_SS; break; case PREFIX_DS_SEG_OVEERIDE: - seg = REG_SEG_DS; + seg = R_DS; break; case PREFIX_ES_SEG_OVEERIDE: - seg = REG_SEG_ES; + seg = R_ES; break; case PREFIX_FS_SEG_OVEERIDE: - seg = REG_SEG_FS; + seg = R_FS; break; case PREFIX_GS_SEG_OVEERIDE: - seg = REG_SEG_GS; + seg = R_GS; break; default: break; diff --git a/target/i386/hvf/x86_decode.h b/target/i386/hvf/x86_decode.h index 50957819f6..1b73a1f5b6 100644 --- a/target/i386/hvf/x86_decode.h +++ b/target/i386/hvf/x86_decode.h @@ -309,7 +309,7 @@ addr_t get_reg_val(CPUX86State *env, int reg, int is_extended, int size); void calc_modrm_operand(CPUX86State *env, struct x86_decode *decode, struct x86_decode_op *op); addr_t decode_linear_addr(CPUX86State *env, struct x86_decode *decode, - addr_t addr, x86_reg_segment seg); + addr_t addr, enum X86Seg seg); void init_decoder(void); void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode, diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index 0b9562818f..269c46f53a 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -21,12 +21,12 @@ #include "vmx.h" #include "x86_descr.h" -#define VMX_SEGMENT_FIELD(seg) \ - [REG_SEG_##seg] = { \ - .selector = VMCS_GUEST_##seg##_SELECTOR, \ - .base = VMCS_GUEST_##seg##_BASE, \ - .limit = VMCS_GUEST_##seg##_LIMIT, \ - .ar_bytes = VMCS_GUEST_##seg##_ACCESS_RIGHTS, \ +#define VMX_SEGMENT_FIELD(seg) \ + [R_##seg] = { \ + .selector = VMCS_GUEST_##seg##_SELECTOR, \ + .base = VMCS_GUEST_##seg##_BASE, \ + .limit = VMCS_GUEST_##seg##_LIMIT, \ + .ar_bytes = VMCS_GUEST_##seg##_ACCESS_RIGHTS, \ } static const struct vmx_segment_field { @@ -45,34 +45,34 @@ static const struct vmx_segment_field { VMX_SEGMENT_FIELD(TR), }; -uint32_t vmx_read_segment_limit(CPUState *cpu, x86_reg_segment seg) +uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg) { return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); } -uint32_t vmx_read_segment_ar(CPUState *cpu, x86_reg_segment seg) +uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg) { return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); } -uint64_t vmx_read_segment_base(CPUState *cpu, x86_reg_segment seg) +uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg) { return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); } -x68_segment_selector vmx_read_segment_selector(CPUState *cpu, x86_reg_segment seg) +x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) { x68_segment_selector sel; sel.sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); return sel; } -void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg) +void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg) { wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel); } -void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg) +void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg) { desc->sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); desc->base = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); @@ -80,7 +80,7 @@ void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, desc->ar = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); } -void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg) +void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg) { const struct vmx_segment_field *sf = &vmx_segment_fields[seg]; diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h index 034d8e95c5..25a2b1731c 100644 --- a/target/i386/hvf/x86_descr.h +++ b/target/i386/hvf/x86_descr.h @@ -30,18 +30,18 @@ typedef struct vmx_segment { /* deal with vmstate descriptors */ void vmx_read_segment_descriptor(struct CPUState *cpu, - struct vmx_segment *desc, x86_reg_segment seg); + struct vmx_segment *desc, enum X86Seg seg); void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, - x86_reg_segment seg); + enum X86Seg seg); x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, - x86_reg_segment seg); + enum X86Seg seg); void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, - x86_reg_segment seg); + enum X86Seg seg); -uint64_t vmx_read_segment_base(struct CPUState *cpu, x86_reg_segment seg); -void vmx_write_segment_base(struct CPUState *cpu, x86_reg_segment seg, +uint64_t vmx_read_segment_base(struct CPUState *cpu, enum X86Seg seg); +void vmx_write_segment_base(struct CPUState *cpu, enum X86Seg seg, uint64_t base); void x86_segment_descriptor_to_vmx(struct CPUState *cpu, @@ -49,8 +49,8 @@ void x86_segment_descriptor_to_vmx(struct CPUState *cpu, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc); -uint32_t vmx_read_segment_limit(CPUState *cpu, x86_reg_segment seg); -uint32_t vmx_read_segment_ar(CPUState *cpu, x86_reg_segment seg); +uint32_t vmx_read_segment_limit(CPUState *cpu, enum X86Seg seg); +uint32_t vmx_read_segment_ar(CPUState *cpu, enum X86Seg seg); void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index f0f68f1c30..b64e490c2d 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -294,7 +294,7 @@ static void fetch_operands(struct CPUX86State *env, struct x86_decode *decode, case X86_VAR_OFFSET: decode->op[i].ptr = decode_linear_addr(env, decode, decode->op[i].ptr, - REG_SEG_DS); + R_DS); if (calc_val[i]) { decode->op[i].val = read_val_ext(env, decode->op[i].ptr, decode->operand_size); @@ -514,10 +514,10 @@ static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode void (*func)(struct CPUX86State *env, struct x86_decode *ins), int rep) { - addr_t rcx = read_reg(env, REG_RCX, decode->addressing_size); + addr_t rcx = read_reg(env, R_RCX, decode->addressing_size); while (rcx--) { func(env, decode); - write_reg(env, REG_RCX, rcx, decode->addressing_size); + write_reg(env, R_RCX, rcx, decode->addressing_size); if ((PREFIX_REP == rep) && !get_ZF(env)) { break; } @@ -530,13 +530,13 @@ static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode) { addr_t addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, - REG_SEG_ES); + R_ES); hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 0, decode->operand_size, 1); vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode->operand_size); - string_increment_reg(env, REG_RDI, decode); + string_increment_reg(env, R_RDI, decode); } static void exec_ins(struct CPUX86State *env, struct x86_decode *decode) @@ -552,13 +552,13 @@ static void exec_ins(struct CPUX86State *env, struct x86_decode *decode) static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode) { - addr_t addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS); + addr_t addr = decode_linear_addr(env, decode, RSI(env), R_DS); vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->operand_size); hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 1, decode->operand_size, 1); - string_increment_reg(env, REG_RSI, decode); + string_increment_reg(env, R_RSI, decode); } static void exec_outs(struct CPUX86State *env, struct x86_decode *decode) @@ -578,15 +578,15 @@ static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode) addr_t dst_addr; addr_t val; - src_addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS); + src_addr = decode_linear_addr(env, decode, RSI(env), R_DS); dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, - REG_SEG_ES); + R_ES); val = read_val_ext(env, src_addr, decode->operand_size); write_val_ext(env, dst_addr, val, decode->operand_size); - string_increment_reg(env, REG_RSI, decode); - string_increment_reg(env, REG_RDI, decode); + string_increment_reg(env, R_RSI, decode); + string_increment_reg(env, R_RDI, decode); } static void exec_movs(struct CPUX86State *env, struct x86_decode *decode) @@ -605,9 +605,9 @@ static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode) addr_t src_addr; addr_t dst_addr; - src_addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS); + src_addr = decode_linear_addr(env, decode, RSI(env), R_DS); dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, - REG_SEG_ES); + R_ES); decode->op[0].type = X86_VAR_IMMEDIATE; decode->op[0].val = read_val_ext(env, src_addr, decode->operand_size); @@ -616,8 +616,8 @@ static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode) EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); - string_increment_reg(env, REG_RSI, decode); - string_increment_reg(env, REG_RDI, decode); + string_increment_reg(env, R_RSI, decode); + string_increment_reg(env, R_RDI, decode); } static void exec_cmps(struct CPUX86State *env, struct x86_decode *decode) @@ -636,11 +636,11 @@ static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode) addr_t addr; addr_t val; - addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, REG_SEG_ES); - val = read_reg(env, REG_RAX, decode->operand_size); + addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, R_ES); + val = read_reg(env, R_RAX, decode->operand_size); vmx_write_mem(ENV_GET_CPU(env), addr, &val, decode->operand_size); - string_increment_reg(env, REG_RDI, decode); + string_increment_reg(env, R_RDI, decode); } @@ -659,18 +659,18 @@ static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode) { addr_t addr; - addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, REG_SEG_ES); + addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, R_ES); decode->op[1].type = X86_VAR_IMMEDIATE; vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->operand_size); EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); - string_increment_reg(env, REG_RDI, decode); + string_increment_reg(env, R_RDI, decode); } static void exec_scas(struct CPUX86State *env, struct x86_decode *decode) { decode->op[0].type = X86_VAR_REG; - decode->op[0].reg = REG_RAX; + decode->op[0].reg = R_RAX; if (decode->rep) { string_rep(env, decode, exec_scas_single, decode->rep); } else { @@ -685,11 +685,11 @@ static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode) addr_t addr; addr_t val = 0; - addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS); + addr = decode_linear_addr(env, decode, RSI(env), R_DS); vmx_read_mem(ENV_GET_CPU(env), &val, addr, decode->operand_size); - write_reg(env, REG_RAX, val, decode->operand_size); + write_reg(env, R_RAX, val, decode->operand_size); - string_increment_reg(env, REG_RSI, decode); + string_increment_reg(env, R_RSI, decode); } static void exec_lods(struct CPUX86State *env, struct x86_decode *decode) @@ -840,7 +840,7 @@ void simulate_wrmsr(struct CPUState *cpu) env->hvf_emul->efer.efer = data; /*printf("new efer %llx\n", EFER(cpu));*/ wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data); - if (data & EFER_NXE) { + if (data & MSR_EFER_NXE) { hv_vcpu_invalidate_tlb(cpu->hvf_fd); } break; @@ -1465,14 +1465,14 @@ void load_regs(struct CPUState *cpu) CPUX86State *env = &x86_cpu->env; int i = 0; - RRX(env, REG_RAX) = rreg(cpu->hvf_fd, HV_X86_RAX); - RRX(env, REG_RBX) = rreg(cpu->hvf_fd, HV_X86_RBX); - RRX(env, REG_RCX) = rreg(cpu->hvf_fd, HV_X86_RCX); - RRX(env, REG_RDX) = rreg(cpu->hvf_fd, HV_X86_RDX); - RRX(env, REG_RSI) = rreg(cpu->hvf_fd, HV_X86_RSI); - RRX(env, REG_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI); - RRX(env, REG_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP); - RRX(env, REG_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP); + RRX(env, R_RAX) = rreg(cpu->hvf_fd, HV_X86_RAX); + RRX(env, R_RBX) = rreg(cpu->hvf_fd, HV_X86_RBX); + RRX(env, R_RCX) = rreg(cpu->hvf_fd, HV_X86_RCX); + RRX(env, R_RDX) = rreg(cpu->hvf_fd, HV_X86_RDX); + RRX(env, R_RSI) = rreg(cpu->hvf_fd, HV_X86_RSI); + RRX(env, R_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI); + RRX(env, R_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP); + RRX(env, R_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP); for (i = 8; i < 16; i++) { RRX(env, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i); } diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 22fde7fc39..6dbb1c6ce1 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -55,12 +55,12 @@ static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) tss->esi = ESI(env); tss->edi = EDI(env); - tss->es = vmx_read_segment_selector(cpu, REG_SEG_ES).sel; - tss->cs = vmx_read_segment_selector(cpu, REG_SEG_CS).sel; - tss->ss = vmx_read_segment_selector(cpu, REG_SEG_SS).sel; - tss->ds = vmx_read_segment_selector(cpu, REG_SEG_DS).sel; - tss->fs = vmx_read_segment_selector(cpu, REG_SEG_FS).sel; - tss->gs = vmx_read_segment_selector(cpu, REG_SEG_GS).sel; + tss->es = vmx_read_segment_selector(cpu, R_ES).sel; + tss->cs = vmx_read_segment_selector(cpu, R_CS).sel; + tss->ss = vmx_read_segment_selector(cpu, R_SS).sel; + tss->ds = vmx_read_segment_selector(cpu, R_DS).sel; + tss->fs = vmx_read_segment_selector(cpu, R_FS).sel; + tss->gs = vmx_read_segment_selector(cpu, R_GS).sel; } static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) @@ -83,22 +83,22 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) RSI(env) = tss->esi; RDI(env) = tss->edi; - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR); - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES); - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS); - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS); - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS); - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS); - vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, R_LDTR); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, R_ES); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, R_CS); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, R_SS); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, R_DS); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, R_FS); + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, R_GS); #if 0 - load_segment(cpu, REG_SEG_LDTR, tss->ldt); - load_segment(cpu, REG_SEG_ES, tss->es); - load_segment(cpu, REG_SEG_CS, tss->cs); - load_segment(cpu, REG_SEG_SS, tss->ss); - load_segment(cpu, REG_SEG_DS, tss->ds); - load_segment(cpu, REG_SEG_FS, tss->fs); - load_segment(cpu, REG_SEG_GS, tss->gs); + load_segment(cpu, R_LDTR, tss->ldt); + load_segment(cpu, R_ES, tss->es); + load_segment(cpu, R_CS, tss->cs); + load_segment(cpu, R_SS, tss->ss); + load_segment(cpu, R_DS, tss->ds); + load_segment(cpu, R_FS, tss->fs); + load_segment(cpu, R_GS, tss->gs); #endif } @@ -140,8 +140,8 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea struct x86_segment_descriptor curr_tss_desc, next_tss_desc; int ret; - x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, REG_SEG_TR); - uint64_t old_tss_base = vmx_read_segment_base(cpu, REG_SEG_TR); + x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR); + uint64_t old_tss_base = vmx_read_segment_base(cpu, R_TR); uint32_t desc_limit; struct x86_call_gate task_gate_desc; struct vmx_segment vmx_seg; @@ -158,7 +158,7 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea ret = x86_read_call_gate(cpu, &task_gate_desc, gate); dpl = task_gate_desc.dpl; - x68_segment_selector cs = vmx_read_segment_selector(cpu, REG_SEG_CS); + x68_segment_selector cs = vmx_read_segment_selector(cpu, R_CS); if (tss_sel.rpl > dpl || cs.rpl > dpl) ;//DPRINTF("emulate_gp"); } @@ -192,7 +192,7 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); - vmx_write_segment_descriptor(cpu, &vmx_seg, REG_SEG_TR); + vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); store_regs(cpu); diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 83eb3be065..087deac6a9 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -107,28 +107,28 @@ void hvf_put_segments(CPUState *cpu_state) macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]); hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_CS); + vmx_write_segment_descriptor(cpu_state, &seg, R_CS); hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_DS); + vmx_write_segment_descriptor(cpu_state, &seg, R_DS); hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_ES); + vmx_write_segment_descriptor(cpu_state, &seg, R_ES); hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_SS); + vmx_write_segment_descriptor(cpu_state, &seg, R_SS); hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_FS); + vmx_write_segment_descriptor(cpu_state, &seg, R_FS); hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_GS); + vmx_write_segment_descriptor(cpu_state, &seg, R_GS); hvf_set_segment(cpu_state, &seg, &env->tr, true); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_TR); + vmx_write_segment_descriptor(cpu_state, &seg, R_TR); hvf_set_segment(cpu_state, &seg, &env->ldt, false); - vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR); + vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); hv_vcpu_flush(cpu_state->hvf_fd); } @@ -183,28 +183,28 @@ void hvf_get_segments(CPUState *cpu_state) env->interrupt_injected = -1; - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_CS); + vmx_read_segment_descriptor(cpu_state, &seg, R_CS); hvf_get_segment(&env->segs[R_CS], &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_DS); + vmx_read_segment_descriptor(cpu_state, &seg, R_DS); hvf_get_segment(&env->segs[R_DS], &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_ES); + vmx_read_segment_descriptor(cpu_state, &seg, R_ES); hvf_get_segment(&env->segs[R_ES], &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_FS); + vmx_read_segment_descriptor(cpu_state, &seg, R_FS); hvf_get_segment(&env->segs[R_FS], &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_GS); + vmx_read_segment_descriptor(cpu_state, &seg, R_GS); hvf_get_segment(&env->segs[R_GS], &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_SS); + vmx_read_segment_descriptor(cpu_state, &seg, R_SS); hvf_get_segment(&env->segs[R_SS], &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_TR); + vmx_read_segment_descriptor(cpu_state, &seg, R_TR); hvf_get_segment(&env->tr, &seg); - vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR); + vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); env->idt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT); From patchwork Tue Oct 3 13:45:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820887 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Nd7G3NPg"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y60hP5FV1z9t2Z for ; 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[78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:14 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:34 +0200 Message-Id: <20171003134540.21625-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH 04/10] i386: hvf: remove more dead emulator code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Paolo Bonzini --- target/i386/hvf/hvf.c | 2 -- target/i386/hvf/x86.h | 5 ----- target/i386/hvf/x86_decode.c | 22 +++++++++++----------- target/i386/hvf/x86_emu.c | 25 ++++++++----------------- target/i386/hvf/x86_flags.c | 10 ---------- target/i386/hvf/x86_flags.h | 1 - target/i386/hvf/x86_mmu.c | 6 ++---- target/i386/hvf/x86_task.c | 10 ---------- 8 files changed, 21 insertions(+), 60 deletions(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 863226cc9a..ae3ecad2a4 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -739,7 +739,6 @@ int hvf_vcpu_exec(CPUState *cpu) uint32_t port = exit_qual >> 16; /*uint32_t rep = (exit_qual & 0x20) != 0;*/ -#if 1 if (!string && in) { uint64_t val = 0; load_regs(cpu); @@ -762,7 +761,6 @@ int hvf_vcpu_exec(CPUState *cpu) macvm_set_rip(cpu, rip + ins_len); break; } -#endif struct x86_decode decode; load_regs(cpu); diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index 650bb718bf..94ac67b5cb 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -103,10 +103,6 @@ typedef struct x86_reg_flags { }; } __attribute__ ((__packed__)) x86_reg_flags; -typedef struct x86_efer { - uint64_t efer; -} __attribute__ ((__packed__)) x86_efer; - typedef enum x86_reg_cr0 { CR0_PE = (1L << 0), CR0_MP = (1L << 1), @@ -306,7 +302,6 @@ typedef struct HVFX86EmulatorState { struct x86_register regs[16]; struct x86_reg_flags rflags; struct lazy_flags lflags; - struct x86_efer efer; uint8_t mmio_buf[4096]; } HVFX86EmulatorState; diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 86e7c4ee7a..24c732d9f1 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -630,7 +630,7 @@ static void decode_aegroup(CPUX86State *env, struct x86_decode *decode) } break; default: - VM_PANIC_ON_EX(1, "0xae: reg %d\n", decode->modrm.reg); + VM_PANIC_EX("0xae: reg %d\n", decode->modrm.reg); break; } } @@ -654,14 +654,14 @@ static void decode_d9_4(CPUX86State *env, struct x86_decode *decode) decode->cmd = X86_DECODE_CMD_FABS; break; case 0xe4: - VM_PANIC_ON_EX(1, "FTST"); + VM_PANIC("FTST"); break; case 0xe5: /* FXAM */ decode->cmd = X86_DECODE_CMD_FXAM; break; default: - VM_PANIC_ON_EX(1, "FLDENV"); + VM_PANIC("FLDENV"); break; } } @@ -670,16 +670,16 @@ static void decode_db_4(CPUX86State *env, struct x86_decode *decode) { switch (decode->modrm.modrm) { case 0xe0: - VM_PANIC_ON_EX(1, "unhandled FNENI: %x %x\n", decode->opcode[0], - decode->modrm.modrm); + VM_PANIC_EX("unhandled FNENI: %x %x\n", decode->opcode[0], + decode->modrm.modrm); break; case 0xe1: - VM_PANIC_ON_EX(1, "unhandled FNDISI: %x %x\n", decode->opcode[0], - decode->modrm.modrm); + VM_PANIC_EX("unhandled FNDISI: %x %x\n", decode->opcode[0], + decode->modrm.modrm); break; case 0xe2: - VM_PANIC_ON_EX(1, "unhandled FCLEX: %x %x\n", decode->opcode[0], - decode->modrm.modrm); + VM_PANIC_EX("unhandled FCLEX: %x %x\n", decode->opcode[0], + decode->modrm.modrm); break; case 0xe3: decode->cmd = X86_DECODE_CMD_FNINIT; @@ -688,8 +688,8 @@ static void decode_db_4(CPUX86State *env, struct x86_decode *decode) decode->cmd = X86_DECODE_CMD_FNSETPM; break; default: - VM_PANIC_ON_EX(1, "unhandled fpu opcode: %x %x\n", decode->opcode[0], - decode->modrm.modrm); + VM_PANIC_EX("unhandled fpu opcode: %x %x\n", decode->opcode[0], + decode->modrm.modrm); break; } } diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index b64e490c2d..3a995fe687 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -837,7 +837,6 @@ void simulate_wrmsr(struct CPUState *cpu) abort(); break; case MSR_EFER: - env->hvf_emul->efer.efer = data; /*printf("new efer %llx\n", EFER(cpu));*/ wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { @@ -1511,23 +1510,15 @@ bool exec_instruction(struct CPUX86State *env, struct x86_decode *ins) printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu), decode_cmd_to_string(ins->cmd));*/ - if (0 && ins->is_fpu) { - VM_PANIC("emulate fpu\n"); - } else { - if (!_cmd_handler[ins->cmd].handler) { - printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env), - ins->cmd, ins->opcode[0], - ins->opcode_len > 1 ? ins->opcode[1] : 0); - RIP(env) += ins->len; - return true; - } - - VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler, - "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env), - ins->cmd, ins->opcode[0], - ins->opcode_len > 1 ? ins->opcode[1] : 0); - _cmd_handler[ins->cmd].handler(env, ins); + if (!_cmd_handler[ins->cmd].handler) { + printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env), + ins->cmd, ins->opcode[0], + ins->opcode_len > 1 ? ins->opcode[1] : 0); + RIP(env) += ins->len; + return true; } + + _cmd_handler[ins->cmd].handler(env, ins); return true; } diff --git a/target/i386/hvf/x86_flags.c b/target/i386/hvf/x86_flags.c index c833774485..e7bbce75e1 100644 --- a/target/i386/hvf/x86_flags.c +++ b/target/i386/hvf/x86_flags.c @@ -301,16 +301,6 @@ void set_SF(CPUX86State *env, bool val) env->hvf_emul->lflags.auxbits ^= (temp_sf ^ val) << LF_BIT_SD; } -void set_OSZAPC(CPUX86State *env, uint32_t flags32) -{ - set_OF(env, env->hvf_emul->rflags.of); - set_SF(env, env->hvf_emul->rflags.sf); - set_ZF(env, env->hvf_emul->rflags.zf); - set_AF(env, env->hvf_emul->rflags.af); - set_PF(env, env->hvf_emul->rflags.pf); - set_CF(env, env->hvf_emul->rflags.cf); -} - void lflags_to_rflags(CPUX86State *env) { env->hvf_emul->rflags.cf = get_CF(env); diff --git a/target/i386/hvf/x86_flags.h b/target/i386/hvf/x86_flags.h index 57a524240c..3e487535ea 100644 --- a/target/i386/hvf/x86_flags.h +++ b/target/i386/hvf/x86_flags.h @@ -190,7 +190,6 @@ bool get_SF(CPUX86State *env); void set_SF(CPUX86State *env, bool val); bool get_OF(CPUX86State *env); void set_OF(CPUX86State *env, bool val); -void set_OSZAPC(CPUX86State *env, uint32_t flags32); void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 26e9e95b0b..1084670c1d 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -238,8 +238,7 @@ void vmx_write_mem(struct CPUState *cpu, addr_t gva, void *data, int bytes) int copy = MIN(bytes, 0x1000 - (gva & 0xfff)); if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { - VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __func__, - gva); + VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); } else { address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 1); @@ -260,8 +259,7 @@ void vmx_read_mem(struct CPUState *cpu, void *data, addr_t gva, int bytes) int copy = MIN(bytes, 0x1000 - (gva & 0xfff)); if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { - VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __func__, - gva); + VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); } address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 0); diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 6dbb1c6ce1..b6ce2a151b 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -90,16 +90,6 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, R_DS); vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, R_FS); vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, R_GS); - -#if 0 - load_segment(cpu, R_LDTR, tss->ldt); - load_segment(cpu, R_ES, tss->es); - load_segment(cpu, R_CS, tss->cs); - load_segment(cpu, R_SS, tss->ss); - load_segment(cpu, R_DS, tss->ds); - load_segment(cpu, R_FS, tss->fs); - load_segment(cpu, R_GS, tss->gs); -#endif } static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel, From patchwork Tue Oct 3 13:45:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:15 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:35 +0200 Message-Id: <20171003134540.21625-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH 05/10] i386: hvf: remove ZERO_INIT macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86.c | 3 ++- target/i386/hvf/x86_decode.c | 3 +-- target/i386/hvf/x86_gen.h | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index ca0ec2968a..8002a41d30 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -53,7 +53,8 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, addr_t base; uint32_t limit; - ZERO_INIT(*desc); + memset(desc, 0, sizeof(*desc)); + /* valid gdt descriptors start from index 1 */ if (!sel.index && GDT_SEL == sel.ti) { return false; diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 24c732d9f1..08b6036f2e 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -2090,8 +2090,7 @@ static void decode_opcodes(CPUX86State *env, struct x86_decode *decode) uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode) { - ZERO_INIT(*decode); - + memset(decode, 0, sizeof(*decode)); decode_prefix(env, decode); set_addressing_size(env, decode); set_operand_size(env, decode); diff --git a/target/i386/hvf/x86_gen.h b/target/i386/hvf/x86_gen.h index 2045b0e69d..d33dea842e 100644 --- a/target/i386/hvf/x86_gen.h +++ b/target/i386/hvf/x86_gen.h @@ -48,6 +48,4 @@ typedef uint64_t addr_t; } \ } -#define ZERO_INIT(obj) memset((void *) &obj, 0, sizeof(obj)) - #endif From patchwork Tue Oct 3 13:45:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:16 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:36 +0200 Message-Id: <20171003134540.21625-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH 06/10] i386: hvf: abort on decoding error X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rather than unsupported situations, some VM_PANIC calls actually are caused by internal errors. Convert them to just abort. Signed-off-by: Paolo Bonzini --- target/i386/hvf/hvf.c | 2 +- target/i386/hvf/x86_emu.c | 10 ++++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ae3ecad2a4..f2dc37d826 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -767,7 +767,7 @@ int hvf_vcpu_exec(CPUState *cpu) env->hvf_emul->fetch_rip = rip; decode_instruction(env, &decode); - VM_PANIC_ON(ins_len != decode.len); + assert(ins_len == decode.len); exec_instruction(env, &decode); store_regs(cpu); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 3a995fe687..63c2b5a54d 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -146,7 +146,7 @@ addr_t read_reg(CPUX86State *env, int reg, int size) case 8: return env->hvf_emul->regs[reg].rrx; default: - VM_PANIC_ON("read_reg size"); + abort(); } return 0; } @@ -167,7 +167,7 @@ void write_reg(CPUX86State *env, int reg, addr_t val, int size) env->hvf_emul->regs[reg].rrx = val; break; default: - VM_PANIC_ON("write_reg size"); + abort(); } } @@ -189,8 +189,7 @@ addr_t read_val_from_reg(addr_t reg_ptr, int size) val = *(uint64_t *)reg_ptr; break; default: - VM_PANIC_ON_EX(1, "read_val: Unknown size %d\n", size); - break; + abort(); } return val; } @@ -211,8 +210,7 @@ void write_val_to_reg(addr_t reg_ptr, addr_t val, int size) *(uint64_t *)reg_ptr = val; break; default: - VM_PANIC("write_val: Unknown size\n"); - break; + abort(); } } From patchwork Tue Oct 3 13:45:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EXZ6Jlij"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y60pH5sqNz9t2Q for ; Wed, 4 Oct 2017 00:52:23 +1100 (AEDT) Received: from localhost ([::1]:58677 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzNcT-0006iX-TJ for incoming@patchwork.ozlabs.org; Tue, 03 Oct 2017 09:52:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzNWm-00025v-W1 for qemu-devel@nongnu.org; Tue, 03 Oct 2017 09:46:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzNWh-0004B8-Hs for qemu-devel@nongnu.org; Tue, 03 Oct 2017 09:46:29 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:55663) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzNWh-0004AW-BE for qemu-devel@nongnu.org; Tue, 03 Oct 2017 09:46:23 -0400 Received: by mail-wm0-x241.google.com with SMTP id u138so17040121wmu.4 for ; Tue, 03 Oct 2017 06:46:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=1YzUUbxg4athwd6C3TGcWXt8ldqUrKcRoOBYBnQ0Hfw=; b=EXZ6JlijDqeJQD/XoOc+PwLiu4FzBXTgs5O72gB7aHgSAd4wCFplWbZKJjRCWAJX94 jyLPf+UD06aBzY1iaIY4SF1w0H+pP7r6IvAGM0Bq1/98bFxI3Z0PVBvEkyoKUcr0oXJy bzr/Aw0wjjaJNIcuXfTiz7Ziwc5eAyktvAUJrkCPaUEsLcQ1zQntrejiVaxJqgnCTMcX JblSe3UzuAebOxOc5whpTFmIwUDrs5wQL0e0qeKUd6pxoAjCKMwSNHF1jC+8KSwWQbHO gNMd2T7+6jziJaWMRhRStFVz2fNPcWyzSkJfMwbFsnxRuqs8X4683gjyLgCWyeBGwpJo GS/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=1YzUUbxg4athwd6C3TGcWXt8ldqUrKcRoOBYBnQ0Hfw=; b=QBGCXgA53GAoDnyARg/YHygruC75qBjXC8DYl8LifEyk1rhP9bnjNkmsjICFzrbf7h wpZzy2+fk3ytMH3AfY3phsqCK0thCv81JrCfPlA5sSuHagAj6vKTlxXsNwa+B+fUb7Mf ad6roxHrkjuoTVlXEnG8LLHxgK68jTMZCKhzDc/GUzfcR8F4Ahm9pccL4zHTH77elky3 KQXZnoWHWvC1+satEoW1ZAe3zJX4zSRpCKXfvNyBPbDzSt62WR1RpWKpf/NkFvkCMneJ GgiG0yEKKfQt/MDA+8O/9qXjvcldKLbICB4jwCn5JGFNewkYJ/msuyT6v0kqXJIyrBmT p+/Q== X-Gm-Message-State: AMCzsaXD0cHyk8qTy/kGGQJE9QCIl7xv+P3119ttLyC9HF9hxMftf7CH rnHdVjZ6XBTmCAA7kaMxkd1V4d7G X-Google-Smtp-Source: AOwi7QBBMDVYOf+ovx//lD3AYOFDJcQxb3bje6Bf8pkHWfcaYExdWSWHbsAViO2Dlxxb68rUe4/XqQ== X-Received: by 10.28.47.69 with SMTP id v66mr11148295wmv.98.1507038382198; Tue, 03 Oct 2017 06:46:22 -0700 (PDT) Received: from donizetti.lan (dynamic-adsl-78-12-246-117.clienti.tiscali.it. [78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:21 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:39 +0200 Message-Id: <20171003134540.21625-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH 09/10] i386: hvf: simplify and fix in/out handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Reading a 32-bit port should clear the upper 32-bits of the register. Signed-off-by: Paolo Bonzini --- target/i386/hvf/hvf.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 5194b94591..35e39afefd 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -748,16 +748,16 @@ int hvf_vcpu_exec(CPUState *cpu) } else if (size == 2) { AX(env) = val; } else if (size == 4) { - RAX(env) = (uint32_t)val; + RRX(env) = (uint32_t)val; } else { - VM_PANIC("size"); + RRX(env) = (uint64_t)val; } RIP(env) += ins_len; store_regs(cpu); break; } else if (!string && !in) { - RAX(env) = rreg(cpu->hvf_fd, HV_X86_RAX); - hvf_handle_io(env, port, &RAX(env), 1, size, 1); + RRX(env) = rreg(cpu->hvf_fd, HV_X86_RAX); + hvf_handle_io(env, port, &RRX(env), 1, size, 1); macvm_set_rip(cpu, rip + ins_len); break; } From patchwork Tue Oct 3 13:45:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 820897 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Pay++SW6"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y60rm3DB8z9t2Q for ; Wed, 4 Oct 2017 00:54:32 +1100 (AEDT) Received: from localhost ([::1]:58683 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzNeY-0008OW-1I for incoming@patchwork.ozlabs.org; Tue, 03 Oct 2017 09:54:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzNWk-00024g-GY for qemu-devel@nongnu.org; Tue, 03 Oct 2017 09:46:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzNWj-0004Bl-1l for qemu-devel@nongnu.org; Tue, 03 Oct 2017 09:46:26 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:36494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzNWi-0004BQ-Oz for qemu-devel@nongnu.org; Tue, 03 Oct 2017 09:46:24 -0400 Received: by mail-wr0-x242.google.com with SMTP id k10so5927678wrk.3 for ; Tue, 03 Oct 2017 06:46:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8VE7NkoKCPECQ2OQKc+Jqi035J6zUJQNY4bNLHhetXY=; b=Pay++SW6iXeLdyDoJkXyRC3dux7GaC6G0BFSSc+vmzIvZMazsi6LSbH/kPg46Cui1+ bcO6PwR65QCqojaqYFOMrG/k9NDYZs7oFqLILkMR7T1dkGz4GgxHuo4DfCJggzePtF9I o0WzrdlwzZ+sEsDdqGakBWiKNVbfVj1khjBDPEyfs7z9zySgTmoe5JbulMdpQDxw/XXW boRnPn/KoIEEOq9PZzCiMtpI8Lpvh0Q08wpre5EcOXpkVIs1iBuY8MOIsyUTNqap0XCh ys0SLLYi0LTsQS+aBJwazHeqLdHWMcwixXTszDg3Tzsan6SzbH5Im6MccfNNcXVPwq3X IU/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=8VE7NkoKCPECQ2OQKc+Jqi035J6zUJQNY4bNLHhetXY=; b=KjFrzgR9gLU85G433vOZ4XGwi2cFbidaKJYD1HvX2oZTSbjMf1cIIJj/6QNRYODztn l09sPS3HejwMSfsL0eCjNkpMWcmY3VSNSa5iY4ExagEybVr3tTasv/Nsk9KMEVBcikLD pSNm5AKE8x1JOPyo1V4w5Q5SAF3c4gGk7xolyX+zdNaJqCxNYurIs5pD4ABvPocJQ8Os ob22/5TSDllO3aNEVdHgLjJQRoBZpytqr+ubh62SMz96J33/rCiEc/H7R0zVgqIbODtr R/HkhDV5j0RGZbe+cACZlZby2SzSAQXqQkROEl8DVenZPKJGf4W1R7RJu3B09CH7+wHN gH4A== X-Gm-Message-State: AHPjjUjq+AnAXx5OnjCGKaU/NZ257eT5R7J9Wlq99pxMuoaJY/eMtNZe OPp1j5X2I8Hu18EGX9eB0o03Gqcx X-Google-Smtp-Source: AOwi7QD44L7mCMCHPa3kXWcC44AedAemx7ILORIDd6nYDYkMS5aMN0TZzspk3bO1wqXWOKlSHEgruw== X-Received: by 10.223.156.137 with SMTP id d9mr18843281wre.276.1507038383472; Tue, 03 Oct 2017 06:46:23 -0700 (PDT) Received: from donizetti.lan (dynamic-adsl-78-12-246-117.clienti.tiscali.it. [78.12.246.117]) by smtp.gmail.com with ESMTPSA id u52sm21724267wrb.23.2017.10.03.06.46.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Oct 2017 06:46:22 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 3 Oct 2017 15:45:40 +0200 Message-Id: <20171003134540.21625-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171003134540.21625-1-pbonzini@redhat.com> References: <20171003134540.21625-1-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH 10/10] i386: hvf: cleanup x86_gen.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sergio.g.delreal@gmail.com, agraf@suse.de, alex@alex.org.uk Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This only includes VM_PANIC now. No need to include it from headers. Signed-off-by: Paolo Bonzini --- target/i386/hvf-utils/panic.h | 45 +++++++++++++++++++++++++++++++++++++++++++ target/i386/hvf/x86.h | 1 - target/i386/hvf/x86_decode.c | 3 +-- target/i386/hvf/x86_emu.c | 2 +- target/i386/hvf/x86_flags.c | 1 + target/i386/hvf/x86_flags.h | 1 - target/i386/hvf/x86_mmu.c | 1 + target/i386/hvf/x86_mmu.h | 2 -- target/i386/hvf/x86_task.c | 1 + 9 files changed, 50 insertions(+), 7 deletions(-) create mode 100644 target/i386/hvf-utils/panic.h diff --git a/target/i386/hvf-utils/panic.h b/target/i386/hvf-utils/panic.h new file mode 100644 index 0000000000..411ef43a5b --- /dev/null +++ b/target/i386/hvf-utils/panic.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016 Veertu Inc, + * Copyright (C) 2017 Google Inc, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this program; if not, see . + */ +#ifndef HVF_PANIC_H +#define HVF_PANIC_H + +#define VM_PANIC(x) {\ + printf("%s\n", x); \ + abort(); \ +} + +#define VM_PANIC_ON(x) {\ + if (x) { \ + printf("%s\n", #x); \ + abort(); \ + } \ +} + +#define VM_PANIC_EX(...) {\ + printf(__VA_ARGS__); \ + abort(); \ +} + +#define VM_PANIC_ON_EX(x, ...) {\ + if (x) { \ + printf(__VA_ARGS__); \ + abort(); \ + } \ +} + +#endif diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index a7fc65a487..595d5aca04 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -20,7 +20,6 @@ #define HVF_X86_H 1 #include "qemu-common.h" -#include "x86_gen.h" typedef struct x86_register { union { diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index f6096ca307..ff31f4f577 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -17,11 +17,10 @@ */ #include "qemu/osdep.h" - +#include "panic.h" #include "x86_decode.h" #include "string.h" #include "vmx.h" -#include "x86_gen.h" #include "x86_mmu.h" #include "x86_descr.h" diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 8f45f01eed..44b0b83fea 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -36,7 +36,7 @@ ///////////////////////////////////////////////////////////////////////// #include "qemu/osdep.h" - +#include "panic.h" #include "qemu-common.h" #include "x86_decode.h" #include "x86.h" diff --git a/target/i386/hvf/x86_flags.c b/target/i386/hvf/x86_flags.c index b1f240ca0f..f79ff096f6 100644 --- a/target/i386/hvf/x86_flags.c +++ b/target/i386/hvf/x86_flags.c @@ -22,6 +22,7 @@ */ #include "qemu/osdep.h" +#include "panic.h" #include "qemu-common.h" #include "cpu.h" diff --git a/target/i386/hvf/x86_flags.h b/target/i386/hvf/x86_flags.h index 69d8672d24..c46a5fd8a8 100644 --- a/target/i386/hvf/x86_flags.h +++ b/target/i386/hvf/x86_flags.h @@ -23,7 +23,6 @@ #ifndef __X86_FLAGS_H__ #define __X86_FLAGS_H__ -#include "x86_gen.h" #include "cpu.h" void lflags_to_rflags(CPUX86State *env); void rflags_to_lflags(CPUX86State *env); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index af11635fba..682e29774e 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -16,6 +16,7 @@ * License along with this program; if not, see . */ #include "qemu/osdep.h" +#include "panic.h" #include "qemu-common.h" #include "x86.h" diff --git a/target/i386/hvf/x86_mmu.h b/target/i386/hvf/x86_mmu.h index ae02cb6916..0bd1acc94f 100644 --- a/target/i386/hvf/x86_mmu.h +++ b/target/i386/hvf/x86_mmu.h @@ -18,8 +18,6 @@ #ifndef __X86_MMU_H__ #define __X86_MMU_H__ -#include "x86_gen.h" - #define PT_PRESENT (1 << 0) #define PT_WRITE (1 << 1) #define PT_USER (1 << 2) diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index b6ce2a151b..f77edda580 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -7,6 +7,7 @@ // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. #include "qemu/osdep.h" +#include "panic.h" #include "qemu-common.h" #include "qemu/error-report.h"