From patchwork Mon Aug 20 17:57:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 959616 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41vBxV2jpFz9s3C for ; Mon, 20 Aug 2018 21:52:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0D63EC21E2F; Mon, 20 Aug 2018 11:48:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=DATE_IN_FUTURE_06_12 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2B124C21E1B; Mon, 20 Aug 2018 11:47:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 91B4CC21C51; Mon, 20 Aug 2018 09:58:15 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id C640AC21C2F for ; Mon, 20 Aug 2018 09:58:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2018 02:58:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,264,1531810800"; d="scan'208";a="67570708" Received: from angcheeh-mobl.gar.corp.intel.com (HELO localhost.localdomain) ([10.226.242.59]) by orsmga006.jf.intel.com with ESMTP; 20 Aug 2018 02:58:12 -0700 From: chee.hong.ang@intel.com To: u-boot@lists.denx.de Date: Mon, 20 Aug 2018 10:57:34 -0700 Message-Id: <1534787856-18530-2-git-send-email-chee.hong.ang@intel.com> In-Reply-To: <1534787856-18530-1-git-send-email-chee.hong.ang@intel.com> References: <1534787856-18530-1-git-send-email-chee.hong.ang@intel.com> X-Mailman-Approved-At: Mon, 20 Aug 2018 11:46:54 +0000 Cc: Tom Rini , Hongbo Zhang , Chin Liang See , Chee Hong Ang Subject: [U-Boot] [PATCH v1 1/3] ARMv8: Enable all asynchronous abort exceptions taken to EL3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Chee Hong Ang Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang --- arch/arm/include/asm/macro.h | 4 ++++ arch/arm/include/asm/system.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index d5a7a8b..bb33b4b 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -193,6 +193,10 @@ lr .req x30 SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ SCR_EL3_NS_EN) #endif + +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + orr \tmp, \tmp, #SCR_EL3_EA_EN +#endif msr scr_el3, \tmp /* Return to the EL2_SP2 mode from EL3 */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index c1f87f9..aed2e3c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -29,6 +29,7 @@ #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */ #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */ #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */ +#define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */ #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */ /* From patchwork Mon Aug 20 17:57:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 959613 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41vBwB00nzz9s3C for ; Mon, 20 Aug 2018 21:51:05 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id ACF8BC21DF8; Mon, 20 Aug 2018 11:48:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=DATE_IN_FUTURE_06_12 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5F55CC21E15; Mon, 20 Aug 2018 11:47:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1EB10C21DD9; Mon, 20 Aug 2018 09:58:18 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id 642B0C21C2F for ; Mon, 20 Aug 2018 09:58:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2018 02:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,264,1531810800"; d="scan'208";a="67570717" Received: from angcheeh-mobl.gar.corp.intel.com (HELO localhost.localdomain) ([10.226.242.59]) by orsmga006.jf.intel.com with ESMTP; 20 Aug 2018 02:58:14 -0700 From: chee.hong.ang@intel.com To: u-boot@lists.denx.de Date: Mon, 20 Aug 2018 10:57:35 -0700 Message-Id: <1534787856-18530-3-git-send-email-chee.hong.ang@intel.com> In-Reply-To: <1534787856-18530-1-git-send-email-chee.hong.ang@intel.com> References: <1534787856-18530-1-git-send-email-chee.hong.ang@intel.com> X-Mailman-Approved-At: Mon, 20 Aug 2018 11:46:54 +0000 Cc: Tom Rini , Hongbo Zhang , Chin Liang See , Chee Hong Ang Subject: [U-Boot] [PATCH v1 2/3] ARMv8: Add EL3 exception handling for ARMv8's Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Chee Hong Ang Kconfig option to allow all External Abort and SError exception taken to EL3. Signed-off-by: Chee Hong Ang --- arch/arm/cpu/armv8/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index c8bebab..ff42791 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -144,6 +144,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. +config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" + default n + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. + if SYS_HAS_ARMV8_SECURE_BASE config ARMV8_SECURE_BASE From patchwork Mon Aug 20 17:57:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 959614 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41vBwP2Z4fz9s3C for ; Mon, 20 Aug 2018 21:51:17 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1CCA9C21DF8; Mon, 20 Aug 2018 11:48:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=DATE_IN_FUTURE_06_12 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 80623C21E3A; Mon, 20 Aug 2018 11:47:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D1128C21C8B; Mon, 20 Aug 2018 09:58:22 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id 0ACE5C21C2F for ; Mon, 20 Aug 2018 09:58:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2018 02:58:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,264,1531810800"; d="scan'208";a="67570727" Received: from angcheeh-mobl.gar.corp.intel.com (HELO localhost.localdomain) ([10.226.242.59]) by orsmga006.jf.intel.com with ESMTP; 20 Aug 2018 02:58:17 -0700 From: chee.hong.ang@intel.com To: u-boot@lists.denx.de Date: Mon, 20 Aug 2018 10:57:36 -0700 Message-Id: <1534787856-18530-4-git-send-email-chee.hong.ang@intel.com> In-Reply-To: <1534787856-18530-1-git-send-email-chee.hong.ang@intel.com> References: <1534787856-18530-1-git-send-email-chee.hong.ang@intel.com> X-Mailman-Approved-At: Mon, 20 Aug 2018 11:46:54 +0000 Cc: Tom Rini , Hongbo Zhang , Chin Liang See , Chee Hong Ang Subject: [U-Boot] [PATCH v1 3/3] ARMv8: SError exception handling in PSCI exception vectors X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Chee Hong Ang Allow platform vendors to handle SError interrupt exceptions from ARMv8 PSCI exception vectors by overriding this weak function 'plat_error_handler'. Signed-off-by: Chee Hong Ang --- arch/arm/cpu/armv8/psci.S | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 097f91b..358df8f 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -236,6 +236,28 @@ handle_sync: b unhandled_exception +#ifdef CONFIG_ARMV8_EA_EL3_FIRST +/* + * Override this function if custom error handling is + * needed for asynchronous aborts + */ +ENTRY(plat_error_handler) + ret +ENDPROC(plat_error_handler) +.weak plat_error_handler + +handle_error: + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov x9, #1 + msr spsel, x9 + mov sp, x0 + + bl plat_error_handler /* Platform specific error handling */ +deadloop: + b deadloop /* Never return */ +#endif + .align 11 .globl el3_exception_vectors el3_exception_vectors: @@ -261,7 +283,11 @@ el3_exception_vectors: .align 7 b unhandled_exception /* FIQ, Lower EL using AArch64 */ .align 7 +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + b handle_error /* SError, Lower EL using AArch64 */ +#else b unhandled_exception /* SError, Lower EL using AArch64 */ +#endif .align 7 b unhandled_exception /* Sync, Lower EL using AArch32 */ .align 7