From patchwork Mon Aug 20 06:39:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 959523 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="vSwB9YON"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41v42G1F95z9s89 for ; Mon, 20 Aug 2018 16:40:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726042AbeHTJzP (ORCPT ); Mon, 20 Aug 2018 05:55:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:40810 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725948AbeHTJzP (ORCPT ); Mon, 20 Aug 2018 05:55:15 -0400 Received: from localhost.localdomain (unknown [171.76.73.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9AEF321536; Mon, 20 Aug 2018 06:40:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1534747251; bh=s4jU+DvjvQ1BcqKQzKl9VxHlU1ZuFAjmsfzUUbvjQfE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vSwB9YONAV+JFHPsUYiqYzjVYEBvgmqObeh0g6a8QCBwndE3PP7pw1gYAdvzvQrde BK5SNHBhqTOgNzh+azXnhZNqRaMe9XO8KOAPh/AzvZrk+8nUH1wQUj9j8EXev3X1l0 oJnKlt8qk4X79ivNhezW81xTD3pyH1RDqEsKlCRI= From: Vinod Koul To: Wolfram Sang , linux-i2c@vger.kernel.org Cc: Bjorn Andersson , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, Todor Tomov , Vinod Koul Subject: [PATCH v4 1/2] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Date: Mon, 20 Aug 2018 12:09:52 +0530 Message-Id: <20180820063953.6866-2-vkoul@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180820063953.6866-1-vkoul@kernel.org> References: <20180820063953.6866-1-vkoul@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Todor Tomov Add DT binding document for Qualcomm Camera Control Interface (CCI) I2C controller. Signed-off-by: Todor Tomov Signed-off-by: Vinod Koul Reviewed-by: Rob Herring --- .../devicetree/bindings/i2c/i2c-qcom-cci.txt | 83 ++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt new file mode 100644 index 000000000000..b7f4240ce5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt @@ -0,0 +1,83 @@ +Qualcomm Camera Control Interface (CCI) I2C controller + +PROPERTIES: + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,msm-8916-cci" + "qcom,msm-8996-cci" + +- reg + Usage: required + Value type: + Definition: base address CCI I2C controller and length of memory + mapped region. + +- interrupts: + Usage: required + Value type: + Definition: specifies the CCI I2C interrupt. The format of the + specifier is defined by the binding document describing + the node's interrupt parent. + +- clocks: + Usage: required + Value type: + Definition: a list of phandle, should contain an entry for each + entries in clock-names. + +- clock-names + Usage: required + Value type: + Definition: a list of clock names, must include these entries: + "mmss_mmagic_ahb" - on "qcom,msm-8996-cci" only; + "camss_top_ahb"; + "cci_ahb"; + "cci"; + "camss_ahb"; + +- power-domains + Usage: required for "qcom,msm-8996-cci" + Value type: + Definition: + +SUBNODES: + +The CCI provides I2C masters for one or two i2c busses, described as +subdevices named "i2c-bus0" and "i2c-bus1". + +PROPERTIES: + +- clock-frequency: + Usage: optional + Value type: + Definition: Desired I2C bus clock frequency in Hz, defaults to 100 + kHz if omitted. + +Example: + + cci@a0c000 { + compatible = "qcom,msm-8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = ; + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, + <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "mmss_mmagic_ahb", + "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + i2c-bus0 { + clock-frequency = <400000>; + }; + i2c-bus1 { + clock-frequency = <400000>; + }; + };