From patchwork Wed Aug 15 12:57:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 957855 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-483699-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="NK1V4SbQ"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="DjgRjokq"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41r8d51Dqdz9sBq for ; Wed, 15 Aug 2018 22:57:28 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=XZm2PVqRL3O0CFGDxARUJtOCJI8pSgK0bOGcASLsF5Lo7IdLkW j6yp3MylxZ+pqQi4sPj0HHkmhWxL3QLARTAefM9Kf10CL1jKCoOsNQU3e2Q6tJ11 arKFlHlGYuKFx5LfwvaNKOLOKdxC24nuBQdYxxfyCfg3VkChazbQE5VPU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=Z6qlUVMC129CSYksHnrF4feAQSs=; b=NK1V4SbQSg2Y7oXT+eMr 29jMbagphn9bvVvAqVDbwk2HyTfd9P0Oh2hGE/Qe0XdTCwTHukTJYI0N4E5rpKc0 TI29OXs0SYALHIvy0YvS1MmefzMxQ1qpzkFEUyFMvgubesFaCHSZxG9ab93tG/3S 76kiIQRKZ9lTlG76SrKoMgk= Received: (qmail 54663 invoked by alias); 15 Aug 2018 12:57:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 54652 invoked by uid 89); 15 Aug 2018 12:57:21 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR04-VI1-obe.outbound.protection.outlook.com Received: from mail-eopbgr80074.outbound.protection.outlook.com (HELO EUR04-VI1-obe.outbound.protection.outlook.com) (40.107.8.74) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 Aug 2018 12:57:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7YUY6quLUSPjVxL4EmUZpEvQdzlpWC27tqfb2DbdGDg=; b=DjgRjokqp13mXASVI6zo9yH6C2CfRgDAO1wIZ54iFVlYKhBYztIzSz+dPQSx1OHLS4mNe6poYI3w05e9zkJWHI/ZYxVMZXGYEDWFODPe5HZLvIJoLnW6EHgN5d3dG/Ra5chVnsgnyLO7W0BRiYgmmOlcHtiXDr6CAWQFhDB9Od0= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Tamar.Christina@arm.com; Received: from arm.com (217.140.106.51) by AM4PR08MB0737.eurprd08.prod.outlook.com (2a01:111:e400:59ed::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1038.21; Wed, 15 Aug 2018 12:57:13 +0000 Date: Wed, 15 Aug 2018 13:57:11 +0100 From: Tamar Christina To: gcc-patches@gcc.gnu.org Cc: nd@arm.com, law@redhat.com, rguenther@suse.de, ian@airs.com Subject: [PATCH][GCC][mid-end] Fix DSE big-endian subreg crash Message-ID: <20180815125709.GA31341@arm.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-IsSubscribed: yes Hi All, This patch fixes an ICE that would happen when extract_low_bits is called with modes for which you can't extract a valid subreg. e.g. taking a 32 bytes subreg from a 48 byte mode. The ICE happens because convert_modes which eventually calls simplify_gen_subreg does not expect the convertion to fail. The assert in gen_lowpart_general would then be hit. The patch changes it to validate the subreg before trying to convert the modes. If the subreg is not possible we return NULL_RTX and bail out early. I don't have a target independent test for this because it depends on the target having a 48byte mode and using it for loads. Cross compiled and regtested on aarch64_be-none-elf and no issues Boostrapped and regtested aarch64-none-linux-gnu and found no issues. Bootstrapped on x86_64-pc-linux-gnu arm-none-linux-gnueabihf and no issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2018-08-15 Tamar Christina * expmed.c (extract_low_bits): Reject invalid subregs early. gcc/testsuite/ChangeLog: 2018-08-15 Tamar Christina * gcc.target/aarch64/large_struct_copy.c: New test. diff --git a/gcc/expmed.c b/gcc/expmed.c index 101e7b88107702b06276cfcd94319d6b79751368..8a1222fa69e88fa7ee6e2c3210d6747d6536de98 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -2392,6 +2392,10 @@ extract_low_bits (machine_mode mode, machine_mode src_mode, rtx src) return NULL_RTX; src = gen_lowpart (src_int_mode, src); + if (!validate_subreg (int_mode, src_int_mode, src, + subreg_lowpart_offset (int_mode, src_int_mode))) + return NULL_RTX; + src = convert_modes (int_mode, src_int_mode, src, true); src = gen_lowpart (mode, src); return src; diff --git a/gcc/testsuite/gcc.target/aarch64/large_struct_copy.c b/gcc/testsuite/gcc.target/aarch64/large_struct_copy.c new file mode 100644 index 0000000000000000000000000000000000000000..2b5e7801bad0598138cbcee7b2f4ffffaaf438df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/large_struct_copy.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned __attribute__((mode(DI))) uint64_t; + +struct S0 { + uint64_t f1; + uint64_t f2; + uint64_t f3; + uint64_t f4; + uint64_t f5; +} a; +struct S2 { + uint64_t f0; + uint64_t f2; + struct S0 f3; +}; + +void fn1 () { + struct S2 b = {0, 1, 7, 4073709551611, 4, 8, 7}; + a = b.f3; +} +