From patchwork Wed Aug 15 18:20:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 957840 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41r58401ySz9s4c for ; Wed, 15 Aug 2018 20:20:35 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 919A8C21D4A; Wed, 15 Aug 2018 10:20:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1E60DC21D4A; Wed, 15 Aug 2018 10:20:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B0061C21C4A; Wed, 15 Aug 2018 10:20:27 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id DB603C21D4A for ; Wed, 15 Aug 2018 10:20:26 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2018 03:20:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,242,1531810800"; d="scan'208";a="62560992" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.105]) by fmsmga007.fm.intel.com with SMTP; 15 Aug 2018 03:20:22 -0700 Received: by ubuntu (sSMTP sendmail emulation); Thu, 16 Aug 2018 02:20:22 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Date: Thu, 16 Aug 2018 02:20:17 +0800 Message-Id: <1534357217-3315-1-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 Cc: Marek Vasut , Chin Liang See Subject: [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h index 813dff2..297f9e1 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h @@ -146,9 +146,9 @@ struct socfpga_system_manager { #define SYSMGR_FPGAINTF_SDMMC BIT(8) #define SYSMGR_FPGAINTF_SPIM0 BIT(16) #define SYSMGR_FPGAINTF_SPIM1 BIT(24) -#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0) -#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8) -#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16) +#define SYSMGR_FPGAINTF_EMAC0 BIT(0) +#define SYSMGR_FPGAINTF_EMAC1 BIT(8) +#define SYSMGR_FPGAINTF_EMAC2 BIT(16) #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 #define SYSMGR_SDMMC_DRVSEL_SHIFT 0