From patchwork Fri Aug 10 09:39:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 956162 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nyxOkoqP"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41n0QF2c6Xz9s7Q for ; Fri, 10 Aug 2018 19:37:09 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 016A9C21DA6; Fri, 10 Aug 2018 09:37:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E767EC21C27; Fri, 10 Aug 2018 09:37:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C36C2C21C27; Fri, 10 Aug 2018 09:37:00 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id D747FC21BE5 for ; Fri, 10 Aug 2018 09:36:59 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id r1-v6so4135790pgp.11 for ; Fri, 10 Aug 2018 02:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=eqUntzbJgNo8kzJ7z1fXa/4UJk3LUJwwu36BiD/yO+k=; b=nyxOkoqPx2g8GP4b1bmAxn/EZOlzcQxHyYf2Vlm0031Lprh0Bz1jczTeNVdSsEb1LG iH9FD8IEYk2sD73uR6Lk7efp7AAagF8p2PRmWSeGJrh/hxyFqz594nr4tBeKXa7L0jyK ucthD77eg4JFONqGszjJavGCXgf1Y79qkgGDdTNIdLL41pMW2TVHm31j4vQdVWflxBfa D6iqcTCCh87VIowH003o77oSmPaLea0larWM2F9eyY1zbUi0IowLgDeB+TGD9NoFO2Gh 5aJwtN5BYoMpHx+9XhbNd4Ytey+89Dq1l5Rj+2Pw/pYTY/0aeucygoFZUwkSrU30nc3b 0WTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=eqUntzbJgNo8kzJ7z1fXa/4UJk3LUJwwu36BiD/yO+k=; b=uU62SH+Etrhaw0vL/xKl8Ll7qE2quhDARiAO+a5gB/i8B9Rnpyz8XmBpYuWYwiNFGO XyZgTwQVEI/xcUvmivwoqur84J0I8lYUpi7VnosmzBUT8umYFa/U+/gruM6EEyKBC3NA BQLw8QRO10Gov2+vhKrhHcv0N9+uYJm3CtyBb4WaBLrjniEm6PsgCmyOhv2/Y7asOSQr Lf5RExqaGWrucynwGvJccmeIxNO476bSTZNnkpz6WsaZ/taa4wznpRI2wjuf3LewJ/1R GZ3yOHbRh+MJgp46k9X0eyTUh8DdnB81NaYqSGPp2cMXr28FvQw/nGmqxwz6UnV03wKC ms0w== X-Gm-Message-State: AOUpUlGExBvHmg2raprHrDcPI4qta1S5fUjBiYRNVr5dBCSTIQF5L8Ch 1seQ/hzfk/MzcoDVBVi6Rfo= X-Google-Smtp-Source: AA+uWPxNxwCGxRwZgjKqxc+gFILA+6Rc+qAZImQcvDTNYFv5uPHq3/c3NovCaGinapohGg3SaZa4Mw== X-Received: by 2002:a63:db4f:: with SMTP id x15-v6mr5695639pgi.214.1533893818269; Fri, 10 Aug 2018 02:36:58 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id u71-v6sm30416717pfk.174.2018.08.10.02.36.56 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 02:36:57 -0700 (PDT) From: Bin Meng To: Simon Glass , George McCollister , U-Boot Mailing List Date: Fri, 10 Aug 2018 02:39:33 -0700 Message-Id: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Subject: [U-Boot] =?utf-8?q?=5BPATCH_1/6=5D_x86=3A_coreboot=3A_Add_generic?= =?utf-8?q?_coreboot_payload_support?= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently building U-Boot as the coreboot payload requires user to change the build configuration for a specific board during menuconfig process. This uses the board's native device tree to configure the hardware. For example, the device tree provides PCI address range for the PCI host controller and U-Boot will re-program all PCI devices' BAR to be within this range. In order to make sure we don't mess up the hardware, we should guarantee the range matches what coreboot programs the chipset. But we really should make the coreboot payload support easier. Just like EFI payload, we can create a generic coreboot payload for all x86 boards as well. The payload is configured to include as many generic drivers as possible. All stuff that touches low level initialization are not allowed as such is the coreboot's responsibility. Platform specific drivers (like gpio, spi, etc) are not included. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- arch/x86/cpu/coreboot/Kconfig | 20 +++++------ arch/x86/cpu/coreboot/coreboot.c | 9 +++-- arch/x86/dts/Makefile | 1 + arch/x86/dts/coreboot.dts | 41 ++++++++++++++++++++++ board/coreboot/coreboot/Kconfig | 28 +++------------ board/coreboot/coreboot/Makefile | 2 +- board/coreboot/coreboot/coreboot.c | 17 +++++++++ .../coreboot/{coreboot_start.S => start.S} | 0 configs/coreboot_defconfig | 18 ++++------ doc/README.x86 | 15 -------- include/configs/coreboot.h | 32 +++++++++++++++++ 11 files changed, 116 insertions(+), 67 deletions(-) create mode 100644 arch/x86/dts/coreboot.dts create mode 100644 board/coreboot/coreboot/coreboot.c rename board/coreboot/coreboot/{coreboot_start.S => start.S} (100%) create mode 100644 include/configs/coreboot.h diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 392c258..93f61f2 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -3,26 +3,26 @@ if TARGET_COREBOOT config SYS_COREBOOT bool default y + imply SYS_NS16550 + imply SCSI + imply SCSI_AHCI imply AHCI_PCI - imply E1000 - imply ICH_SPI imply MMC imply MMC_PCI imply MMC_SDHCI imply MMC_SDHCI_SDMA - imply SCSI - imply SCSI_AHCI - imply SPI_FLASH - imply SYS_NS16550 imply USB imply USB_EHCI_HCD imply USB_XHCI_HCD + imply USB_STORAGE + imply USB_KEYBOARD imply VIDEO_COREBOOT + imply E1000 + imply ETH_DESIGNWARE + imply PCH_GBE + imply RTL8169 imply CMD_CBFS imply FS_CBFS - -config CBMEM_CONSOLE - bool - default y + imply CBMEM_CONSOLE endif diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 69025c1..a6fd3a8 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -75,12 +76,10 @@ int last_stage_init(void) if (gd->flags & GD_FLG_COLD_BOOT) timestamp_add_to_bootstage(); - board_final_cleanup(); + /* start usb so that usb keyboard can be used as input device */ + usb_init(); - return 0; -} + board_final_cleanup(); -int misc_init_r(void) -{ return 0; } diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 37e4fdc..c62540f 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ conga-qeval20-qa3-e3845.dtb \ + coreboot.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts new file mode 100644 index 0000000..a94f781 --- /dev/null +++ b/arch/x86/dts/coreboot.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * Generic coreboot payload device tree for x86 targets + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "reset.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "coreboot x86 payload"; + compatible = "coreboot,x86-payload"; + + aliases { + serial0 = &serial; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + }; + + coreboot-fb { + compatible = "coreboot-fb"; + }; +}; diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index cfa1d50..5bd6465 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -9,35 +9,15 @@ config SYS_VENDOR config SYS_SOC default "coreboot" +config SYS_CONFIG_NAME + default "coreboot" + config SYS_TEXT_BASE default 0x01110000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - imply SPI_FLASH_ATMEL - imply SPI_FLASH_EON - imply SPI_FLASH_GIGADEVICE - imply SPI_FLASH_MACRONIX - imply SPI_FLASH_SPANSION - imply SPI_FLASH_STMICRO - imply SPI_FLASH_SST - imply SPI_FLASH_WINBOND - -comment "coreboot-specific options" - -config SYS_CONFIG_NAME - string "Board configuration file" - default "qemu-x86" - help - This option selects the board configuration file in include/configs/ - directory to be used to build U-Boot for coreboot. - -config DEFAULT_DEVICE_TREE - string "Board Device Tree Source (dts) file" - default "qemu-x86_i440fx" - help - This option selects the board Device Tree Source (dts) file in - arch/x86/dts/ directory to be used to build U-Boot for coreboot. + select BOARD_EARLY_INIT_R config SYS_CAR_ADDR hex "Board specific Cache-As-RAM (CAR) address" diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index ea0f3ee..8db7cc6 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -10,4 +10,4 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -obj-y += coreboot_start.o +obj-y += start.o coreboot.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c new file mode 100644 index 0000000..ed5606d --- /dev/null +++ b/board/coreboot/coreboot/coreboot.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers + */ + pci_init(); + + return 0; +} diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/start.S similarity index 100% rename from board/coreboot/coreboot/coreboot_start.S rename to board/coreboot/coreboot/start.S diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 6af2f23..350acfb 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -3,28 +3,25 @@ CONFIG_SYS_TEXT_BASE=0x1110000 CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y +CONFIG_FIT_SIGNATURE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_BOOTSTAGE=y -CONFIG_CMD_TPM=y -CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -33,11 +30,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="coreboot" CONFIG_REGMAP=y CONFIG_SYSCON=y -CONFIG_SPI=y -CONFIG_TPM_TIS_LPC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y +# CONFIG_PCI_PNP is not set CONFIG_CONSOLE_SCROLL_LINES=5 -CONFIG_TPM=y diff --git a/doc/README.x86 b/doc/README.x86 index 9162ea1..6015ca4 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -47,21 +47,6 @@ on other architectures, like below: $ make coreboot_defconfig $ make all -Note this default configuration will build a U-Boot payload for the QEMU board. -To build a coreboot payload against another board, you can change the build -configuration during the 'make menuconfig' process. - -x86 architecture ---> - ... - (qemu-x86) Board configuration file - (qemu-x86_i440fx) Board Device Tree Source (dts) file - (0x01920000) Board specific Cache-As-RAM (CAR) address - (0x4000) Board specific Cache-As-RAM (CAR) size - -Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' -to point to a new board. You can also change the Cache-As-RAM (CAR) related -settings here if the default values do not fit your new board. - Build Instructions for U-Boot as main bootloader ------------------------------------------------ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h new file mode 100644 index 0000000..1cf5c03 --- /dev/null +++ b/include/configs/coreboot.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* ATA/IDE support */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#endif /* __CONFIG_H */ From patchwork Fri Aug 10 09:39:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 956164 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="serHV1/g"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41n0Rg0YrTz9s7Q for ; Fri, 10 Aug 2018 19:38:23 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B4F10C21CB6; Fri, 10 Aug 2018 09:37:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8E258C21D4A; Fri, 10 Aug 2018 09:37:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8D05AC21C27; Fri, 10 Aug 2018 09:37:01 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id EF6B0C21BE5 for ; Fri, 10 Aug 2018 09:37:00 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id r5-v6so4157451pgv.0 for ; Fri, 10 Aug 2018 02:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=zr/q4CxYuMNOY35tNu8W21UJY4jL5m2rXvYPAAuJPkI=; b=serHV1/gmr1G6rc4q+jdTV/QvDXgT8HbDYbDMUMjAzM7KOZJbRh+bpcvgf5fxNb0xE uS+W2JH2WBkPp5ltDIN1eAnHMNXTNmpuKrdY/7beVU/2kePSKn6c144hrSTRcvWQlyou FLalDzrI6FlLQiLrLeoBYsZlqLFN8pO+7lGIVL/lWbll9AljOxCvlOwAz/DU81Yk/Lec bfBxjoessVLZ334u9hzTgUAhiavuWaYUUCRP0AWNmmclXFlsMDlpA6zQe4LA4eOlZ+yj 8VqNdPLUqyB6xuzuJNK4SEyx5VrTQ0mYicZUayJldfkLFgeX8Ofk4NaCmcLljLE3Q729 KIeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=zr/q4CxYuMNOY35tNu8W21UJY4jL5m2rXvYPAAuJPkI=; b=F9/aj2jo5b5mdY7cTzp18+JPOWOm49nWcNFOYFkNUkMp+J5FqxNvp609PM8Zd1soFx CdYu2NdG/tlf2ZNwPK0zwWWNZvvEqxABiGwkMuCs0YCOx4W1Fgi5ysXT5MDgsO9WLvRf 8tgVhE6gyo8O6lGBRl+/DjvnqiAPqyFng476ohkmyiU6UCvH6Y+iufH4JJcWxG9SP4zd mdzhR4FwkgUYrsZMYdf3xd48gb5+4Ml8Bvhz9PTlfqQcL6t8k/g9uP4D+W3OHC/xergT MogQUYraXcx+V/JPF76wl9dKTZXgrpRhofhQZFZ35oETBECcb4DjQWe12fBYaPMxG+JQ lI+w== X-Gm-Message-State: AOUpUlFwPFk8xWi9mkBX8jsMlwxxeox8+qtvFMXKENI1hPAJI6hluUc7 oK3yzeNyJnumrlHjHSyre9o= X-Google-Smtp-Source: AA+uWPxsLtt4X4PmOEiPu2+0mLGXCveyIOnD/MCjJJS2+wqBIQOkAiefDJVHYXIJtWVedXZVQw9rIg== X-Received: by 2002:a63:4450:: with SMTP id t16-v6mr5734763pgk.102.1533893819642; Fri, 10 Aug 2018 02:36:59 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id u71-v6sm30416717pfk.174.2018.08.10.02.36.58 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 02:36:58 -0700 (PDT) From: Bin Meng To: Simon Glass , George McCollister , U-Boot Mailing List Date: Fri, 10 Aug 2018 02:39:34 -0700 Message-Id: <1533893978-12838-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> References: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 2/6] x86: Remove support for Advantech SOM-6896 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now that we have generic coreboot payload support, remove the dedicated support for Advantech SOM-6896. Signed-off-by: Bin Meng --- arch/x86/dts/Makefile | 1 - arch/x86/dts/broadwell_som-6896.dts | 52 ------------------------------------- include/configs/som-6896.h | 28 -------------------- 3 files changed, 81 deletions(-) delete mode 100644 arch/x86/dts/broadwell_som-6896.dts delete mode 100644 include/configs/som-6896.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index c62540f..fa717bc 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -18,7 +18,6 @@ dtb-y += bayleybay.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ theadorable-x86-dfi-bt700.dtb \ - broadwell_som-6896.dtb \ baytrail_som-db5800-som-6867.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts deleted file mode 100644 index ec691f1..0000000 --- a/arch/x86/dts/broadwell_som-6896.dts +++ /dev/null @@ -1,52 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" -/include/ "serial.dtsi" -/include/ "reset.dtsi" -/include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" - -/ { - model = "Advantech SOM-6896"; - compatible = "advantech,som-6896", "intel,broadwell"; - - aliases { - spi0 = &spi; - }; - - config { - silent_console = <0>; - }; - - chosen { - stdout-path = "/serial"; - }; - - pci { - compatible = "pci-x86"; - #address-cells = <3>; - #size-cells = <2>; - u-boot,dm-pre-reloc; - ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 - 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 - 0x01000000 0x0 0x2000 0x2000 0 0xe000>; - - pch@1f,0 { - reg = <0x0000f800 0 0 0 0>; - compatible = "intel,pch9"; - - spi: spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich9-spi"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q128", "spi-flash"; - memory-map = <0xff000000 0x01000000>; - }; - }; - }; - }; - -}; diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h deleted file mode 100644 index f0e8d61..0000000 --- a/include/configs/som-6896.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SOM-6896 - * - * Copyright (C) 2015 NovaTech LLC - * George McCollister - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_MISC_INIT_R - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x00ff0000 - -#endif /* __CONFIG_H */ From patchwork Fri Aug 10 09:39:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 956163 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="e1oXnBfM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41n0Rb3Q43z9s7Q for ; Fri, 10 Aug 2018 19:38:19 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B5AD9C21DA1; Fri, 10 Aug 2018 09:37:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6518BC21E13; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id u71-v6sm30416717pfk.174.2018.08.10.02.36.59 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 02:37:00 -0700 (PDT) From: Bin Meng To: Simon Glass , George McCollister , U-Boot Mailing List Date: Fri, 10 Aug 2018 02:39:35 -0700 Message-Id: <1533893978-12838-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> References: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 3/6] x86: dts: Remove coreboot_fb.dtsi X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is no need to keep a separate coreboot_fb.dtsi since now we have a generic coreboot payload dts. While we are here, this also remove the out-of-date description in the documentation regarding to coreboot framebuffer driver with U-Boot loaded as a payload from coreboot. As the testing result with QEMU 2.5.0 shows, the driver just works like a charm. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/dts/bayleybay.dts | 1 - arch/x86/dts/chromebook_link.dts | 1 - arch/x86/dts/chromebook_samus.dts | 1 - arch/x86/dts/chromebox_panther.dts | 1 - arch/x86/dts/coreboot_fb.dtsi | 5 ----- arch/x86/dts/minnowmax.dts | 1 - doc/README.x86 | 7 ------- 7 files changed, 17 deletions(-) delete mode 100644 arch/x86/dts/coreboot_fb.dtsi diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 9683c52..291dc07 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -15,7 +15,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Intel Bayley Bay"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 115a088..f9f0979 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -8,7 +8,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 9c48c9a..b58936b 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -8,7 +8,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Samus"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index a72a85e..f56e482 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -5,7 +5,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi deleted file mode 100644 index 7d72f18..0000000 --- a/arch/x86/dts/coreboot_fb.dtsi +++ /dev/null @@ -1,5 +0,0 @@ -/ { - coreboot-fb { - compatible = "coreboot-fb"; - }; -}; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 02ab4c1..6c65fb9 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -14,7 +14,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/doc/README.x86 b/doc/README.x86 index 6015ca4..8cc4672 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -412,17 +412,10 @@ To enable video you must enable these options in coreboot: - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) - Keep VESA framebuffer -And include coreboot_fb.dtsi in your board's device tree source file, like: - - /include/ "coreboot_fb.dtsi" - At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. -Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown -at this point. Patches are welcome if you figure out anything wrong. - Test with QEMU for bare mode ---------------------------- QEMU is a fancy emulator that can enable us to test U-Boot without access to From patchwork Fri Aug 10 09:39:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 956167 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ftrf90zV"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41n0T66kfqz9s7Q for ; Fri, 10 Aug 2018 19:39:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9C697C21DF8; Fri, 10 Aug 2018 09:38:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 71EA4C21E26; Fri, 10 Aug 2018 09:37:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D1849C21DD7; Fri, 10 Aug 2018 09:37:11 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id EDB9AC21DD7 for ; Fri, 10 Aug 2018 09:37:04 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id y5-v6so4157627pgv.1 for ; Fri, 10 Aug 2018 02:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=/yK4gSE0H2T/ViknlnjMI2ePVBIscBdfeMlgCqRwnJk=; b=ftrf90zV352MeHeJ7ScdG4RaAY3/0d5chuegQ2NIBU3YBMWQUbyL714IJ4H1B+P4sg CBJA3fvqjcT/5M5ifNrMZaxSzajgbTfMbvSUTOKVcxkuoioXa5QgdJR1gzlS5RVvDDuN Vm+I/WFUfTJY7uJNkRe7GcgIcCiMFw6KtqhQXWVclpkpSridF9xiKBxIam0rvcYsvDn+ hxn9bl8ochGj0839WoYkeeru0b45KPsRL0/6peBrDQVgMyDKqzA3G2lrqjs7rYQdHF9G XouHMkYQjGguRTiCJTMdXyq+JxGAP2npECA+N8eY23mLaE5477LDaNbAypcF4hNTeL30 fBmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=/yK4gSE0H2T/ViknlnjMI2ePVBIscBdfeMlgCqRwnJk=; b=AM+47lX7F2Rci4BLBWimumUVNLp+3B1g9datALAFuG5XNdjMiZ4Aq6TWgbGFSliLLX sqfaYkhfbku/cdc7jAnqpo4gHmM0XPdF8/yshDgrcrEUSq8c3Stkl0JIa9ZlQE1CsqTO Zp/hq03aNmPYZ22CaDU7cMQ/bDkDj9RnL03DS646srDML3hRcLaLwIotRHZIGZo/2Z1B Rlnn4I02qSxdZtmFmUXIZPEJI0Jz8UJmSum6UtVsDRQybcMVTTWpUVXACpXYIMElRVwI rkgNzUL8UaP2650/KvOknfpXPFDZOgsxGhvOK/4kylBK5yvahPNlPXEug7b83yyKkO6r mYAw== X-Gm-Message-State: AOUpUlEkvwJwS5Fa9IhrCgulVQ0g4BEhim7T+xaxfKZevn9tJHhyA9K0 +nwvU7pyS/6z1hHi3DvSTZY= X-Google-Smtp-Source: AA+uWPyurlvpa0WrJv+aTOOTe0iOZYj349Llhk0vliUlAA7r3dtbN29iuV0Nls0qUshKtD+3ELNy5g== X-Received: by 2002:a62:3601:: with SMTP id d1-v6mr6318925pfa.41.1533893822422; Fri, 10 Aug 2018 02:37:02 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id u71-v6sm30416717pfk.174.2018.08.10.02.37.01 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 02:37:01 -0700 (PDT) From: Bin Meng To: Simon Glass , George McCollister , U-Boot Mailing List Date: Fri, 10 Aug 2018 02:39:36 -0700 Message-Id: <1533893978-12838-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> References: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 4/6] x86: tsc: Try hardware calibration first X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present if TSC frequency is provided in the device tree, it takes precedence over hardware calibration result. This swaps the order to try hardware calibration first and uses device tree as last resort. This can be helpful when a generic dts (eg: coreboot/efi payload) is supposed to work on as many hardware as possible, including emulators like QEMU where TSC hardware calibration sometimes fails. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- drivers/timer/tsc_timer.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 747f190..6473de2 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -341,16 +341,12 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count) return 0; } -static void tsc_timer_ensure_setup(void) +static void tsc_timer_ensure_setup(bool stop) { if (gd->arch.tsc_base) return; gd->arch.tsc_base = rdtsc(); - /* - * If there is no clock frequency specified in the device tree, - * calibrate it by ourselves. - */ if (!gd->arch.clock_rate) { unsigned long fast_calibrate; @@ -366,7 +362,10 @@ static void tsc_timer_ensure_setup(void) if (fast_calibrate) goto done; - panic("TSC frequency is ZERO"); + if (stop) + panic("TSC frequency is ZERO"); + else + return; done: gd->arch.clock_rate = fast_calibrate * 1000000; @@ -377,11 +376,17 @@ static int tsc_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - if (!uc_priv->clock_rate) { - tsc_timer_ensure_setup(); - uc_priv->clock_rate = gd->arch.clock_rate; + /* Try hardware calibration first */ + tsc_timer_ensure_setup(false); + if (!gd->arch.clock_rate) { + /* + * Use the clock frequency specified in the + * device tree as last resort + */ + if (!uc_priv->clock_rate) + panic("TSC frequency is ZERO"); } else { - gd->arch.tsc_base = rdtsc(); + uc_priv->clock_rate = gd->arch.clock_rate; } return 0; @@ -394,7 +399,7 @@ unsigned long notrace timer_early_get_rate(void) * clock rate can only be calibrated via some hardware ways. Specifying * it in the device tree won't work for the early timer. */ - tsc_timer_ensure_setup(); + tsc_timer_ensure_setup(true); return gd->arch.clock_rate; } From patchwork Fri Aug 10 09:39:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 956166 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WDkcxdzu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41n0Sp5Dxnz9s7Q for ; Fri, 10 Aug 2018 19:39:22 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 65F23C21DC1; Fri, 10 Aug 2018 09:38:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6DD7DC21D74; Fri, 10 Aug 2018 09:37:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6D943C21DF8; Fri, 10 Aug 2018 09:37:12 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 2726DC21DCA for ; Fri, 10 Aug 2018 09:37:05 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id z8-v6so4142549pgu.8 for ; Fri, 10 Aug 2018 02:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=2VOSB+N1WF0cBWOAB3Gqa82TLziYqSMbSyg2sxernig=; b=WDkcxdzu79r33mvoZ0IjPkTD+6X3ggb9lvrLdqm6YAnXPg1M51hHw4/yrlc6d4sr0I nS+Aqd9d2ZcCbsN8B8HlnpCG8d1W1rG2vmkPd3G50/AMidUE3JeTuavdhLHtgNDW88W+ Bm8Pv8P/JHtJCNOdtJAWrFWetdl0c86J79m18yoGxcMSkalmULPOLHKc46Pqm4QUijOx 9PgK8qWiNhQdCLFiJAOzVFQkLFkUFrgt0yquwGT3LygugBwhOoKx2yVN/cmfS8ufEVAl ApPXrINQdjD8ucc96ZrH3O/sCeizPRaDG8vogFseSu7JNh6AL4MtF/Lwedh7QIe++4XZ gtEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=2VOSB+N1WF0cBWOAB3Gqa82TLziYqSMbSyg2sxernig=; b=lzAPex8c+zHY+dVIh1LbXBGayfJ2ixYd4xjmF0xQJXRxW1enLXn8jIXzN92TT/UGub clnyDI1J2kv7XyePOLyZn3oZkynJs7ihg12vVrPa/IRClxABIS1nj0DffV730qrh5jCs ef+/HfOrHycQqnxo4o+HYG2WXrAZERv1q988JLBnpOuMYbSkcS9b9md9Ye/Hj+eqpYHA aWHb0a5fNUcc6G9rorQMh/3cWQ8mrYsmy9W5ea0O1jYEGRQGEDULDcy/fZQ9UBCxeyYN WHgRycAmromSKPF+J+/Edej5fIcggwp8TjJl3iV+NWR6DsJ1xOn5wajE/DWVLBwAcImf KVsg== X-Gm-Message-State: AOUpUlHVTUVHwVtaYplPyMXpJEGrdrYaroO/fiIjgYx/+IRnqmMQmH4i goSY77q2hMK+Ilp1ZG3naTE= X-Google-Smtp-Source: AA+uWPyjkXgEASJzzcKrfiyoolVQf7EmHfvlheIN0Ob+15q359MZOVwVBbHzVe4e11tSTvQ3bnvxwQ== X-Received: by 2002:a62:5b85:: with SMTP id p127-v6mr6395207pfb.33.1533893823864; Fri, 10 Aug 2018 02:37:03 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id u71-v6sm30416717pfk.174.2018.08.10.02.37.02 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 02:37:02 -0700 (PDT) From: Bin Meng To: Simon Glass , George McCollister , U-Boot Mailing List Date: Fri, 10 Aug 2018 02:39:37 -0700 Message-Id: <1533893978-12838-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> References: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 5/6] x86: coreboot: Add default TSC frequency in the device tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It was observed sometimes U-Boot as the coreboot payload fails to boot on QEMU. This is because TSC calibration fails with no valid frequency. This adds default TSC frequency in the device tree. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- arch/x86/dts/coreboot.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index a94f781..e212f3d 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; From patchwork Fri Aug 10 09:39:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 956165 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="m9CazUVB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41n0Sg5x5pz9s7Q for ; Fri, 10 Aug 2018 19:39:15 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 842C4C21DC1; Fri, 10 Aug 2018 09:38:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C87AC21DFA; Fri, 10 Aug 2018 09:37:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A4139C21DA2; Fri, 10 Aug 2018 09:37:12 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 8684AC21E02 for ; Fri, 10 Aug 2018 09:37:06 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id n7-v6so4148258pgq.4 for ; Fri, 10 Aug 2018 02:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=Kom6bTslJQ4M4LlJJ61ryjSy3mEOrQHOt25VzWvdY5s=; b=m9CazUVBVuz5YrU9hZj0mfNfzOXt3UkngE8VxeYVeXZ9TzNf80gFbCeNDiT2oNgj7t afO5aMKV+pZ68RFX3DFH4liPg4b1Od4/NtQ+4vjvHofzx28O0pjWAGIfMzRVYYaKdyy4 CfAyCQ9DVEJbQKO+j/rVmVOmHLTZ9sPL7pYCDjmu6O7LpgVNqvAsshntirZuKiCqZ5zG 1ebIgZ8xwNn/P4B30LnBviKGWrWy/HWBDXte21/XHg5cKKktaVa96TWgwPMzO0Gtes2v ZY2/KQnKkPh4nRWvnPxx8J6ru0dWMwSI6NYhMztLjcN7cL4W2qR6r4MmizU+2nfEI4++ woIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Kom6bTslJQ4M4LlJJ61ryjSy3mEOrQHOt25VzWvdY5s=; b=jLb7OR1OO5JKtsY235TduHvuOihs5FXr+AgtIi/SMl9QDfnD5humzffjHm/FJJ/U0E jWkYa9YzQt3IFkV0ufzbDpbjy+T3gGeoYXGoAjQBKhWBdFF4UN7fg+zHV/IxBRKE2W4k bS5k7ebNgNjZNp3W0dqrLUe31Jf6lmXTpS8I4j7g+LIFUx+dC3bp2Z8bRGaIss88RK3K ylwcf4uwJxdjdCZ3T2HD8pocvLvwvbDvQS2DKDWVjjLpJtL6fF7j839e3ZYPETtleZwZ 7d6RtkkllDJzWhzx092iJGp49wqQV07ewWwovGYB+M3/LCM1bd7uFcoR3IJ6bQvk/XWK 47Xg== X-Gm-Message-State: AOUpUlFLJkZeL6c631zfd3sqpxEh3TpQGsbk4VQqJJtqFJbNwr/54B7w gkvozhxc/ydMLKabGnz2EHs= X-Google-Smtp-Source: AA+uWPwilTE+06ZYqZXXjNKAWlQWeEkO8n9tNYDD+jPUkNau3uDvqfg80zpkE1jZ/Yi2bTr7KnVcEw== X-Received: by 2002:a62:3a5b:: with SMTP id h88-v6mr6304959pfa.61.1533893825230; Fri, 10 Aug 2018 02:37:05 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id u71-v6sm30416717pfk.174.2018.08.10.02.37.03 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 02:37:04 -0700 (PDT) From: Bin Meng To: Simon Glass , George McCollister , U-Boot Mailing List Date: Fri, 10 Aug 2018 02:39:38 -0700 Message-Id: <1533893978-12838-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> References: <1533893978-12838-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 6/6] x86: efi: payload: Add default TSC frequency in the device tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It was observed sometimes U-Boot as the EFI payload fails to boot on QEMU. This is because TSC calibration fails with no valid frequency. This adds default TSC frequency in the device tree. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/dts/efi-x86_payload.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts index 19f2530..5ccb986 100644 --- a/arch/x86/dts/efi-x86_payload.dts +++ b/arch/x86/dts/efi-x86_payload.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc;