From patchwork Fri Aug 10 07:48:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 956028 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41my3k6YStz9s7Q for ; Fri, 10 Aug 2018 17:50:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8DEA3C21D56; Fri, 10 Aug 2018 07:50:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DC251C21E12; Fri, 10 Aug 2018 07:48:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5ACDEC21C27; Fri, 10 Aug 2018 07:48:23 +0000 (UTC) Received: from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212]) by lists.denx.de (Postfix) with ESMTPS id BDAB4C21C27 for ; Fri, 10 Aug 2018 07:48:22 +0000 (UTC) Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.mailbox.org (Postfix) with ESMTPS id A9BB0481C5; Fri, 10 Aug 2018 09:48:22 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter03.heinlein-hosting.de (spamfilter03.heinlein-hosting.de [80.241.56.117]) (amavisd-new, port 10030) with ESMTP id rn8tA1EaECRY; Fri, 10 Aug 2018 09:48:19 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 10 Aug 2018 09:48:15 +0200 Message-Id: <20180810074819.24962-1-sr@denx.de> Subject: [U-Boot] [PATCH 1/5 v2] mips: Add basic MediaTek MT7620/88 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- v2: - Sort Kconfig symbols alphabetically - Use MIPS_TUNE_24KC - Use imply for SPI support - Dont' add LinkIt module support yet (is added with the board support) - Move SKIP_LOWLEVEL_INIT from Kconfig to config header - Use DT to get the base address of the system controller (for display_cpuinfo) - Remove _machine_restart - a separate driver is provided in a new patch - Remove cachop_op() and cal_invalidate_dcache_range and use the generic invalidate_dcache_range function instead Daniel I tried to change to CPU_HAS PREFETCH, but this did not work smoothly. It seems this option is very old and outdated. Perhaps I can revisit this again, once this patchset has settled a bit. arch/mips/Kconfig | 15 ++ arch/mips/Makefile | 1 + arch/mips/mach-mt7620/Kconfig | 113 +++++++++ arch/mips/mach-mt7620/Makefile | 8 + arch/mips/mach-mt7620/cpu.c | 72 ++++++ arch/mips/mach-mt7620/ddr_calibrate.c | 307 +++++++++++++++++++++++ arch/mips/mach-mt7620/lowlevel_init.S | 337 ++++++++++++++++++++++++++ arch/mips/mach-mt7620/mt76xx.h | 38 +++ 8 files changed, 891 insertions(+) create mode 100644 arch/mips/mach-mt7620/Kconfig create mode 100644 arch/mips/mach-mt7620/Makefile create mode 100644 arch/mips/mach-mt7620/cpu.c create mode 100644 arch/mips/mach-mt7620/ddr_calibrate.c create mode 100644 arch/mips/mach-mt7620/lowlevel_init.S create mode 100644 arch/mips/mach-mt7620/mt76xx.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31b622ff51..b7c5fa3114 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -87,6 +87,20 @@ config ARCH_BMIPS select SYSRESET imply CMD_DM +config ARCH_MT7620 + bool "Support MT7620/7688 SoCs" + select DISPLAY_CPUINFO + select DM + select DM_SERIAL + imply DM_SPI + imply DM_SPI_FLASH + select MIPS_TUNE_24KC + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -141,6 +155,7 @@ source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" +source "arch/mips/mach-mt7620/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5deec9a202..cc8ea5d7d4 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_SOC_AU1X00) += au1x00 machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 +machine-$(CONFIG_ARCH_MT7620) += mt7620 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig new file mode 100644 index 0000000000..396fbd0141 --- /dev/null +++ b/arch/mips/mach-mt7620/Kconfig @@ -0,0 +1,113 @@ +menu "MediaTek MIPS platforms" + depends on ARCH_MT7620 + +config SYS_MALLOC_F_LEN + default 0x1000 + +config SYS_SOC + default "mt7620" if SOC_MT7620 + +choice + prompt "MediaTek MIPS SoC select" + +config SOC_MT7620 + bool "MT7620/8" + select MIPS_L1_CACHE_SHIFT_5 + help + This supports MediaTek MIPS MT7620 family. + +endchoice + +choice + prompt "Board select" + +endchoice + +choice + prompt "Boot mode" + +config BOOT_RAM + bool "RAM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a RAM address. It can be used + for booting from CFE via TFTP using an ELF image, but it can also be + booted from RAM by other bootloaders using a BIN image. + +config BOOT_ROM + bool "ROM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a ROM address. It can be + used as main bootloader image which is programmed onto the onboard + flash storage (SPI NOR). + +endchoice + +choice + prompt "DDR2 size" + +config ONBOARD_DDR2_SIZE_256MBIT + bool "256MBit (32MByte) total size" + depends on BOOT_ROM + help + Use 256MBit (32MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_512MBIT + bool "512MBit (64MByte) total size" + depends on BOOT_ROM + help + Use 512MBit (64MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_1024MBIT + bool "1024MBit (128MByte) total size" + depends on BOOT_ROM + help + Use 1024MBit (128MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_2048MBIT + bool "2048MBit (256MByte) total size" + depends on BOOT_ROM + help + Use 2048MBit (256MByte) of DDR total size + +endchoice + +choice + prompt "DDR2 chip width" + +config ONBOARD_DDR2_CHIP_WIDTH_8BIT + bool "8bit DDR chip width" + depends on BOOT_ROM + help + Use DDR chips with 8bit width + +config ONBOARD_DDR2_CHIP_WIDTH_16BIT + bool "16bit DDR chip width" + depends on BOOT_ROM + help + Use DDR chips with 16bit width + +endchoice + +choice + prompt "DDR2 bus width" + +config ONBOARD_DDR2_BUS_WIDTH_16BIT + bool "16bit DDR bus width" + depends on BOOT_ROM + help + Use 16bit DDR bus width + +config ONBOARD_DDR2_BUS_WIDTH_32BIT + bool "32bit DDR bus width" + depends on BOOT_ROM + help + Use 32bit DDR bus width + +endchoice + +config SUPPORTS_BOOT_RAM + bool + +endmenu diff --git a/arch/mips/mach-mt7620/Makefile b/arch/mips/mach-mt7620/Makefile new file mode 100644 index 0000000000..1f3e65e8a5 --- /dev/null +++ b/arch/mips/mach-mt7620/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += cpu.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +obj-y += ddr_calibrate.o +obj-y += lowlevel_init.o +endif diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c new file mode 100644 index 0000000000..f21209522b --- /dev/null +++ b/arch/mips/mach-mt7620/cpu.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include +#include +#include +#include +#include +#include "mt76xx.h" + +#define STR_LEN 6 + +#ifdef CONFIG_BOOT_ROM +int mach_cpu_init(void) +{ + void (*ptr)(void); + + /* + * DDR calibration routine needs to be called very early. This + * function also configures the clock to run at full speed. + */ + ptr = (void *)CKSEG0ADDR(ddr_calibrate); + (*ptr)(); + + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M); + + return 0; +} + +int print_cpuinfo(void) +{ + static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)", + "PLL (4-Byte SPI Addr)", + "XTAL (3-Byte SPI Addr)", + "XTAL (4-Byte SPI Addr)" }; + const void *blob = gd->fdt_blob; + char buf[STR_LEN + 1]; + fdt_addr_t base; + char *str; + int node; + u32 val; + + /* Get system controller base address */ + node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", + 0, NULL, true); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + str = (char *)base + MT76XX_CHIPID_OFFS; + snprintf(buf, STR_LEN + 1, "%s", str); + val = readl((void *)base + MT76XX_CHIP_REV_ID_OFFS); + printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf, + (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0)); + + val = (readl((void *)base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1; + printf("Boot from %s\n", boot_str[val]); + + return 0; +} diff --git a/arch/mips/mach-mt7620/ddr_calibrate.c b/arch/mips/mach-mt7620/ddr_calibrate.c new file mode 100644 index 0000000000..623816019b --- /dev/null +++ b/arch/mips/mach-mt7620/ddr_calibrate.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + * + * Most functions in this file are copied from the MediaTek U-Boot + * repository. Without any documentation, it was impossible to really + * implement this differently. So its mostly a cleaned-up version of + * the original code, with only support for the MT7628 / MT7688 SoC. + */ + +#include +#include +#include +#include +#include "mt76xx.h" + +#define NUM_OF_CACHELINE 64 +#define MIN_START 6 +#define MIN_FINE_START 0xf +#define MAX_START 7 +#define MAX_FINE_START 0x0 + +#define CPU_FRAC_DIV 1 + +#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) +#define DRAM_BUTTOM 0x02000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) +#define DRAM_BUTTOM 0x04000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) +#define DRAM_BUTTOM 0x08000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) +#define DRAM_BUTTOM 0x10000000 +#endif + +static inline void cal_memcpy(void *src, void *dst, u32 size) +{ + u8 *psrc = (u8 *)src; + u8 *pdst = (u8 *)dst; + int i; + + for (i = 0; i < size; i++, psrc++, pdst++) + *pdst = *psrc; +} + +static inline void cal_memset(void *src, u8 pat, u32 size) +{ + u8 *psrc = (u8 *)src; + int i; + + for (i = 0; i < size; i++, psrc++) + *psrc = pat; +} + +#define pref_op(hint, addr) \ + __asm__ __volatile__( \ + ".set push\n" \ + ".set noreorder\n" \ + "pref %0, %1\n" \ + ".set pop\n" \ + : \ + : "i" (hint), "R" (*(u8 *)(addr))) + +static inline void cal_patgen(u32 start_addr, u32 size, u32 bias) +{ + u32 *addr = (u32 *)start_addr; + int i; + + for (i = 0; i < size; i++) + addr[i] = start_addr + i + bias; +} + +static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs, + u32 offs, u32 pat, u32 val) +{ + u32 nc_addr; + u32 *c_addr; + int i; + + for (nc_addr = 0xa0000000; + nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32); + nc_addr += (DRAM_BUTTOM >> 6) + offs) { + writel(0x00007474, MT76XX_MEMCTRL_BASE + 0x64); + wmb(); /* Make sure store if finished */ + + c_addr = (u32 *)(nc_addr & 0xdfffffff); + cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32); + cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat); + + if (dqs > 0) + writel(0x00000074 | + (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) | + (((k == 0) ? val : test_dqs) << 8), + MT76XX_MEMCTRL_BASE + 0x64); + else + writel(0x00007400 | + (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) | + (((k == 0) ? val : test_dqs) << 0), + MT76XX_MEMCTRL_BASE + 0x64); + wmb(); /* Make sure store if finished */ + + invalidate_dcache_range((u32)c_addr, + (u32)c_addr + + NUM_OF_CACHELINE * 32); + wmb(); /* Make sure store if finished */ + + for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { + if (i % 8 == 0) + pref_op(0, &c_addr[i]); + } + + for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { + if (c_addr[i] != nc_addr + i + pat) + return -1; + } + } + + return 0; +} + +void ddr_calibrate(void) +{ + u32 min_coarse_dqs[2]; + u32 max_coarse_dqs[2]; + u32 min_fine_dqs[2]; + u32 max_fine_dqs[2]; + u32 coarse_dqs[2]; + u32 fine_dqs[2]; + int reg = 0, ddr_cfg2_reg; + int flag; + int i, k; + int dqs = 0; + u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll; + u32 val; + u32 fdiv = 0, frac = 0; + + /* Setup clock to run at full speed */ + val = readl(MT76XX_DYN_CFG0_REG); + fdiv = (u32)((val >> 8) & 0x0F); + if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10) + frac = val & 0x0f; + else + frac = CPU_FRAC_DIV; + + while (frac < fdiv) { + val = readl(MT76XX_DYN_CFG0_REG); + fdiv = (val >> 8) & 0x0f; + fdiv--; + val &= ~(0x0f << 8); + val |= (fdiv << 8); + writel(val, MT76XX_DYN_CFG0_REG); + udelay(500); + val = readl(MT76XX_DYN_CFG0_REG); + fdiv = (val >> 8) & 0x0f; + } + + clrbits_le32(MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + ddr_cfg2_reg = readl(MT76XX_MEMCTRL_BASE + 0x48); + clrbits_le32(MT76XX_MEMCTRL_BASE + 0x48, (0x3 << 28) | (0x3 << 26)); + + min_coarse_dqs[0] = MIN_START; + min_coarse_dqs[1] = MIN_START; + min_fine_dqs[0] = MIN_FINE_START; + min_fine_dqs[1] = MIN_FINE_START; + max_coarse_dqs[0] = MAX_START; + max_coarse_dqs[1] = MAX_START; + max_fine_dqs[0] = MAX_FINE_START; + max_fine_dqs[1] = MAX_FINE_START; + dqs = 0; + + /* Add by KP, DQS MIN boundary */ + reg = readl(MT76XX_MEMCTRL_BASE + 0x20); + coarse_dqs_dll = (reg & 0xf00) >> 8; + fine_dqs_dll = (reg & 0xf0) >> 4; + if (coarse_dqs_dll <= 8) + min_coarse_dqs_bnd = 8 - coarse_dqs_dll; + else + min_coarse_dqs_bnd = 0; + + if (fine_dqs_dll <= 8) + min_fine_dqs_bnd = 8 - fine_dqs_dll; + else + min_fine_dqs_bnd = 0; + /* DQS MIN boundary */ + +DQS_CAL: + + for (k = 0; k < 2; k++) { + u32 test_dqs; + + if (k == 0) + test_dqs = MAX_START; + else + test_dqs = MAX_FINE_START; + + do { + flag = test_loop(k, dqs, test_dqs, max_coarse_dqs, + 0x400, 0x3, 0xf); + if (flag == -1) + break; + + test_dqs++; + } while (test_dqs <= 0xf); + + if (k == 0) { + max_coarse_dqs[dqs] = test_dqs; + } else { + test_dqs--; + + if (test_dqs == MAX_FINE_START - 1) { + max_coarse_dqs[dqs]--; + max_fine_dqs[dqs] = 0xf; + } else { + max_fine_dqs[dqs] = test_dqs; + } + } + } + + for (k = 0; k < 2; k++) { + u32 test_dqs; + + if (k == 0) + test_dqs = MIN_START; + else + test_dqs = MIN_FINE_START; + + do { + flag = test_loop(k, dqs, test_dqs, min_coarse_dqs, + 0x480, 0x1, 0x0); + if (k == 0) { + if (flag == -1 || + test_dqs == min_coarse_dqs_bnd) + break; + + test_dqs--; + + if (test_dqs < min_coarse_dqs_bnd) + break; + } else { + if (flag == -1) { + test_dqs++; + break; + } else if (test_dqs == min_fine_dqs_bnd) { + break; + } + + test_dqs--; + + if (test_dqs < min_fine_dqs_bnd) + break; + } + } while (test_dqs >= 0); + + if (k == 0) { + min_coarse_dqs[dqs] = test_dqs; + } else { + if (test_dqs == MIN_FINE_START + 1) { + min_coarse_dqs[dqs]++; + min_fine_dqs[dqs] = 0x0; + } else { + min_fine_dqs[dqs] = test_dqs; + } + } + } + + if (dqs == 0) { + dqs = 1; + goto DQS_CAL; + } + + for (i = 0; i < 2; i++) { + u32 temp; + + coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1; + temp = + (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) + + ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1); + if (temp >= 0x10) { + coarse_dqs[i]++; + fine_dqs[i] = (temp - 0x10) + 0x8; + } else { + fine_dqs[i] = temp; + } + } + reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) | + (coarse_dqs[0] << 4) | fine_dqs[0]; + + clrbits_le32(MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + writel(reg, MT76XX_MEMCTRL_BASE + 0x64); + writel(ddr_cfg2_reg, MT76XX_MEMCTRL_BASE + 0x48); + setbits_le32(MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + + for (i = 0; i < 2; i++) + debug("[%02X%02X%02X%02X]", min_coarse_dqs[i], + min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]); + debug("\nDDR Calibration DQS reg = %08X\n", reg); +} diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S new file mode 100644 index 0000000000..92b2fcd2bb --- /dev/null +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2018 Stefan Roese + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include +#include +#include +#include +#include "mt76xx.h" + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define DELAY_USEC(us) ((us) / 100) + +#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16) +#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12) + +#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) +#define DDR_CFG1_SIZE_VAL 0x222e2323 +#define DDR_CFG4_SIZE_VAL 7 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) +#define DDR_CFG1_SIZE_VAL 0x22322323 +#define DDR_CFG4_SIZE_VAL 9 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) +#define DDR_CFG1_SIZE_VAL 0x22362323 +#define DDR_CFG4_SIZE_VAL 9 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) +#define DDR_CFG1_SIZE_VAL 0x223a2323 +#define DDR_CFG4_SIZE_VAL 9 +#endif + +#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT) +#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16) +#endif +#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT) +#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16) +#endif + +#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT) +#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12) +#endif +#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT) +#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12) +#endif + +LEAF(lowlevel_init) + /* polling CPLL is ready */ + li t1, DELAY_USEC(1000000) + la t5, MT76XX_ROM_STATUS_REG +1: + lw t2, 0(t5) + andi t2, t2, 0x1 + bnez t2, CPLL_READY + subu t1, t1, 1 + bgtz t1, 1b + nop + la t0, MT76XX_CLKCFG0_REG + lw t3, 0(t0) + ori t3, t3, 0x1 + sw t3, 0(t0) + j CPLL_DONE + nop +CPLL_READY: + la t0, MT76XX_CLKCFG0_REG + lw t1, 0(t0) + li t2, ~0x0c + and t1, t1, t2 + ori t1, t1, 0xc + sw t1, 0(t0) + la t0, MT76XX_DYN_CFG0_REG + lw t3, 0(t0) + li t5, ~((0x0f << 8) | (0x0f << 0)) + and t3, t3, t5 + li t5, (10 << 8) | (1 << 0) + or t3, t3, t5 + sw t3, 0(t0) + la t0, MT76XX_CLKCFG0_REG + lw t3, 0(t0) + li t4, ~0x0F + and t3, t3, t4 + ori t3, t3, 0xc + sw t3, 0(t0) + lw t3, 0(t0) + ori t3, t3, 0x08 + sw t3, 0(t0) + +CPLL_DONE: + /* + * SDR and DDR initialization: delay 200us + */ + li t0, DELAY_USEC(200 + 40) + li t1, 0x1 +1: + sub t0, t0, t1 + bnez t0, 1b + nop + + /* set DRAM IO PAD for MT7628IC */ + /* DDR LDO Enable */ + li t1, MT76XX_RGCTRL_BASE+0x100 + lw t4, 0(t1) + li t2, BIT(31) + or t4, t4, t2 + sw t4, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x10c + lw t4, 0(t1) + j LDO_1P8V + nop +LDO_1P8V: + li t2, ~BIT(6) + and t4, t4, t2 + li t1, MT76XX_RGCTRL_BASE+0x10c + sw t4, 0(t1) + j DDRLDO_SOFT_START +LDO_2P5V: + /* suppose external DDR1 LDO 2.5V */ + li t2, BIT(6) + or t4, t4, t2 + li t1, MT76XX_RGCTRL_BASE+0x10c + sw t4, 0(t1) + +DDRLDO_SOFT_START: + li t1, MT76XX_RGCTRL_BASE+0x10c + lw t2, 0(t1) + li t3, BIT(16) + or t2, t2, t3 + sw t2, 0(t1) + li t3, DELAY_USEC(250*50) +LDO_DELAY: + subu t3, t3, 1 + bnez t3, LDO_DELAY + nop + + li t1, MT76XX_RGCTRL_BASE+0x10c + lw t2, 0(t1) + li t3, BIT(18) + or t2, t2, t3 + sw t2, 0(t1) + +SET_RG_BUCK_FPWM: + li t1, MT76XX_RGCTRL_BASE+0x104 + lw t2, 0(t1) + ori t2, t2, BIT(10) + sw t2, 0(t1) + +DDR_PAD_CFG: + /* clean CLK PAD */ + li t1, MT76XX_RGCTRL_BASE+0x704 + lw t2, 0(t1) + li t8, 0xfffff0f0 + and t2, t2, t8 + /* clean CMD PAD */ + li t1, MT76XX_RGCTRL_BASE+0x70c + lw t3, 0(t1) + li t8, 0xfffff0f0 + and t3, t3, t8 + /* clean DQ IPAD */ + li t1, MT76XX_RGCTRL_BASE+0x710 + lw t4, 0(t1) + li t8, 0xfffff8ff + and t4, t4, t8 + /* clean DQ OPAD */ + li t1, MT76XX_RGCTRL_BASE+0x714 + lw t5, 0(t1) + li t8, 0xfffff0f0 + and t5, t5, t8 + /* clean DQS IPAD */ + li t1, MT76XX_RGCTRL_BASE+0x718 + lw t6, 0(t1) + li t8, 0xfffff8ff + and t6, t6, t8 + /* clean DQS OPAD */ + li t1, MT76XX_RGCTRL_BASE+0x71c + lw t7, 0(t1) + li t8, 0xfffff0f0 + and t7, t7, t8 + + li t1, MT76XX_SYSCTL_BASE+0xC + lw t9, 0(t1) + srl t9, t9, 16 + andi t9, t9, 0x1 + bnez t9, MT7628_AN_DDR1_PAD +MT7628_KN_PAD: + li t8, 0x00000303 + or t2, t2, t8 + or t3, t3, t8 + or t5, t5, t8 + or t7, t7, t8 + li t8, 0x00000000 + or t4, t4, t8 + or t6, t6, t8 + j SET_PAD_CFG +MT7628_AN_DDR1_PAD: + li t1, MT76XX_SYSCTL_BASE+0x10 + lw t1, 0(t1) + andi t1, t1, 0x1 + beqz t1, MT7628_AN_DDR2_PAD + li t8, 0x00000c0c + or t2, t2, t8 + li t8, 0x00000202 + or t3, t3, t8 + li t8, 0x00000707 + or t5, t5, t8 + li t8, 0x00000c0c + or t7, t7, t8 + li t8, 0x00000000 + or t4, t4, t8 + or t6, t6, t8 + j SET_PAD_CFG +MT7628_AN_DDR2_PAD: + li t8, 0x00000c0c + or t2, t2, t8 + li t8, 0x00000202 + or t3, t3, t8 + li t8, 0x00000404 + or t5, t5, t8 + li t8, 0x00000c0c + or t7, t7, t8 + li t8, 0x00000000 /* ODT off */ + or t4, t4, t8 + or t6, t6, t8 + +SET_PAD_CFG: + li t1, MT76XX_RGCTRL_BASE+0x704 + sw t2, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x70c + sw t3, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x710 + sw t4, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x714 + sw t5, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x718 + sw t6, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x71c + sw t7, 0(t1) + + /* + * DDR initialization: reset pin to 0 + */ + li t1, MT76XX_SYSCTL_BASE + 0x34 + lw t2, 0(t1) + and t2, ~BIT(10) + sw t2, 0(t1) + nop + + /* + * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready) + */ +DDR_READY: + li t1, DDR_CFG1_REG + lw t0, 0(t1) + nop + and t2, t0, BIT(21) + beqz t2, DDR_READY + nop + + /* + * DDR initialization + * + * Only DDR2 supported right now. DDR2 support can be added, once + * boards using it will get added to mainline U-Boot. + */ + li t1, DDR_CFG2_REG + lw t0, 0(t1) + nop + and t0, ~BIT(30) + and t0, ~(7 << 4) + or t0, (4 << 4) + or t0, BIT(30) + or t0, BIT(11) + sw t0, 0(t1) + nop + + li t1, DDR_CFG3_REG + lw t2, 0(t1) + /* Disable ODT; reference board ok, ev board fail */ + and t2, ~BIT(6) + or t2, BIT(2) + li t0, DDR_CFG4_REG + lw t1, 0(t0) + li t2, ~(0x01f | 0x0f0) + and t1, t1, t2 + ori t1, t1, DDR_CFG4_SIZE_VAL + sw t1, 0(t0) + nop + + /* + * DDR initialization: config size and width on reg DDR_CFG1 + */ + li t6, DDR_CFG1_SIZE_VAL + + and t6, ~DDR_CFG1_CHIP_WIDTH_MASK + or t6, DDR_CFG1_CHIP_WIDTH_VAL + + /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */ + and t6, ~DDR_CFG1_BUS_WIDTH_MASK + or t6, DDR_CFG1_BUS_WIDTH_VAL + + li t5, DDR_CFG1_REG + sw t6, 0(t5) + nop + + /* + * DDR: enable self auto refresh for power saving + * enable it by default for both RAM and ROM version (for CoC) + */ + li t0, MT76XX_MEMCTRL_BASE + 0x14 + lw t1, 0(t0) + nop + and t1, 0xff000000 + or t1, 0x01 + sw t1, 0(t0) + nop + li t0, MT76XX_MEMCTRL_BASE + 0x10 + lw t1, 0(t0) + nop + or t1, 0x10 + sw t1, 0(t0) + nop + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-mt7620/mt76xx.h b/arch/mips/mach-mt7620/mt76xx.h new file mode 100644 index 0000000000..fb3d4582bf --- /dev/null +++ b/arch/mips/mach-mt7620/mt76xx.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __MT76XX_H +#define __MT76XX_H + +#ifdef __ASSEMBLY__ +#define VOID_PTR +#else +#define VOID_PTR (void *) +#endif + +#define MT76XX_SYSCTL_BASE 0xb0000000 + +#define MT76XX_CHIPID_OFFS 0x00 +#define MT76XX_CHIP_REV_ID_OFFS 0x0c +#define MT76XX_SYSCFG0_OFFS 0x10 + +#define MT76XX_MEMCTRL_BASE (VOID_PTR(MT76XX_SYSCTL_BASE + 0x0300)) +#define MT76XX_RGCTRL_BASE (VOID_PTR(MT76XX_SYSCTL_BASE + 0x1000)) + +#define MT76XX_ROM_STATUS_REG (VOID_PTR(MT76XX_SYSCTL_BASE + 0x0028)) +#define MT76XX_CLKCFG0_REG (VOID_PTR(MT76XX_SYSCTL_BASE + 0x002c)) +#define MT76XX_DYN_CFG0_REG (VOID_PTR(MT76XX_SYSCTL_BASE + 0x0440)) + +#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) +#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48) +#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c) +#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50) + +#ifndef __ASSEMBLY__ +/* Prototypes */ +void ddr_calibrate(void); +#endif + +#endif From patchwork Fri Aug 10 07:48:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 956024 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41my0v489Zz9s5b for ; Fri, 10 Aug 2018 17:48:31 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 4BB81C21DD9; Fri, 10 Aug 2018 07:48:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1AD54C21C50; Fri, 10 Aug 2018 07:48:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AE3B2C21C27; Fri, 10 Aug 2018 07:48:21 +0000 (UTC) Received: from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212]) by lists.denx.de (Postfix) with ESMTPS id 7563EC21BE5 for ; Fri, 10 Aug 2018 07:48:21 +0000 (UTC) Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.mailbox.org (Postfix) with ESMTPS id 4DCAB43063; Fri, 10 Aug 2018 09:48:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter03.heinlein-hosting.de (spamfilter03.heinlein-hosting.de [80.241.56.117]) (amavisd-new, port 10030) with ESMTP id fV-UUJBLK4zc; Fri, 10 Aug 2018 09:48:20 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 10 Aug 2018 09:48:16 +0200 Message-Id: <20180810074819.24962-2-sr@denx.de> In-Reply-To: <20180810074819.24962-1-sr@denx.de> References: <20180810074819.24962-1-sr@denx.de> Subject: [U-Boot] [PATCH 2/5 v2] mips: Add arch/mips/include/asm/atomic.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is needed for the UBIFS support. The file is a copy of arch/xtensa/include/asm/atomic.h Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- v2: - No change arch/mips/include/asm/atomic.h | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 arch/mips/include/asm/atomic.h diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h new file mode 100644 index 0000000000..7551bf6e6c --- /dev/null +++ b/arch/mips/include/asm/atomic.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + */ + +#ifndef _MIPS_ATOMIC_H +#define _MIPS_ATOMIC_H + +#include + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v, i) ((v)->counter = (i)) + +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + ++v->counter; + local_irq_restore(flags); +} + +static inline void atomic_dec(atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + --v->counter; + local_irq_restore(flags); +} + +#endif From patchwork Fri Aug 10 07:48:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 956027 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41my346wNsz9s5b for ; Fri, 10 Aug 2018 17:50:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id AE777C21DA2; Fri, 10 Aug 2018 07:49:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E5EE6C21DB6; Fri, 10 Aug 2018 07:48:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1A7A6C21C4A; Fri, 10 Aug 2018 07:48:22 +0000 (UTC) Received: from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215]) by lists.denx.de (Postfix) with ESMTPS id C341BC21BE5 for ; Fri, 10 Aug 2018 07:48:21 +0000 (UTC) Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id 9B49E41199; Fri, 10 Aug 2018 09:48:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id vfr-F9mlOmks; Fri, 10 Aug 2018 09:48:20 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 10 Aug 2018 09:48:17 +0200 Message-Id: <20180810074819.24962-3-sr@denx.de> In-Reply-To: <20180810074819.24962-1-sr@denx.de> References: <20180810074819.24962-1-sr@denx.de> Subject: [U-Boot] [PATCH 3/5 v2] mips: Add LinkIt Smart 7688 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI NOR). The mt7628a.dtsi file is imported from Linux v4.17. This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- v2: - Kconfig entries added with this patch now arch/mips/dts/linkit-smart-7688.dts | 46 ++++++++ arch/mips/dts/mt7628a.dtsi | 135 ++++++++++++++++++++++ arch/mips/mach-mt7620/Kconfig | 13 +++ board/seeed/linkit-smart-7688/Kconfig | 12 ++ board/seeed/linkit-smart-7688/MAINTAINERS | 8 ++ board/seeed/linkit-smart-7688/Makefile | 3 + board/seeed/linkit-smart-7688/board.c | 22 ++++ configs/linkit-smart-7688-ram_defconfig | 58 ++++++++++ configs/linkit-smart-7688_defconfig | 62 ++++++++++ include/configs/linkit-smart-7688.h | 52 +++++++++ 10 files changed, 411 insertions(+) create mode 100644 arch/mips/dts/linkit-smart-7688.dts create mode 100644 arch/mips/dts/mt7628a.dtsi create mode 100644 board/seeed/linkit-smart-7688/Kconfig create mode 100644 board/seeed/linkit-smart-7688/MAINTAINERS create mode 100644 board/seeed/linkit-smart-7688/Makefile create mode 100644 board/seeed/linkit-smart-7688/board.c create mode 100644 configs/linkit-smart-7688-ram_defconfig create mode 100644 configs/linkit-smart-7688_defconfig create mode 100644 include/configs/linkit-smart-7688.h diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts new file mode 100644 index 0000000000..df4bf907c6 --- /dev/null +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc"; + model = "LinkIt-Smart-7688"; + + aliases { + serial0 = &uart2; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + stdout-path = &uart2; + }; +}; + +&uart2 { + status = "okay"; + clock-frequency = <40000000>; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi new file mode 100644 index 0000000000..d00f528e1f --- /dev/null +++ b/arch/mips/dts/mt7628a.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,mt7628a-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mti,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + resetc: reset-controller { + compatible = "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@10000000 { + compatible = "palmbus", "simple-bus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc: system-controller@0 { + compatible = "ralink,mt7620a-sysc", "syscon"; + reg = <0x0 0x100>; + }; + + intc: interrupt-controller@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&resetc 9>; + reset-names = "intc"; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + ralink,intc-registers = <0x9c 0xa0 + 0x6c 0xa4 + 0x80 0x78>; + }; + + memory-controller@300 { + compatible = "ralink,mt7620a-memc"; + reg = <0x300 0x100>; + }; + + spi0: spi@b00 { + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x40>; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: uartlite@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + resets = <&resetc 12>; + reset-names = "uart0"; + + interrupt-parent = <&intc>; + interrupts = <20>; + + reg-shift = <2>; + }; + + uart1: uart1@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + resets = <&resetc 19>; + reset-names = "uart1"; + + interrupt-parent = <&intc>; + interrupts = <21>; + + reg-shift = <2>; + }; + + uart2: uart2@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + + resets = <&resetc 20>; + reset-names = "uart2"; + + interrupt-parent = <&intc>; + interrupts = <22>; + + reg-shift = <2>; + }; + }; + + usb_phy: usb-phy@10120000 { + compatible = "mediatek,mt7628-usbphy"; + reg = <0x10120000 0x1000>; + + #phy-cells = <0>; + + ralink,sysctl = <&sysc>; + resets = <&resetc 22 &resetc 25>; + reset-names = "host", "device"; + }; + + ehci@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x1000>; + + phys = <&usb_phy>; + phy-names = "usb"; + + interrupt-parent = <&intc>; + interrupts = <18>; + }; +}; diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig index 396fbd0141..ef1211d172 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mt7620/Kconfig @@ -21,6 +21,17 @@ endchoice choice prompt "Board select" +config BOARD_LINKIT_SMART_7688 + bool "LinkIt Smart 7688" + depends on SOC_MT7620 + select SUPPORTS_BOOT_RAM + help + Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM + and 32 MiB of flash (SPI). + Between its different peripherals there's an integrated switch with 4 + ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and + a MT7688 (PCIe). + endchoice choice @@ -110,4 +121,6 @@ endchoice config SUPPORTS_BOOT_RAM bool +source "board/seeed/linkit-smart-7688/Kconfig" + endmenu diff --git a/board/seeed/linkit-smart-7688/Kconfig b/board/seeed/linkit-smart-7688/Kconfig new file mode 100644 index 0000000000..a9d63285c3 --- /dev/null +++ b/board/seeed/linkit-smart-7688/Kconfig @@ -0,0 +1,12 @@ +if BOARD_LINKIT_SMART_7688 + +config SYS_BOARD + default "linkit-smart-7688" + +config SYS_VENDOR + default "seeed" + +config SYS_CONFIG_NAME + default "linkit-smart-7688" + +endif diff --git a/board/seeed/linkit-smart-7688/MAINTAINERS b/board/seeed/linkit-smart-7688/MAINTAINERS new file mode 100644 index 0000000000..c3bbad4231 --- /dev/null +++ b/board/seeed/linkit-smart-7688/MAINTAINERS @@ -0,0 +1,8 @@ +LINKIT_SMART_7688 BOARD +M: Stefan Roese +S: Maintained +F: board/seeed/linkit-smart-7688 +F: include/configs/linkit-smart-7688.h +F: configs/linkit-smart-7688_defconfig +F: configs/linkit-smart-7688_ram_defconfig +F: arch/mips/dts/linkit-smart-7688.dts diff --git a/board/seeed/linkit-smart-7688/Makefile b/board/seeed/linkit-smart-7688/Makefile new file mode 100644 index 0000000000..70cd7a8e56 --- /dev/null +++ b/board/seeed/linkit-smart-7688/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o diff --git a/board/seeed/linkit-smart-7688/board.c b/board/seeed/linkit-smart-7688/board.c new file mode 100644 index 0000000000..fbe94cc292 --- /dev/null +++ b/board/seeed/linkit-smart-7688/board.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include + +#define MT76XX_GPIO1_MODE 0xb0000060 + +void board_debug_uart_init(void) +{ + /* Select UART2 mode instead of GPIO mode (default) */ + clrbits_le32((void __iomem *)MT76XX_GPIO1_MODE, GENMASK(27, 26)); +} + +int board_early_init_f(void) +{ + board_debug_uart_init(); + + return 0; +} diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig new file mode 100644 index 0000000000..4b269f459b --- /dev/null +++ b/configs/linkit-smart-7688-ram_defconfig @@ -0,0 +1,58 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x10000e00 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_ARCH_MT7620=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" +CONFIG_DEBUG_UART=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTE_MODE_ONLY=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_MT76XX_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig new file mode 100644 index 0000000000..cdb8c06517 --- /dev/null +++ b/configs/linkit-smart-7688_defconfig @@ -0,0 +1,62 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xbc000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x10000e00 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_ARCH_MT7620=y +CONFIG_BOOT_ROM=y +CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y +CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" +CONFIG_DEBUG_UART=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTE_MODE_ONLY=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_MT76XX_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h new file mode 100644 index 0000000000..be6cffee35 --- /dev/null +++ b/include/configs/linkit-smart-7688.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __CONFIG_LINKIT_SMART_7688_H +#define __CONFIG_LINKIT_SMART_7688_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#ifdef CONFIG_BOOT_RAM +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE (16 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) + +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +#endif /* __CONFIG_LINKIT_SMART_7688_H */ From patchwork Fri Aug 10 07:48:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 956026 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41my2c2BlLz9s5b for ; Fri, 10 Aug 2018 17:50:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D3C4FC21CB6; Fri, 10 Aug 2018 07:49:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C1845C21DD7; Fri, 10 Aug 2018 07:48:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B904FC21BE5; Fri, 10 Aug 2018 07:48:22 +0000 (UTC) Received: from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212]) by lists.denx.de (Postfix) with ESMTPS id 6A47DC21C27 for ; Fri, 10 Aug 2018 07:48:22 +0000 (UTC) Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.mailbox.org (Postfix) with ESMTPS id 4B25A483EE; Fri, 10 Aug 2018 09:48:22 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by hefe.heinlein-support.de (hefe.heinlein-support.de [91.198.250.172]) (amavisd-new, port 10030) with ESMTP id bUCpV8EGqo_g; Fri, 10 Aug 2018 09:48:20 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 10 Aug 2018 09:48:18 +0200 Message-Id: <20180810074819.24962-4-sr@denx.de> In-Reply-To: <20180810074819.24962-1-sr@denx.de> References: <20180810074819.24962-1-sr@denx.de> Subject: [U-Boot] [PATCH 4/5 v2] mips: Add Gardena Smart-Gateway board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage. This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- v2: - No change .../mips/dts/gardena-smart-gateway-mt7688.dts | 54 +++++++++++++++ arch/mips/mach-mt7620/Kconfig | 9 +++ board/gardena/smart-gateway-mt7688/Kconfig | 12 ++++ .../gardena/smart-gateway-mt7688/MAINTAINERS | 8 +++ board/gardena/smart-gateway-mt7688/Makefile | 3 + board/gardena/smart-gateway-mt7688/board.c | 18 +++++ ...gardena-smart-gateway-mt7688-ram_defconfig | 68 +++++++++++++++++++ .../gardena-smart-gateway-mt7688_defconfig | 67 ++++++++++++++++++ .../configs/gardena-smart-gateway-mt7688.h | 56 +++++++++++++++ 9 files changed, 295 insertions(+) create mode 100644 arch/mips/dts/gardena-smart-gateway-mt7688.dts create mode 100644 board/gardena/smart-gateway-mt7688/Kconfig create mode 100644 board/gardena/smart-gateway-mt7688/MAINTAINERS create mode 100644 board/gardena/smart-gateway-mt7688/Makefile create mode 100644 board/gardena/smart-gateway-mt7688/board.c create mode 100644 configs/gardena-smart-gateway-mt7688-ram_defconfig create mode 100644 configs/gardena-smart-gateway-mt7688_defconfig create mode 100644 include/configs/gardena-smart-gateway-mt7688.h diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts new file mode 100644 index 0000000000..6b2600a446 --- /dev/null +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc"; + model = "Gardena smart-Gateway-MT7688"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + stdout-path = &uart0; + }; +}; + +&uart0 { + status = "okay"; + clock-frequency = <40000000>; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; + + spi-nand@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig index ef1211d172..13a7bd2cc0 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mt7620/Kconfig @@ -21,6 +21,14 @@ endchoice choice prompt "Board select" +config BOARD_GARDENA_SMART_GATEWAY_MT7688 + bool "Gardena Smart Gateway" + depends on SOC_MT7620 + select SUPPORTS_BOOT_RAM + help + Gardena Smart Gateway boards have a MT7688 SoC with 128 MiB of RAM + and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. + config BOARD_LINKIT_SMART_7688 bool "LinkIt Smart 7688" depends on SOC_MT7620 @@ -121,6 +129,7 @@ endchoice config SUPPORTS_BOOT_RAM bool +source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" endmenu diff --git a/board/gardena/smart-gateway-mt7688/Kconfig b/board/gardena/smart-gateway-mt7688/Kconfig new file mode 100644 index 0000000000..3653f8aadb --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/Kconfig @@ -0,0 +1,12 @@ +if BOARD_GARDENA_SMART_GATEWAY_MT7688 + +config SYS_BOARD + default "smart-gateway-mt7688" + +config SYS_VENDOR + default "gardena" + +config SYS_CONFIG_NAME + default "gardena-smart-gateway-mt7688" + +endif diff --git a/board/gardena/smart-gateway-mt7688/MAINTAINERS b/board/gardena/smart-gateway-mt7688/MAINTAINERS new file mode 100644 index 0000000000..bbb491c1ce --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/MAINTAINERS @@ -0,0 +1,8 @@ +GARDENA_SMART_GATEWAY_MT7688 BOARD +M: Stefan Roese +S: Maintained +F: board/gardena/smart-gateway-mt7688 +F: include/configs/gardena-smart-gateway-mt7688.h +F: configs/gardena-smart-gateway-mt7688_defconfig +F: configs/gardena-smart-gateway-mt7688-ram_defconfig +F: arch/mips/dts/gardena-smart-gateway-mt7688.dts diff --git a/board/gardena/smart-gateway-mt7688/Makefile b/board/gardena/smart-gateway-mt7688/Makefile new file mode 100644 index 0000000000..70cd7a8e56 --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c new file mode 100644 index 0000000000..a62dc654f2 --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include + +void board_debug_uart_init(void) +{ + /* Nothing to be done here for this board (no UART setup etc) */ +} + +int board_early_init_f(void) +{ + /* Nothing to be done here for this board (no UART setup etc) */ + return 0; +} diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig new file mode 100644 index 0000000000..3220db6677 --- /dev/null +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -0,0 +1,68 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x10000c00 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_ARCH_MT7620=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" +CONFIG_DEBUG_UART=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)" +CONFIG_CMD_UBI=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_FIXED=y +CONFIG_MT76XX_ETH=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_MT76XX_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig new file mode 100644 index 0000000000..8e9e6e895e --- /dev/null +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -0,0 +1,67 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xbc000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x10000c00 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_ARCH_MT7620=y +CONFIG_BOOT_ROM=y +CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y +CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" +CONFIG_DEBUG_UART=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)" +CONFIG_CMD_UBI=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_MT76XX_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h new file mode 100644 index 0000000000..5ec9c6a041 --- /dev/null +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H +#define __CONFIG_GARDENA_SMART_GATEWAY_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#ifdef CONFIG_BOOT_RAM +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ +#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ From patchwork Fri Aug 10 07:48:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 956025 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41my1v4nLFz9s8f for ; Fri, 10 Aug 2018 17:49:23 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 4D840C21DA2; Fri, 10 Aug 2018 07:48:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E9D0FC21C93; Fri, 10 Aug 2018 07:48:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0BF06C21C27; Fri, 10 Aug 2018 07:48:22 +0000 (UTC) Received: from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215]) by lists.denx.de (Postfix) with ESMTPS id C8B58C21C4A for ; Fri, 10 Aug 2018 07:48:21 +0000 (UTC) Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id B1B114135D; Fri, 10 Aug 2018 09:48:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id R878YTbjQziz; Fri, 10 Aug 2018 09:48:21 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 10 Aug 2018 09:48:19 +0200 Message-Id: <20180810074819.24962-5-sr@denx.de> In-Reply-To: <20180810074819.24962-1-sr@denx.de> References: <20180810074819.24962-1-sr@denx.de> Subject: [U-Boot] [PATCH 5/5 v2] mips: mt76xx: Add sysreset support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds the necessary sysreset DT node and enables the required drivers via Kconfig. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- v2: - New patch arch/mips/Kconfig | 1 + arch/mips/dts/mt7628a.dtsi | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b7c5fa3114..4234b924c4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -100,6 +100,7 @@ config ARCH_MT7620 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN + select SYSRESET config MACH_PIC32 bool "Support Microchip PIC32" diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index d00f528e1f..d525f019fe 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -41,6 +41,13 @@ reg = <0x0 0x100>; }; + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysc>; + offset = <0x34>; + mask = <0x1>; + }; + intc: interrupt-controller@200 { compatible = "ralink,rt2880-intc"; reg = <0x200 0x100>;