From patchwork Wed Aug 8 15:15:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 955091 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41lw4s2ZGbz9s0n for ; Thu, 9 Aug 2018 01:18:21 +1000 (AEST) Received: from localhost ([::1]:44282 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnQE6-0006tx-VF for incoming@patchwork.ozlabs.org; Wed, 08 Aug 2018 11:18:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnQBx-0005pG-TB for qemu-devel@nongnu.org; Wed, 08 Aug 2018 11:16:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnQBu-0002gc-4k for qemu-devel@nongnu.org; Wed, 08 Aug 2018 11:16:05 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:56706 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnQBt-0002g6-Vy for qemu-devel@nongnu.org; Wed, 08 Aug 2018 11:16:02 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E4AA5402315B for ; Wed, 8 Aug 2018 15:16:00 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5C242104949D; Wed, 8 Aug 2018 15:16:00 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 17:15:46 +0200 Message-Id: <1533741349-199141-2-git-send-email-imammedo@redhat.com> In-Reply-To: <1533741349-199141-1-git-send-email-imammedo@redhat.com> References: <1533741349-199141-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Wed, 08 Aug 2018 15:16:00 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Wed, 08 Aug 2018 15:16:00 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'imammedo@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC PATCH 1/4] acpi: aml: add aml_register() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Michael S. Tsirkin" Based on a patch by Igor Mammedov. Signed-off-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- include/hw/acpi/aml-build.h | 5 +++++ hw/acpi/aml-build.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 6c36903..10c7946 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -346,6 +346,11 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed, uint64_t len); Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTransferSize sz, uint8_t channel); +Aml *aml_register(AmlAddressSpace as, + uint8_t bit_width, + uint8_t bit_offset, + uint64_t address, + uint8_t access_size); Aml *aml_sleep(uint64_t msec); /* Block AML object primitives */ diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 1e43cd7..def62b3 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -874,6 +874,27 @@ Aml *aml_irq_no_flags(uint8_t irq) return var; } +/* + * ACPI: 2.0: 16.2.4.16 ASL Macro for Generic Register Descriptor + * + * access_size comes from: + * ACPI 3.0: 17.5.98 Register (Generic Register Resource Descriptor Macro) + */ +Aml *aml_register(AmlAddressSpace as, + uint8_t bit_width, + uint8_t bit_offset, + uint64_t address, + uint8_t access_size) +{ + Aml *var = aml_alloc(); + + build_append_byte(var->buf, 0x82); /* Generic Register Descriptor */ + build_append_byte(var->buf, 0x0C); /* Length, bits[7:0] */ + build_append_byte(var->buf, 0x0); /* Length, bits[15:8] */ + build_append_gas(var->buf, as, bit_width, bit_offset, access_size, address); + return var; +} + /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLNot */ Aml *aml_lnot(Aml *arg) { From patchwork Wed Aug 8 15:15:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 955090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41lw3F028Hz9s1c for ; Thu, 9 Aug 2018 01:16:56 +1000 (AEST) Received: from localhost ([::1]:44275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnQCk-0005s2-K6 for incoming@patchwork.ozlabs.org; Wed, 08 Aug 2018 11:16:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnQBx-0005pK-Tt for qemu-devel@nongnu.org; Wed, 08 Aug 2018 11:16:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnQBv-0002h3-2v for qemu-devel@nongnu.org; Wed, 08 Aug 2018 11:16:05 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:50250 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnQBu-0002gm-S9 for qemu-devel@nongnu.org; Wed, 08 Aug 2018 11:16:02 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7932187916 for ; Wed, 8 Aug 2018 15:16:02 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id E6CB010F1BE6; Wed, 8 Aug 2018 15:16:01 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 17:15:48 +0200 Message-Id: <1533741349-199141-4-git-send-email-imammedo@redhat.com> In-Reply-To: <1533741349-199141-1-git-send-email-imammedo@redhat.com> References: <1533741349-199141-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Wed, 08 Aug 2018 15:16:02 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Wed, 08 Aug 2018 15:16:02 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'imammedo@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC PATCH 3/4] pc: acpi: add _CST support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Reuse CPU hotplug IO registers for passing a CST entry containing package for shalowest C1 using mwait and read it out in guest with new CCST AML method. The CState support is optional and could be turned on with '-global PIIX4_PM.cstate=on' CLI option. Signed-off-by: Igor Mammedov --- for demo purposes it's wired only to piix4 TODO: q35 wiring 'tested' with rhel7 and XPsp3 - WS2016 (i.e. it boots and all windows versions happy about AML qemu produces) --- include/hw/acpi/cpu.h | 9 +++ docs/specs/acpi_cpu_hotplug.txt | 10 ++- hw/acpi/cpu.c | 131 ++++++++++++++++++++++++++++++++++++++++ hw/acpi/piix4.c | 2 + hw/i386/acpi-build.c | 5 +- tests/bios-tables-test.c | 1 + 6 files changed, 156 insertions(+), 2 deletions(-) diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 89ce172..eb79cbf 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -17,6 +17,12 @@ #include "hw/acpi/aml-build.h" #include "hw/hotplug.h" +typedef struct AcpiCState { + uint32_t current_cst_field; + uint32_t latency; + uint32_t power; +} AcpiCState; + typedef struct AcpiCpuStatus { struct CPUState *cpu; uint64_t arch_id; @@ -24,6 +30,7 @@ typedef struct AcpiCpuStatus { bool is_removing; uint32_t ost_event; uint32_t ost_status; + AcpiCState cst; } AcpiCpuStatus; typedef struct CPUHotplugState { @@ -32,6 +39,7 @@ typedef struct CPUHotplugState { uint8_t command; uint32_t dev_count; AcpiCpuStatus *devs; + bool enable_cstate; } CPUHotplugState; void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, @@ -50,6 +58,7 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, typedef struct CPUHotplugFeatures { bool apci_1_compatible; bool has_legacy_cphp; + bool cstate_enabled; } CPUHotplugFeatures; void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.txt index ee219c8..adfb026 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -47,6 +47,12 @@ read access: in case of error or unsupported command reads is 0xFFFFFFFF current 'Command field' value: 0: returns PXM value corresponding to device + 3: sequential reads return a sequence of DWORDs + { + AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, + RegisterAddress Lo, RegisterAddress Hi, AccessSize, + C State type, Latency, Power, + } write access: offset: @@ -75,7 +81,9 @@ write access: 1: following writes to 'Command data' register set OST event register in QEMU 2: following writes to 'Command data' register set OST status - register in QEMU + 3: following reads from 'Command data' register return Cx + state (command execution resets unread field counter to the 1st + field). other values: reserved [0x6-0x7] reserved [0x8] Command data: (DWORD access) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 5ae595e..7ef04f9 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -16,6 +16,7 @@ enum { CPHP_GET_NEXT_CPU_WITH_EVENT_CMD = 0, CPHP_OST_EVENT_CMD = 1, CPHP_OST_STATUS_CMD = 2, + CPHP_READ_CST_CMD = 3, CPHP_CMD_MAX }; @@ -73,6 +74,41 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr, unsigned size) case CPHP_GET_NEXT_CPU_WITH_EVENT_CMD: val = cpu_st->selector; break; + case CPHP_READ_CST_CMD: + switch (cdev->cst.current_cst_field) { + case 0: + val = cpu_to_le32(AML_AS_FFH); /* AddressSpaceKeyword */ + break; + case 1: /* RegisterBitWidth */ + val = cpu_to_le32(1); /* Vendor: Intel */ + break; + case 2: /* RegisterBitOffset */ + val = cpu_to_le32(2); /* Class: Native C State Instruction */ + break; + case 3: /* RegisterAddress Lo */ + val = cpu_to_le64(0); /* Arg0: mwait EAX hint */ + break; + case 4: /* RegisterAddress Hi */ + val = cpu_to_le32(0); /* Reserved */ + break; + case 5: /* AccessSize */ + val = cpu_to_le32(0); /* Arg1 */ + break; + case 6: + val = cpu_to_le32(1); /* The C State type C1*/ + break; + case 7: + val = cpu_to_le32(cdev->cst.latency); + break; + case 8: + val = cpu_to_le32(cdev->cst.power); + break; + default: + val = 0xFFFFFFFF; + break; + } + cdev->cst.current_cst_field++; + break; default: break; } @@ -145,6 +181,9 @@ static void cpu_hotplug_wr(void *opaque, hwaddr addr, uint64_t data, } iter = iter + 1 < cpu_st->dev_count ? iter + 1 : 0; } while (iter != cpu_st->selector); + } else if (cpu_st->command == CPHP_READ_CST_CMD) { + cdev = &cpu_st->devs[cpu_st->selector]; + cdev->cst.current_cst_field = 0; } } break; @@ -265,6 +304,36 @@ void acpi_cpu_unplug_cb(CPUHotplugState *cpu_st, cdev->cpu = NULL; } +static const VMStateDescription vmstate_cstate_sts = { + .name = "CState", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(cst.current_cst_field, AcpiCpuStatus), + VMSTATE_UINT32(cst.latency, AcpiCpuStatus), + VMSTATE_UINT32(cst.power, AcpiCpuStatus), + VMSTATE_END_OF_LIST() + } +}; + +static bool vmstate_test_use_cst(void *opaque) +{ + CPUHotplugState *s = opaque; + return s->enable_cstate; +} + +static const VMStateDescription vmstate_cstates = { + .name = "CPU hotplug state/CStates", + .version_id = 1, + .minimum_version_id = 1, + .needed = vmstate_test_use_cst, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(devs, CPUHotplugState, dev_count, + vmstate_cstate_sts, AcpiCpuStatus), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_cpuhp_sts = { .name = "CPU hotplug device state", .version_id = 1, @@ -290,6 +359,10 @@ const VMStateDescription vmstate_cpu_hotplug = { VMSTATE_STRUCT_VARRAY_POINTER_UINT32(devs, CPUHotplugState, dev_count, vmstate_cpuhp_sts, AcpiCpuStatus), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &vmstate_cstates, + NULL } }; @@ -301,6 +374,7 @@ const VMStateDescription vmstate_cpu_hotplug = { #define CPU_NOTIFY_METHOD "CTFY" #define CPU_EJECT_METHOD "CEJ0" #define CPU_OST_METHOD "COST" +#define CPU_CST_METHOD "CCST" #define CPU_ENABLED "CPEN" #define CPU_SELECTOR "CSEL" @@ -501,6 +575,57 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, } aml_append(cpus_dev, method); + if (opts.cstate_enabled) { + Aml *crs; + Aml *pkg = aml_local(0); + Aml *cst = aml_local(1); + Aml *cst_cmd = aml_int(CPHP_READ_CST_CMD); + Aml *uid = aml_arg(0); + Aml *nm = aml_name("CCRS"); + + method = aml_method(CPU_CST_METHOD, 1, AML_SERIALIZED); + /* Package to hold 1 CST entry */ + aml_append(method, aml_store(aml_package(2), pkg)); + aml_append(method, aml_store(aml_package(4), cst)); /* CST entry */ + + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + aml_append(method, aml_store(uid, cpu_selector)); + aml_append(method, aml_store(cst_cmd, cpu_cmd)); + + /* create register template to fill in */ + crs = aml_resource_template(); + aml_append(crs, aml_register(AML_AS_FFH, 0, 0, 0, 0)); + aml_append(method, aml_name_decl("CCRS", crs)); + + /* fill in actual register values */ + aml_append(method, aml_create_byte_field(nm, aml_int(3), "_ASI")); + aml_append(method, aml_store(cpu_data, aml_name("_ASI"))); + aml_append(method, aml_create_byte_field(nm, aml_int(4), "_RBW")); + aml_append(method, aml_store(cpu_data, aml_name("_RBW"))); + aml_append(method, aml_create_byte_field(nm, aml_int(5), "_RBO")); + aml_append(method, aml_store(cpu_data, aml_name("_RBO"))); + aml_append(method, aml_create_dword_field(nm, aml_int(7), "LADR")); + aml_append(method, aml_store(cpu_data, aml_name("LADR"))); + aml_append(method, aml_create_dword_field(nm, aml_int(11), "HADR")); + aml_append(method, aml_store(cpu_data, aml_name("HADR"))); + aml_append(method, aml_create_byte_field(nm, aml_int(6), "_ASZ")); + aml_append(method, aml_store(cpu_data, aml_name("_ASZ"))); + + /* pack CST entry */ + aml_append(method, aml_store(crs, aml_index(cst, zero))); + aml_append(method, aml_store(cpu_data, aml_index(cst, one))); + aml_append(method, aml_store(cpu_data, aml_index(cst, aml_int(2)))); + aml_append(method, aml_store(cpu_data, aml_index(cst, aml_int(3)))); + aml_append(method, aml_release(ctrl_lock)); + + /* prepare _CST descriptor with 1 CST entry */ + aml_append(method, aml_store(one, aml_index(pkg, zero))); + aml_append(method, aml_store(cst, aml_index(pkg, one))); + + aml_append(method, aml_return(pkg)); + aml_append(cpus_dev, method); + } + /* build Processor object for each processor */ for (i = 0; i < arch_ids->len; i++) { Aml *dev; @@ -520,6 +645,12 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(method, aml_return(aml_call1(CPU_STS_METHOD, uid))); aml_append(dev, method); + if (opts.cstate_enabled) { + method = aml_method("_CST", 0, AML_SERIALIZED); + aml_append(method, aml_return(aml_call1(CPU_CST_METHOD, uid))); + aml_append(dev, method); + } + /* build _MAT object */ assert(adevc && adevc->madt_cpu); adevc->madt_cpu(adev, i, arch_ids, madt_buf); diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 6404af5..6d3df17 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -677,6 +677,8 @@ static Property piix4_pm_properties[] = { use_acpi_pci_hotplug, true), DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, acpi_memory_hotplug.is_enabled, true), + DEFINE_PROP_BOOL("cstate", PIIX4PMState, + cpuhp_state.enable_cstate, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index e1ee8ae..dd695bd 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -100,6 +100,7 @@ typedef struct AcpiPmInfo { uint16_t cpu_hp_io_base; uint16_t pcihp_io_base; uint16_t pcihp_io_len; + bool cstate_enabled; } AcpiPmInfo; typedef struct AcpiMiscInfo { @@ -218,6 +219,7 @@ static void acpi_get_pm_info(AcpiPmInfo *pm) pm->pcihp_bridge_en = object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", NULL); + pm->cstate_enabled = object_property_get_bool(obj, "cstate", NULL); } static void acpi_get_misc_info(AcpiMiscInfo *info) @@ -1840,7 +1842,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); } else { CPUHotplugFeatures opts = { - .apci_1_compatible = true, .has_legacy_cphp = true + .apci_1_compatible = true, .has_legacy_cphp = true, + .cstate_enabled = pm->cstate_enabled }; build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c index 4e24930..3c1687e 100644 --- a/tests/bios-tables-test.c +++ b/tests/bios-tables-test.c @@ -716,6 +716,7 @@ static void test_acpi_piix4_tcg_cphp(void) data.machine = MACHINE_PC; data.variant = ".cphp"; test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6" + " -global PIIX4_PM.cstate=on" " -numa node -numa node" " -numa dist,src=0,dst=1,val=21", &data); From patchwork Wed Aug 8 15:15:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 955093 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41lw7D3Jjqz9s0n for ; Thu, 9 Aug 2018 01:20:24 +1000 (AEST) Received: from localhost ([::1]:44291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnQG6-0008Uj-3S for incoming@patchwork.ozlabs.org; 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Wed, 8 Aug 2018 15:16:02 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 17:15:49 +0200 Message-Id: <1533741349-199141-5-git-send-email-imammedo@redhat.com> In-Reply-To: <1533741349-199141-1-git-send-email-imammedo@redhat.com> References: <1533741349-199141-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Wed, 08 Aug 2018 15:16:03 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Wed, 08 Aug 2018 15:16:03 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'imammedo@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC PATCH 4/4] acpi: add support for CST update notification X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Reuse cpu hotplug inotification interface to notify guest about CST change. Signed-off-by: Igor Mammedov --- include/hw/acpi/cpu.h | 1 + docs/specs/acpi_cpu_hotplug.txt | 11 ++++++++--- hw/acpi/cpu.c | 27 ++++++++++++++++++++++++++- 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index eb79cbf..51d7fc6 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -28,6 +28,7 @@ typedef struct AcpiCpuStatus { uint64_t arch_id; bool is_inserting; bool is_removing; + bool is_cst_update; uint32_t ost_event; uint32_t ost_status; AcpiCState cst; diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.txt index adfb026..41ba236 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -41,7 +41,10 @@ read access: It's valid only when bit 0 is set. 2: Device remove event, used to distinguish device for which no device eject request to OSPM was issued. - 3-7: reserved and should be ignored by OSPM + 3: reserved and should be ignored by OSPM + 4: Device CST event, used to distinguish device for which + device eject request to OSPM was issued + 5-7: reserved and should be ignored by OSPM [0x5-0x7] reserved [0x8] Command data: (DWORD access) in case of error or unsupported command reads is 0xFFFFFFFF @@ -70,14 +73,16 @@ write access: selected CPU device 3: if set to 1 initiates device eject, set by OSPM when it triggers CPU device removal and calls _EJ0 method + 4: if set to 1 clears CST update event, set by OSPM + after it has emitted CST update notification 4-7: reserved, OSPM must clear them before writing to register [0x5] Command field: (1 byte access) value: - 0: selects a CPU device with inserting/removing events and + 0: selects a CPU device with inserting/removing/cst events and following reads from 'Command data' register return selected CPU (CPU selector value). If no CPU with events found, the current CPU selector doesn't change and - corresponding insert/remove event flags are not set. + corresponding insert/remove/cst event flags are not set. 1: following writes to 'Command data' register set OST event register in QEMU 2: following writes to 'Command data' register set OST status diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 7ef04f9..c4a9fac 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -67,6 +67,7 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr, unsigned size) val |= cdev->cpu ? 1 : 0; val |= cdev->is_inserting ? 2 : 0; val |= cdev->is_removing ? 4 : 0; + val |= cdev->is_cst_update ? 16 : 0; trace_cpuhp_acpi_read_flags(cpu_st->selector, val); break; case ACPI_CPU_CMD_DATA_OFFSET_RW: @@ -162,6 +163,8 @@ static void cpu_hotplug_wr(void *opaque, hwaddr addr, uint64_t data, dev = DEVICE(cdev->cpu); hotplug_ctrl = qdev_get_hotplug_handler(dev); hotplug_handler_unplug(hotplug_ctrl, dev, NULL); + } else if (data & 16) { /* clear CST update event */ + cdev->is_cst_update = false; } break; case ACPI_CPU_CMD_OFFSET_WR: @@ -312,6 +315,7 @@ static const VMStateDescription vmstate_cstate_sts = { VMSTATE_UINT32(cst.current_cst_field, AcpiCpuStatus), VMSTATE_UINT32(cst.latency, AcpiCpuStatus), VMSTATE_UINT32(cst.power, AcpiCpuStatus), + VMSTATE_BOOL(is_cst_update, AcpiCpuStatus), VMSTATE_END_OF_LIST() } }; @@ -383,6 +387,7 @@ const VMStateDescription vmstate_cpu_hotplug = { #define CPU_INSERT_EVENT "CINS" #define CPU_REMOVE_EVENT "CRMV" #define CPU_EJECT_EVENT "CEJ0" +#define CPU_CST_EVENT "CSTU" void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, hwaddr io_base, @@ -435,7 +440,13 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(field, aml_named_field(CPU_REMOVE_EVENT, 1)); /* initiates device eject, write only */ aml_append(field, aml_named_field(CPU_EJECT_EVENT, 1)); - aml_append(field, aml_reserved_field(4)); + if (opts.cstate_enabled) { + /* (read) 1 if has a CST event. (write) 1 to clear event */ + aml_append(field, aml_named_field(CPU_CST_EVENT, 1)); + aml_append(field, aml_reserved_field(3)); + } else { + aml_append(field, aml_reserved_field(4)); + } aml_append(field, aml_named_field(CPU_COMMAND, 8)); aml_append(cpu_ctrl_dev, field); @@ -470,6 +481,7 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, Aml *ins_evt = aml_name("%s.%s", cphp_res_path, CPU_INSERT_EVENT); Aml *rm_evt = aml_name("%s.%s", cphp_res_path, CPU_REMOVE_EVENT); Aml *ej_evt = aml_name("%s.%s", cphp_res_path, CPU_EJECT_EVENT); + Aml *cst_evt = aml_name("%s.%s", cphp_res_path, CPU_CST_EVENT); aml_append(cpus_dev, aml_name_decl("_HID", aml_string("ACPI0010"))); aml_append(cpus_dev, aml_name_decl("_CID", aml_eisaid("PNP0A05"))); @@ -524,6 +536,7 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, Aml *has_event = aml_local(0); Aml *dev_chk = aml_int(1); Aml *eject_req = aml_int(3); + Aml *cst_upd = aml_int(0x81); Aml *next_cpu_cmd = aml_int(CPHP_GET_NEXT_CPU_WITH_EVENT_CMD); aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); @@ -553,6 +566,18 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, } aml_append(else_ctx, ifctx); aml_append(while_ctx, else_ctx); + if (opts.cstate_enabled == true) { + else_ctx = aml_else(); + ifctx = aml_if(aml_equal(cst_evt, one)); + { + aml_append(ifctx, + aml_call2(CPU_NOTIFY_METHOD, cpu_data, cst_upd)); + aml_append(ifctx, aml_store(one, cst_evt)); + aml_append(ifctx, aml_store(one, has_event)); + } + aml_append(else_ctx, ifctx); + aml_append(while_ctx, else_ctx); + } } aml_append(method, while_ctx); aml_append(method, aml_release(ctrl_lock));