From patchwork Fri Aug 3 15:34:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 953284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-483115-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Z4PQKfbt"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41hrhG5p7cz9s0R for ; Sat, 4 Aug 2018 01:34:53 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=aSE1vlwQGzYZ5lYtYYRYgxmsoxbKGM82RE9L+wE+s5pbgPJcdq CRXcyQxY26KkSo/3InESLJbyb0T8qet2fak7w0mNUs7blQhAbXYUOrt+UuBJ7ICv WVwKkUATzZM8mZn4e9CmVR1vCBj8OdhsEOmUC3MA94dOHnn1CFVfk8fKc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=FYSJg7XfIxcBGtJBQUY4K1zsZ0E=; b=Z4PQKfbtRJKF4LqaJUxg 8eYfsf97wCEJ5zXCfORAm7K2a1NYIuel2cAb8+n3IkpDadAjwxCpumN4oM6q3g1t RpEPUgs9RXe6e2s+qXCb4AHXLhW9bBmYN2SdjGtWuW9ml5MfF6WotWpmL3Dang9+ NHspl0u06lWDqGpkXKl2Ln4= Received: (qmail 31571 invoked by alias); 3 Aug 2018 15:34:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31559 invoked by uid 89); 3 Aug 2018 15:34:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.2 spammy=aarch64-simd.md, aarch64simdmd, UD:aarch64-simd.md, UNSPEC X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Aug 2018 15:34:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0855F80D; Fri, 3 Aug 2018 08:34:40 -0700 (PDT) Received: from localhost (unknown [10.32.98.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 155EF3F2EA; Fri, 3 Aug 2018 08:34:38 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@arm.com Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [AArch64] Fix -mlow-precision-div (PR 86838) Date: Fri, 03 Aug 2018 16:34:37 +0100 Message-ID: <87zhy379bm.fsf@arm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 The "@" handling broke -mlow-precision-div, because the scalar forms of the instruction were provided by a pattern that also provided FRECPX (and so were parameterised on an unspec code as well as a mode), while the SIMD versions had a dedicated FRECPE pattern. This patch moves the scalar FRECPE handling to the SIMD pattern too (as for FRECPS) and uses a separate pattern for FRECPX. The convention in aarch64-simd-builtins.def seemed to be to add comments only if the mapping wasn't obvious (i.e. not just sticking "aarch64_" on the beginning and "" on the end), so the patch deletes the reference to the combined pattern instead of rewording it. There didn't seem to be any coverage of -mlow-precision-div in the testsuite, so the patch adds some tests for it. Tested on aarch64-linux-gnu. OK to install? Richard 2018-08-03 Richard Sandiford gcc/ PR target/86838 * config/aarch64/iterators.md (FRECP, frecp_suffix): Delete. * config/aarch64/aarch64-simd.md (aarch64_frecp): Fold FRECPE into... (@aarch64_frecpe): ...here and the move FRECPX to... (aarch64_frecpx): ...this new pattern. * config/aarch64/aarch64-simd-builtins.def: Remove comment about aarch64_frecp. gcc/testsuite/ PR target/86838 * gcc.target/aarch64/frecpe_1.c: New test. * gcc.target/aarch64/frecpe_2.c: Likewise. Index: gcc/config/aarch64/iterators.md =================================================================== --- gcc/config/aarch64/iterators.md 2018-07-31 19:10:15.744291661 +0100 +++ gcc/config/aarch64/iterators.md 2018-08-03 16:32:07.531492221 +0100 @@ -1537,8 +1537,6 @@ (define_int_iterator FCVT [UNSPEC_FRINTZ (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) -(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) - (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW UNSPEC_CRC32CX]) @@ -1788,8 +1786,6 @@ (define_int_attr hi_lanes_optab [(UNSPEC (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) -(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) - (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2018-08-02 11:59:06.851355923 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2018-08-03 16:32:07.531492221 +0100 @@ -5879,21 +5879,22 @@ (define_insn "aarch64_simd_ld1_x2" (define_insn "@aarch64_frecpe" - [(set (match_operand:VHSDF 0 "register_operand" "=w") - (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")] + [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w") + (unspec:VHSDF_HSDF + [(match_operand:VHSDF_HSDF 1 "register_operand" "w")] UNSPEC_FRECPE))] "TARGET_SIMD" - "frecpe\\t%0., %1." + "frecpe\t%0, %1" [(set_attr "type" "neon_fp_recpe_")] ) -(define_insn "aarch64_frecp" +(define_insn "aarch64_frecpx" [(set (match_operand:GPF_F16 0 "register_operand" "=w") (unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")] - FRECP))] + UNSPEC_FRECPX))] "TARGET_SIMD" - "frecp\\t%0, %1" - [(set_attr "type" "neon_fp_recp_")] + "frecpx\t%0, %1" + [(set_attr "type" "neon_fp_recpx_")] ) (define_insn "@aarch64_frecps" Index: gcc/config/aarch64/aarch64-simd-builtins.def =================================================================== --- gcc/config/aarch64/aarch64-simd-builtins.def 2018-06-14 12:27:40.672026808 +0100 +++ gcc/config/aarch64/aarch64-simd-builtins.def 2018-08-03 16:32:07.531492221 +0100 @@ -413,8 +413,6 @@ BUILTIN_VALL (BINOP, trn1, 0) BUILTIN_VALL (BINOP, trn2, 0) - /* Implemented by - aarch64_frecp. */ BUILTIN_GPF_F16 (UNOP, frecpe, 0) BUILTIN_GPF_F16 (UNOP, frecpx, 0) Index: gcc/testsuite/gcc.target/aarch64/frecpe_1.c =================================================================== --- /dev/null 2018-07-26 10:26:13.137955424 +0100 +++ gcc/testsuite/gcc.target/aarch64/frecpe_1.c 2018-08-03 16:32:07.531492221 +0100 @@ -0,0 +1,18 @@ +/* { dg-options "-Ofast -mlow-precision-div" } */ +/* { dg-do compile } */ + +float +f1 (float x) +{ + return 1 / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\ts0, \1, \2\n} } } */ + +double +f2 (double x) +{ + return 1 / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\td0, \1, \2\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/frecpe_2.c =================================================================== --- /dev/null 2018-07-26 10:26:13.137955424 +0100 +++ gcc/testsuite/gcc.target/aarch64/frecpe_2.c 2018-08-03 16:32:07.531492221 +0100 @@ -0,0 +1,18 @@ +/* { dg-options "-Ofast -mlow-precision-div" } */ +/* { dg-do compile } */ + +float +f1 (float x, float y) +{ + return y / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\t\1, \1, s1\n\tfmul\ts0, \1, \2\n} } } */ + +double +f2 (double x, double y) +{ + return y / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\t\1, \1, d1\n\tfmul\td0, \1, \2\n} } } */