From patchwork Wed Jul 25 22:28:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 949393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="d5waiVkt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41bVJZ4X0Tz9s1R for ; Thu, 26 Jul 2018 08:29:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731586AbeGYXmu (ORCPT ); Wed, 25 Jul 2018 19:42:50 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:40097 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731575AbeGYXmu (ORCPT ); Wed, 25 Jul 2018 19:42:50 -0400 Received: by mail-pg1-f194.google.com with SMTP id x5-v6so6201963pgp.7 for ; Wed, 25 Jul 2018 15:29:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ink+Zn8JKKzqrmjhPVKUxo0wTebG1Ak/9NW4SCv+NEs=; b=d5waiVktb7Skwo+wZNY5Gu3m9T6CTmlCMM1asro2WMbqNmst/sXeI5axBsr3BRpBFM 7k4V4/j/7gIrAqRKTsFsnZaviZ/v2SY8CBSIOanvpeUNOka7HopjreorUONwHhx0BSRa V6nNctLVYwWXCi0h8ksFE1aF386LzWzz0fJro= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ink+Zn8JKKzqrmjhPVKUxo0wTebG1Ak/9NW4SCv+NEs=; b=oiTl0hyN8ZFp5Q/+nTIddvI8F4uz4BqvgnxeNiP5pAtiVVks+XT8LsHJPjVZ2mjor9 J/wOK2DBa+okLeTftcbScxiixYmjvYD5SeBh6mdbgU+kbrXb01y3buIw39fBXHs7Niv4 2ga544m5gFIYOlLxih4iprEJUg1TCu62XkD2KgWBfuCJzSdhQywHVTDUolTSFl2752KW IfTpI1hbvLeGiVxDWMYhB4mEDtrY6TKpriWrw73LpDV6LTrrWd45gezcL1NRKP26TDi5 G4FaUUmEy6HD51F4/VcUjdOhwiahk3eHYtbuxoatzH/cZPPOc9aNgmH+gbCkpmL+OpwB 255A== X-Gm-Message-State: AOUpUlFgGLJjWfg2AAIU3seYpzWmsjDjYhy1z7+DpvSCkc/CpMOukrHx IRofVYl8hHO1tWFQpJ+Zy6NhJw== X-Google-Smtp-Source: AAOMgpfrezkXI2QKska/+IpXiR8SnBknmM6lpJPDhofAwAKPOJUysXllMOIDO48GEoEOj33pIPZogw== X-Received: by 2002:a62:669b:: with SMTP id s27-v6mr21979355pfj.224.1532557744045; Wed, 25 Jul 2018 15:29:04 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id o21-v6sm23839234pfa.54.2018.07.25.15.29.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 15:29:03 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bjorn Andersson , Doug Anderson Subject: [PATCH v2 1/3] pinctrl: msm: Really mask level interrupts to prevent latching Date: Wed, 25 Jul 2018 15:28:58 -0700 Message-Id: <20180725222900.33231-2-swboyd@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog In-Reply-To: <20180725222900.33231-1-swboyd@chromium.org> References: <20180725222900.33231-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The interrupt controller hardware in this pin controller has two status enable bits. The first "normal" status enable bit enables or disables the summary interrupt line being raised when a gpio interrupt triggers and the "raw" status enable bit allows or prevents the hardware from latching an interrupt into the status register for a gpio interrupt. Currently we just toggle the "normal" status enable bit in the mask and unmask ops so that the summary irq interrupt going to the CPU's interrupt controller doesn't trigger for the masked gpio interrupt. For a level triggered interrupt, the flow would be as follows: the pin controller sees the interrupt, latches the status into the status register, raises the summary irq to the CPU, summary irq handler runs and calls handle_level_irq(), handle_level_irq() masks and acks the gpio interrupt, the interrupt handler runs, and finally unmask the interrupt. When the interrupt handler completes, we expect that the interrupt line level will go back to the deasserted state so the genirq code can unmask the interrupt without it triggering again. If we only mask the interrupt by clearing the "normal" status enable bit then we'll ack the interrupt but it will continue to show up as pending in the status register because the raw status bit is enabled, the hardware hasn't deasserted the line, and thus the asserted state latches into the status register again. When the hardware deasserts the interrupt the pin controller still thinks there is a pending unserviced level interrupt because it latched it earlier. This behavior causes software to see an extra interrupt for level type interrupts each time the interrupt is handled. Let's fix this by clearing the raw status enable bit for level type interrupts so that the hardware stops latching the status of the interrupt after we ack it. We don't do this for edge type interrupts because it seems that toggling the raw status enable bit for edge type interrupts causes spurious edge interrupts. Cc: Bjorn Andersson Cc: Doug Anderson Signed-off-by: Stephen Boyd --- Changes from v1: - Squashed raw_status_bit write into same write on unmask (Doug Andersson) drivers/pinctrl/qcom/pinctrl-msm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 2155a30c282b..3970dc599092 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -634,6 +634,19 @@ static void msm_gpio_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg); + /* + * Leaving the RAW_STATUS_EN bit enabled causes level interrupts that + * are still asserted to re-latch after we ack them. Clear the raw + * status enable bit too so the interrupt can't even latch into the + * hardware while it's masked, but only do this for level interrupts + * because edge interrupts have a problem with the raw status bit + * toggling and causing spurious interrupts. + */ + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) { + val &= ~BIT(g->intr_raw_status_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + } + val &= ~BIT(g->intr_enable_bit); writel(val, pctrl->regs + g->intr_cfg_reg); @@ -655,6 +668,7 @@ static void msm_gpio_irq_unmask(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_raw_status_bit); val |= BIT(g->intr_enable_bit); writel(val, pctrl->regs + g->intr_cfg_reg); From patchwork Wed Jul 25 22:28:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 949394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Hh8ZFtM/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41bVJh6V9cz9s1R for ; Thu, 26 Jul 2018 08:29:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731447AbeGYXnC (ORCPT ); Wed, 25 Jul 2018 19:43:02 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:44280 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731578AbeGYXmu (ORCPT ); Wed, 25 Jul 2018 19:42:50 -0400 Received: by mail-pf1-f194.google.com with SMTP id k21-v6so2142106pff.11 for ; Wed, 25 Jul 2018 15:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=St6GA7EQfesMvQkxgGbb3MU3M3YjzaV9AWMKmBCouNo=; b=Hh8ZFtM/GapFvbm5ucHLFHNKCW92R6+horDtCwxwjcdi7MhrY6qhdP4UIHzCxw0L53 0gSdt0oJNJ368s/PDcQ+byBuf/gjxGcQui8loS9TE53cZuSi4aELuW5tWyIKyPDJx8CA uAq1OgXxIZji+GT1G5EyQ00MbfWbtm4xmpRXU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=St6GA7EQfesMvQkxgGbb3MU3M3YjzaV9AWMKmBCouNo=; b=QqW8pOYIolMX5k2QC+M8Ty4zRR9of0w+ItA/X9PsBloIXu914aPQCHrGra8v2FkaSX VUk3CWLYPdNIb5mRcFWtWggPSUDQxbaG1lHx22nBj+1ppEKNfgT+qcca93eTXIvAIMHo +Sjh36V69/ZRd+YoMKcjYdMxfdS0lWG0rb6xljDpMICjn9zqHbEow5TPWOdRsN9GvfjV /dqW3NZtNJMFvDIjOT7OD8PlEhaQbSmNLpmdufgS6YdpvOYBrvA1GGbCsMI9ofMVZirc H5GR86eYXDhsLzzsSS2LbKmTgcs9kpEzuq/0RG9hIZEj8ZSAIRx+3yRa/kfah6pbIKbS QP6A== X-Gm-Message-State: AOUpUlEYmjyn8neM8N9YZqiZciqTOOnHZyVv/w54/zMdhu+6k/WmFkup +OsGPcD+mzbFqtNr4V3ApqizgewErqQ3xQ== X-Google-Smtp-Source: AAOMgpeeh17JHQh+xn4AGSpPCKxCACFpQlSRyUWcXhSQ3zvCwNyhf1fs+/tqXKiN/COPlHzgJiNUYw== X-Received: by 2002:a62:5047:: with SMTP id e68-v6mr24193364pfb.157.1532557744708; Wed, 25 Jul 2018 15:29:04 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id o21-v6sm23839234pfa.54.2018.07.25.15.29.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 15:29:04 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bjorn Andersson , Doug Anderson Subject: [PATCH v2 2/3] pinctrl: msm: Mux out gpio function with gpio_request() Date: Wed, 25 Jul 2018 15:28:59 -0700 Message-Id: <20180725222900.33231-3-swboyd@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog In-Reply-To: <20180725222900.33231-1-swboyd@chromium.org> References: <20180725222900.33231-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We rely on devices to use pinmuxing configurations in DT to select the GPIO function (function 0) if they're going to use the gpio in GPIO mode. Let's simplify things for driver authors by implementing gpio_request_enable() for this pinctrl driver to mux out the GPIO function when the gpio is use from gpiolib. Cc: Bjorn Andersson Cc: Doug Anderson Signed-off-by: Stephen Boyd --- Changes from v1: * None drivers/pinctrl/qcom/pinctrl-msm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 3970dc599092..1d7367149268 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -176,11 +176,27 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + /* No funcs? Probably ACPI so can't do anything here */ + if (!g->nfuncs) + return 0; + + /* For now assume function 0 is GPIO because it always is */ + return msm_pinmux_set_mux(pctldev, 0, offset); +} + static const struct pinmux_ops msm_pinmux_ops = { .request = msm_pinmux_request, .get_functions_count = msm_get_functions_count, .get_function_name = msm_get_function_name, .get_function_groups = msm_get_function_groups, + .gpio_request_enable = msm_pinmux_request_gpio, .set_mux = msm_pinmux_set_mux, }; From patchwork Wed Jul 25 22:29:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 949392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="VTr9miTT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41bVJS4QMBz9s4V for ; Thu, 26 Jul 2018 08:29:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731618AbeGYXmw (ORCPT ); Wed, 25 Jul 2018 19:42:52 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:44435 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731591AbeGYXmv (ORCPT ); Wed, 25 Jul 2018 19:42:51 -0400 Received: by mail-pg1-f195.google.com with SMTP id r1-v6so6193701pgp.11 for ; Wed, 25 Jul 2018 15:29:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GWZK7b9lm024T3/GSjJUtOLt5Sv+N+aSacDYyJvd2YQ=; b=VTr9miTTfbJ4sDN7muGudDUIwoiT5H1w/3UBMvlWD1K1g9tisuV60ZNlkQjOzEz0qa 7ozj5gaxq3dFtZ1560Fg6x3ztcJRYnNzm/374ch27YCAMhGkW4w7/ePpAmB6QhLsa7g3 VRjfZOk9mRcVEt2c5r1PxBP00XXyjcvcXPoLs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GWZK7b9lm024T3/GSjJUtOLt5Sv+N+aSacDYyJvd2YQ=; b=YjGIfgUFzY+EXNseiLutw2mQvvVbjSELMerj+pmGOsTVwNfFW5C9Wyt6AKEwdk+58h zEvE9J/BEUVXd2fDPTeh0EakRs1VRRu0TPBx3ODbiXGqE9vPlurk7csXoifv9Z01OJUS JooAI+2ltstvmPyUWg7YOQT04psFcL3OraaRZj09A2Es4UPSs1VREO/QS4VIaX8uUvNh sXlbdcs1NMYzAkEBb9KIozNbalFEUTfHuGCP6FEYVS9+rNKhBlC56f4lS3guY61Lk9lX 8BXoMqAPiIf89bkfz4O0qVjuHaABSiSvkGEZKzqInTDf/04s2hF4DJe8AApxL6U19Yfc kHXw== X-Gm-Message-State: AOUpUlFYB9fQMMYKnA2IICAd8thP4tVuFtPkoEWC2FpfTZNoh40J4tB5 ao+0yj2+spA77lPkv/uxTozcKQ== X-Google-Smtp-Source: AAOMgpdVI3/vwA1jwld8k23Nkq39S0/+Ft5EaeUHNQKq6G48WIWizq7P/ShbOYvWRgUQHhoLSJkayg== X-Received: by 2002:a62:9cd7:: with SMTP id u84-v6mr24051324pfk.90.1532557745571; Wed, 25 Jul 2018 15:29:05 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id o21-v6sm23839234pfa.54.2018.07.25.15.29.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 15:29:05 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bjorn Andersson , Doug Anderson Subject: [PATCH v2 3/3] pinctrl: msm: Configure interrupts as input and gpio mode Date: Wed, 25 Jul 2018 15:29:00 -0700 Message-Id: <20180725222900.33231-4-swboyd@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog In-Reply-To: <20180725222900.33231-1-swboyd@chromium.org> References: <20180725222900.33231-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org When requesting a gpio as an interrupt, we should make sure to mux the pin as the GPIO function and configure it to be an input so that various functions or output signals don't affect the interrupt state of the pin. So far, we've relied on pinmux configurations in DT to handle this, but let's explicitly configure this in the code so that DT implementers don't have to get this part right. Cc: Bjorn Andersson Cc: Doug Anderson Signed-off-by: Stephen Boyd --- Changes from v1: * None drivers/pinctrl/qcom/pinctrl-msm.c | 37 ++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 1d7367149268..f2744092a4bf 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -827,6 +827,41 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) return 0; } +static int msm_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + int ret; + + if (!try_module_get(gc->owner)) + return -ENODEV; + + ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); + if (ret) + goto out; + msm_gpio_direction_input(gc, d->hwirq); + + if (gpiochip_lock_as_irq(gc, d->hwirq)) { + dev_err(gc->parent, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + ret = -EINVAL; + goto out; + } + return 0; +out: + module_put(gc->owner); + return ret; +} + +static void msm_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_unlock_as_irq(gc, d->hwirq); + module_put(gc->owner); +} + static void msm_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); @@ -925,6 +960,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; + pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; + pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) {