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Received: from smtprelay.synopsys.com ([198.182.47.9]) by merlin.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dxv7e-0002i4-Nw for linux-snps-arc@lists.infradead.org; Fri, 29 Sep 2017 13:14:31 +0000 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id A8FEF24E1573; Fri, 29 Sep 2017 06:14:02 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 87DFF8AB; Fri, 29 Sep 2017 06:14:02 -0700 (PDT) Received: from localhost.internal.synopsys.com (unknown [10.121.8.106]) by mailhost.synopsys.com (Postfix) with ESMTP id 577677F2; Fri, 29 Sep 2017 06:14:00 -0700 (PDT) From: Eugeniy Paltsev To: linux-clk@vger.kernel.org Subject: [PATCH] CLK: ARC: Set initial pll output frequency specified in device tree Date: Fri, 29 Sep 2017 16:13:57 +0300 Message-Id: <20170929131357.26796-1-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [198.182.47.9 listed in list.dnswl.org] -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Rob Herring , linux-snps-arc@lists.infradead.org, Eugeniy Paltsev MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add option to set initial output frequency of plls via "clock-frequency" property in pll's device tree node. This frequency will be set while pll driver probed. The usage example is setting CPU clock frequency on boot See discussion: https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html Signed-off-by: Eugeniy Paltsev --- .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- 4 files changed, 74 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt index c56c755..5703059 100644 --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt @@ -13,6 +13,10 @@ Required properties: - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input_clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x00 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + clock-frequency = <1000000000>; }; diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt index 11fe487..5908f99 100644 --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input-clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input-clk>; + clock-frequency = <100000000>; }; diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 25d8c24..3f4345d 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { .set_rate = axs10x_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int axs10x_pll_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int axs10x_pll_clk_remove(struct platform_device *pdev) @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) goto err_unregister_clk; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unregister_clk: diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index bbf23717..74fd006 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { .set_rate = hsdk_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int hsdk_pll_clk_probe(struct platform_device *pdev) { int ret; @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int hsdk_pll_clk_remove(struct platform_device *pdev) @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) goto err_unmap_spec_regs; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unmap_spec_regs: