From patchwork Thu Jul 12 11:13:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 942765 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41R1JL6dptz9ryt for ; Thu, 12 Jul 2018 13:14:42 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8FCE5C21DDC; Thu, 12 Jul 2018 03:14:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6F0ECC21C6A; Thu, 12 Jul 2018 03:14:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 90CEBC21EAE; Thu, 12 Jul 2018 03:14:02 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lists.denx.de (Postfix) with ESMTPS id 68B25C21EC9 for ; Thu, 12 Jul 2018 03:13:58 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jul 2018 20:13:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,341,1526367600"; d="scan'208";a="55885364" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.193]) by orsmga007.jf.intel.com with SMTP; 11 Jul 2018 20:13:40 -0700 Received: by ubuntu (sSMTP sendmail emulation); Thu, 12 Jul 2018 19:13:39 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Thu, 12 Jul 2018 19:13:34 +0800 Message-Id: <1531394014-12620-2-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531394014-12620-1-git-send-email-ley.foon.tan@intel.com> References: <1531394014-12620-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See Subject: [U-Boot] [PATCH] arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index cb6530f..26d84be 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; void s_init(void) { +#ifndef CONFIG_ARM64 /* * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled. * This is optional on CycloneV / ArriaV. @@ -29,6 +30,7 @@ void s_init(void) { "isb\n" "dsb\n" ::"r"(0x0)); +#endif } /*