From patchwork Wed Jul 11 10:36:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Malcomson X-Patchwork-Id: 942408 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-481336-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="B5qPe1RS"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="RvzKEy7v"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Qb8x1xPpzB4MQ for ; Wed, 11 Jul 2018 20:36:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=gSzHDkcGPMqq5LAXpQhylgu6/rwg2XO6Gn1WOrrkjYVLMoUb8o 7W1xylkqCBuwwyec4s25XRD49u3lQ6DMCqvPS0pYWhGYnIBNJ/9AqFxyiSImloIv 7Wa6U/CSGXdsriIa1DLgol7m4AdWJIZ0Ay0qlzvLs+br2RpxJEUMglIMg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; s= default; bh=sXiR8KJPFoqxSTED3Q0Eqd9wrbk=; b=B5qPe1RStRDJcG7G63eh qQEGsnTZDo4Q/vhtL6qucrPHZmjP/gGrG1qB0e/tWKbC0CVAJYjrwBp9oByDtfDd jNdNfbNWH/yLqgCAnQYOfLWq3SPTQ4+zmzN+h3EQCJJksb6Sex4uFynNm/UrUzIE FFdYiDgFYAe1F5AJ0+C4vlQ= Received: (qmail 30391 invoked by alias); 11 Jul 2018 10:36:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30369 invoked by uid 89); 11 Jul 2018 10:36:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR03-VE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr50071.outbound.protection.outlook.com (HELO EUR03-VE1-obe.outbound.protection.outlook.com) (40.107.5.71) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 11 Jul 2018 10:36:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4DWygUzecMA61JB+uksSbDVljwyvtURCxjWrnRvH68M=; b=RvzKEy7v3v/twv6WQhk2gVvRkXqqiSvRoiTBWQLDFrSpI/gDdldFwzouXhN2IzQE0L5qjiRyohZ38+CZsB9EEcg9/+V7/NB9D02qtFszskgv47oG66pBMB5K6zEfG/Bu4NcuaoD70B0gYJ2p/Lsh/yLFqVzX/aOkhBZXNzaBqFE= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Matthew.Malcomson@arm.com; Received: from [10.2.207.76] (217.140.96.140) by HE1PR0801MB2012.eurprd08.prod.outlook.com (2603:10a6:3:50::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.930.20; Wed, 11 Jul 2018 10:36:33 +0000 To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, nd@arm.com From: Matthew Malcomson Subject: [PATCH][GCC][AARCH64] Canonicalize aarch64 widening simd plus insns Message-ID: <006edc68-c5a2-e77d-70d6-02ac77ef53e3@arm.com> Date: Wed, 11 Jul 2018 11:36:27 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-IsSubscribed: yes Hi there, The current RTL patterns for widening addition and subtraction instructions in aarch64-simd.md use the code iterator attribute to make their definition more compact. This approach means that the `minus` and `plus` cases have their operands in the same order, which causes problems in matching. The `minus` case needs the more complex operand second to be semantically correct, but the `plus` case needs the more complex operand first to be in canonical form. This patch splits the RTL patterns into two, one for `plus` and one for `minus` with differing operand order to match their differing requirements. Ready for trunk? Bootstrap and test on aarch64-none-linux-gnu Changelog for gcc/testsuite/Changelog 2018-07-10  Matthew Malcomson      * gcc.target/aarch64/vect-su-add-sub.c: New. Changelog for gcc/Changelog 2018-07-10  Matthew Malcomson      * config/aarch64/aarch64-simd.md (aarch64_w): Split into...     (aarch64_subw): ... This...     (aarch64_addw): ... And this. (aarch64_w_internal): Split into...     (aarch64_subw_internal): ... This...     (aarch64_addw_internal): ... And this. (aarch64_w2_internal): Split into...     (aarch64_subw2_internal): ... This...     (aarch64_addw2_internal): ... And this. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index aac5fa146ed8dde4507a0eb4ad6a07ce78d2f0cd..67b29cbe2cad91e031ee23be656ec61a403f2cf9 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3302,38 +3302,78 @@ DONE; }) -(define_insn "aarch64_w" +(define_insn "aarch64_subw" [(set (match_operand: 0 "register_operand" "=w") - (ADDSUB: (match_operand: 1 "register_operand" "w") - (ANY_EXTEND: - (match_operand:VD_BHSI 2 "register_operand" "w"))))] + (minus: + (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (match_operand:VD_BHSI 2 "register_operand" "w"))))] "TARGET_SIMD" - "w\\t%0., %1., %2." - [(set_attr "type" "neon__widen")] + "subw\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_w_internal" +(define_insn "aarch64_subw_internal" [(set (match_operand: 0 "register_operand" "=w") - (ADDSUB: (match_operand: 1 "register_operand" "w") - (ANY_EXTEND: - (vec_select: - (match_operand:VQW 2 "register_operand" "w") - (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))] + (minus: + (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))] "TARGET_SIMD" - "w\\t%0., %1., %2." - [(set_attr "type" "neon__widen")] + "subw\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_w2_internal" +(define_insn "aarch64_subw2_internal" [(set (match_operand: 0 "register_operand" "=w") - (ADDSUB: (match_operand: 1 "register_operand" "w") - (ANY_EXTEND: - (vec_select: - (match_operand:VQW 2 "register_operand" "w") - (match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))] + (minus: + (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))] + "TARGET_SIMD" + "subw2\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] +) + +(define_insn "aarch64_addw" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (ANY_EXTEND: + (match_operand:VD_BHSI 2 "register_operand" "w")) + (match_operand: 1 "register_operand" "w")))] "TARGET_SIMD" - "w2\\t%0., %1., %2." - [(set_attr "type" "neon__widen")] + "addw\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] +) + +(define_insn "aarch64_addw_internal" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "addw\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] +) + +(define_insn "aarch64_addw2_internal" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "addw2\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] ) (define_expand "aarch64_saddw2" diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c new file mode 100644 index 0000000000000000000000000000000000000000..15956ed83fdd5fc8dc895ab1ac4de3f98bc8a625 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* Ensure we use the signed/unsigned extend vectorized add and sub + instructions. */ +#define N 1024 + +int a[N]; +long c[N]; +long d[N]; +unsigned int ua[N]; +unsigned long uc[N]; +unsigned long ud[N]; + +void +add () +{ + for (int i = 0; i < N; i++) + d[i] = a[i] + c[i]; +} + +void +subtract () +{ + for (int i = 0; i < N; i++) + d[i] = c[i] - a[i]; +} + +void +uadd () +{ + for (int i = 0; i < N; i++) + ud[i] = ua[i] + uc[i]; +} + +void +usubtract () +{ + for (int i = 0; i < N; i++) + ud[i] = uc[i] - ua[i]; +} + +/* Ensure + saddw2 and one saddw for the function add() + ssubw2 and one ssubw for the function subtract() + uaddw2 and one uaddw for the function uadd() + usubw2 and one usubw for the function usubtract() */ + +/* { dg-final { scan-assembler-times "\[ \t\]ssubw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]ssubw\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]saddw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]saddw\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]usubw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]usubw\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]uaddw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]uaddw\[ \t\]+" 1 } } */