From patchwork Tue Jul 10 13:47:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 941999 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="m+mpDvSc"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Q3Rt72Dbz9s01 for ; Tue, 10 Jul 2018 23:47:54 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=um+0wxfkfcQ5zXbkPoxwsxavKilscLcsxcg7i07zEoI=; b=m+mpDvSc2hBiRvzs8gm+LcZv/a iC2rqxv9mJ5FUil996Dn0xf+wQtYNuT+TYxXJV4vyJE9P/HydZI1YG3TG6hx9udQlJkV/JO754VNp 2kiV0cO7tdr5umlsgd7Zg2KTe+f8tkDHyc17EqdcWxQqbVQ+bJUsJnbI32Yrs65JBwL5NNDn5mNCs hliwvL4k/abpnYV7jl7TonYBpFdpyFx78bi7cUrYDy/t+5TJjDR4Db9OtB7ncjTRK16+lKhhaPRIk 8R70WpquAvSreTxK+8Gq+ggEa1F5hJZSJIUFrBIWeMe7pmUN+JxZnjZcLGyuewLh9bQDPwkb+1qM2 i1MKVO2g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fcszf-0007YX-PR; Tue, 10 Jul 2018 13:47:51 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fcsyu-0006dE-BN for linux-arm-kernel@lists.infradead.org; Tue, 10 Jul 2018 13:47:07 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6A2CF1A00B8; Tue, 10 Jul 2018 15:47:00 +0200 (CEST) Received: from smtp.na-rdc02.nxp.com (inv1260.us-phx01.nxp.com [134.27.49.11]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 018E61A0039; Tue, 10 Jul 2018 15:47:00 +0200 (CEST) Received: from az84smr01.freescale.net (az84smr01.freescale.net [10.64.34.197]) by inv1260.na-rdc02.nxp.com (Postfix) with ESMTP id 7300B40C8A; Tue, 10 Jul 2018 06:46:59 -0700 (MST) Received: from fabio-Latitude-E5450.am.freescale.net (fabio-Latitude-E5450.am.freescale.net [10.29.244.117]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id w6ADkjtU027450; Tue, 10 Jul 2018 06:46:57 -0700 From: Fabio Estevam To: shawnguo@kernel.org Subject: [PATCH v2 6/6] ARM: mx5: Set the DBGEN bit in ARM_GPC register Date: Tue, 10 Jul 2018 10:47:36 -0300 Message-Id: <1531230456-27717-6-git-send-email-fabio.estevam@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531230456-27717-1-git-send-email-fabio.estevam@nxp.com> References: <1531230456-27717-1-git-send-email-fabio.estevam@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180710_064705_090380_E25779D0 X-CRM114-Status: GOOD ( 15.30 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [92.121.34.13 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Fabio Estevam , robh+dt@kernel.org, kernel@pengutronix.de, sebastian.reichel@collabora.co.uk, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On i.MX51/i.MX53 it is necessary to set the DBGEN bit in ARM_GPC register in order to turn on the debug clocks. The DBGEN bit of ARM_GPC register has the following description in the i.MX53 Reference Manual: "This allows the user to manually activate clocks within the debug system. This register bit directly controls the platform's dbgen_out output signal which connects to the DAP_SYS to enable all debug clocks. Once enabled, the clocks cannot be disabled except by asserting the disable_trace input of the DAP_SYS." Based on a previous patch from Sebastian Reichel. Signed-off-by: Fabio Estevam --- Changes since v1: - Annonate __init in mx5_pmu_init() - Unmap tigerp_base after use - Also touch mx51 arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu-imx5.c | 38 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mach-imx51.c | 2 +- arch/arm/mach-imx/mach-imx53.c | 2 +- 4 files changed, 41 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 93225db7..423dd76 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -62,6 +62,7 @@ void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); void imx25_pm_init(void); void imx27_pm_init(void); +void imx5_pmu_init(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index 4f2d1c7..d093017 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -117,3 +117,41 @@ int mx53_revision(void) return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); + +#define ARM_GPC 0x4 +#define DBGEN BIT(16) + +/* + * This enables the DBGEN bit in ARM_GPC register, which is + * required for accessing some performance counter features. + * Technically it is only required while perf is used, but to + * keep the source code simple we just enable it all the time + * when the kernel configuration allows using the feature. + */ +void __init imx5_pmu_init(void) +{ + void __iomem *tigerp_base; + struct device_node *np; + u32 gpc; + + if (!IS_ENABLED(CONFIG_ARM_PMU)) + return; + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); + if (!np) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp"); + if (!np) + return; + + tigerp_base = of_iomap(np, 0); + if (!tigerp_base) + return; + + gpc = readl_relaxed(tigerp_base + ARM_GPC); + gpc |= DBGEN; + writel_relaxed(gpc, tigerp_base + ARM_GPC); + iounmap(tigerp_base); + +} diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c index 3835b6a..8838fba 100644 --- a/arch/arm/mach-imx/mach-imx51.c +++ b/arch/arm/mach-imx/mach-imx51.c @@ -52,7 +52,7 @@ static void __init imx51_dt_init(void) { imx51_ipu_mipi_setup(); imx_src_init(); - + imx5_pmu_init(); imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); } diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 07c2e8d..5ec7100 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -31,7 +31,7 @@ static void __init imx53_init_early(void) static void __init imx53_dt_init(void) { imx_src_init(); - + imx5_pmu_init(); imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); }