From patchwork Fri Jul 6 14:18:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anssi Hannula X-Patchwork-Id: 940533 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bitwise.fi Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41McK90fxKz9s4Z for ; Sat, 7 Jul 2018 00:18:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932300AbeGFOSf (ORCPT ); Fri, 6 Jul 2018 10:18:35 -0400 Received: from mail.bitwise.fi ([109.204.228.163]:41546 "EHLO mail.bitwise.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753632AbeGFOSe (ORCPT ); Fri, 6 Jul 2018 10:18:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.bitwise.fi (Postfix) with ESMTP id 236536026C; Fri, 6 Jul 2018 17:18:33 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at mail.bitwise.fi Received: from mail.bitwise.fi ([127.0.0.1]) by localhost (mail.bitwise.fi [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EzSI7zXk4BYM; Fri, 6 Jul 2018 17:18:30 +0300 (EEST) Received: from localhost.sec.bitwise.fi (fw1.dmz.bitwise.fi [192.168.69.1]) (using TLSv1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: anssiha) by mail.bitwise.fi (Postfix) with ESMTPSA id BC17560243; Fri, 6 Jul 2018 17:18:30 +0300 (EEST) From: Anssi Hannula To: Wolfgang Grandegger , Marc Kleine-Budde Cc: Michal Simek , linux-can@vger.kernel.org, Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: can: xilinx_can: add Xilinx CAN FD bindings Date: Fri, 6 Jul 2018 17:18:15 +0300 Message-Id: <20180706141817.19729-2-anssi.hannula@bitwise.fi> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20180706141817.19729-1-anssi.hannula@bitwise.fi> References: <20180706141817.19729-1-anssi.hannula@bitwise.fi> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible string and new attributes to support the Xilinx CAN FD core. Unlike the previously documented Xilinx CAN cores, the CAN FD core has TX mailboxes instead of TX FIFO, and optionally RX mailboxes instead of RX FIFO (selected at core generation time, not switchable at runtime). Add "tx-mailbox-count" and "rx-mailbox-count" to specify the mailbox counts instead of reusing "tx-fifo-depth" and "rx-fifo-depth". The RX FIFO depth is constant 32, but allow it to be specified via "rx-fifo-depth" to match DT usage with Zynq CAN (which has constant RX FIFO of depth of 64). v2: Remove unnecessary "rx-mode" DT property. Signed-off-by: Anssi Hannula Cc: Michal Simek Reviewed-by: Rob Herring --- .../devicetree/bindings/net/can/xilinx_can.txt | 35 ++++++++++++++++------ 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt b/Documentation/devicetree/bindings/net/can/xilinx_can.txt index fe38847d8e26..ae5c07e96ad5 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx_can.txt +++ b/Documentation/devicetree/bindings/net/can/xilinx_can.txt @@ -2,20 +2,26 @@ Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings --------------------------------------------------------- Required properties: -- compatible : Should be "xlnx,zynq-can-1.0" for Zynq CAN - controllers and "xlnx,axi-can-1.00.a" for Axi CAN - controllers. -- reg : Physical base address and size of the Axi CAN/Zynq - CANPS registers map. +- compatible : Should be: + - "xlnx,zynq-can-1.0" for Zynq CAN controllers + - "xlnx,axi-can-1.00.a" for Axi CAN controllers + - "xlnx,canfd-1.0" for CAN FD controllers +- reg : Physical base address and size of the controller + registers map. - interrupts : Property with a value describing the interrupt number. - interrupt-parent : Must be core interrupt controller -- clock-names : List of input clock names - "can_clk", "pclk" - (For CANPS), "can_clk" , "s_axi_aclk"(For AXI CAN) +- clock-names : List of input clock names + - "can_clk", "pclk" (For CANPS), + - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD). (See clock bindings for details). - clocks : Clock phandles (see clock bindings for details). -- tx-fifo-depth : Can Tx fifo depth. -- rx-fifo-depth : Can Rx fifo depth. +- tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN). +- rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in + sequential Rx mode). +- tx-mailbox-count : Can Tx mailbox buffer count (CAN FD). +- rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx + mode). Example: @@ -42,3 +48,14 @@ For Axi CAN Dts file: tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; +For CAN FD Dts file: + canfd_0: canfd@40000000 { + compatible = "xlnx,canfd-1.0"; + clocks = <&clkc 0>, <&clkc 1>; + clock-names = "can_clk", "s_axi_aclk"; + reg = <0x40000000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <0 59 1>; + tx-mailbox-count = <0x20>; + rx-fifo-depth = <0x20>; + };