From patchwork Tue Jul 3 09:48:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 938560 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kQ9MbTpr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41KfMn0Vg3z9s29 for ; Tue, 3 Jul 2018 19:44:04 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2D5E4C21EFC; Tue, 3 Jul 2018 09:43:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 779BAC21D4A; Tue, 3 Jul 2018 09:43:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4C15C21D4A; Tue, 3 Jul 2018 09:43:52 +0000 (UTC) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by lists.denx.de (Postfix) with ESMTPS id 1636AC21C93 for ; Tue, 3 Jul 2018 09:43:52 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id j3-v6so743377pfh.11 for ; Tue, 03 Jul 2018 02:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id; bh=Eqrx3qwt/lfWqHPOmk2PMw8R3hKOK2tYKCEp1Eng7N4=; b=kQ9MbTprHl9508W07HamAs3/aIsQQIvvJ80ZBIbIZzW2jTyGiiFBLKCx7Asb3QhEo4 6LQ7Pr7mpY4a8EihF4dUu7pMuBb2W/ChzP1TlI5jLOp7DVK9yo88QenvfE3vYRJSInjS wsveP9iJ00gtEYhFhrZ9bK5AyiIinLApEakq39zVvmKKBQCNHUKUpkRu/EHn6yuw4sqo YLcxOb5D7oFOqduHOyCKpc/8X3sjVTSKysWxAp44Z8jM5rXcL/xLHRYsg/F//B02z6xg GRZpebcALyNNW9GtG5CvIzJYTaT5fe3k3SW7ohB3D5oNU8P04PZ7wjZVjL/hwns+uNIj 5ndw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=Eqrx3qwt/lfWqHPOmk2PMw8R3hKOK2tYKCEp1Eng7N4=; b=RtN8ASJ4TXxRCgphVano7z4/NfrkS+PWOZat9W4Awy6iHYpyVfcQoIScHLIkeg6f0c XMObtY3mvyFQ7lBcZKq4Jkkhw5WXTyuIVPNqWaR0+t0vXrGu5fWPUStalMqLgh3UgG2G JyqJnMWu32FOhpD/18lflmcmUN7pusAN/g4C2cGNsfjcLfEV4/SL7Gz79uY1K84VSCfh uEWQSHF6Jg8njUAj2Vqh5tSwrOVbO9+ug76ziT0U15mOgJotNJ5zF3Pff6koqNLoNVLs tflZD6a/9Q/T1JeADCD66OoX1joZ/VP0w6bVoVeNYw84jHt8YNBxK+cksd5gyNIkFi+j J5RQ== X-Gm-Message-State: APt69E17SFe6XF6MNPSORyYYPh4Tmq1YjII3vu7RODYqOfu/PX776Ueo e8F9T2PcuG6A2Wr9yk7E6vlg7g== X-Google-Smtp-Source: AAOMgpcpNl4dwws3ovfMljAl1jNYkcK/ewd6mdwsrIsQLnT4nz0DSPlT7R1P/wavgA0e+kDP1Bss4g== X-Received: by 2002:a65:6243:: with SMTP id q3-v6mr22300043pgv.273.1530611030671; Tue, 03 Jul 2018 02:43:50 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id d18-v6sm1721593pfn.118.2018.07.03.02.43.49 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Jul 2018 02:43:49 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , George McCollister , Andy Shevchenko , U-Boot Mailing List Date: Tue, 3 Jul 2018 02:48:39 -0700 Message-Id: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 Subject: [U-Boot] [PATCH 1/4] x86: quark: acpi: Add full reset bit to the reset register value in FADT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds full reset bit in the reset register value in the ACPI FADT table, so that kernel can do a thorough reboot. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/quark/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 4a02720..7b6fc2f 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -67,7 +67,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = IO_PORT_RESET; fadt->reset_reg.addrh = 0; - fadt->reset_value = SYS_RST | RST_CPU; + fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; From patchwork Tue Jul 3 09:48:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 938562 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nk6p4oUi"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41KfNX4tNmz9s29 for ; Tue, 3 Jul 2018 19:44:44 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 4E264C21EE7; Tue, 3 Jul 2018 09:44:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 41E86C21EA7; Tue, 3 Jul 2018 09:43:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 138B0C21D4A; Tue, 3 Jul 2018 09:43:54 +0000 (UTC) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by lists.denx.de (Postfix) with ESMTPS id 7B8C3C21C93 for ; Tue, 3 Jul 2018 09:43:53 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id j17-v6so751685pfn.5 for ; Tue, 03 Jul 2018 02:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=Z+PAmIKXwQI6TwoJeVWKihcmurOydItHVXdqctlAB1I=; b=nk6p4oUiJX5pMX38KycroD2hKvAIaB2C1w/Vi0ZuH9+2wMZvwNo3Wh4M26vw6N2p5u Ogzd+UYabKMDl4dDeY1bfp59GMe62U9pF6Ktdo2FbDu42GhYhDYOm1INPoCviw28JXjV g8rastfHvzqT+VxICYl+nl4LUyORk+2q7mCRTaX5tVEj48fcExAi2JYcbJ/c98McJR2H L4WyKG5Q0yd7G5KE2hGR+fUEu5EeBSui3MVw4npQYSuVuy9MUCbrgjCzyiV3/7YZuds6 /3+aYZydh5B8083dlLHW4zJWIbuH2+xrZLAovxA/Ki16WXBccXQzmWe1+f/imlTz9Qi5 5eLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Z+PAmIKXwQI6TwoJeVWKihcmurOydItHVXdqctlAB1I=; b=Ghbdo2c7IGLfO6B0H3v2YfY1N7PDOBIbx1DEG4Di8ITZY9XXcz326cRT8esG+zo2LA aF9alpXs+cOOLouRgORwm9/D05FSI3F14/arYF3MIHFHgJNeloQrLf9tbm/CnoUCgGgD WvKMceCZF9pqUDY+zKcoYkFy0jKo4eyif8KqXXxT6tMvC6A1/pyCAEv9cw6MV7mVS0QW OcAqglwliv3idUv6vGZtp/1XMA/wVnTQFDIRK5y19Ly6g/h2xc7YpTsWxplCf9n2axB7 dmX+jSWAppIiUklPYMeLlE4j1ZvK0v7pF978MNbjq5By2yxg+w5pOkykEUcgWDLTa+Ep DY2g== X-Gm-Message-State: APt69E2HSCcA/Y2/31yf7u7U8YFulttRBPbue5G3uA8ejCY6d5iABPQr lJryiO0xuD8t6HBVgCGKKX8= X-Google-Smtp-Source: ADUXVKJsvgh7376jVsu7Zy6SRT7bh6wPNP4cmZKVRfPZLV9V3qwOwNEKDx5/kfrc+PLehHp8qjjLcA== X-Received: by 2002:a63:b505:: with SMTP id y5-v6mr25450484pge.213.1530611032238; Tue, 03 Jul 2018 02:43:52 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id d18-v6sm1721593pfn.118.2018.07.03.02.43.50 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Jul 2018 02:43:51 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , George McCollister , Andy Shevchenko , U-Boot Mailing List Date: Tue, 3 Jul 2018 02:48:40 -0700 Message-Id: <1530611322-20965-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> References: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 2/4] dm: sysreset: x86: Add a sysreset driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a generic reset driver for x86 processor. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/sysreset/Kconfig | 6 +++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_x86.c | 49 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 drivers/sysreset/sysreset_x86.c diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index a6d48e8..2afeadc 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -37,4 +37,10 @@ config SYSRESET_WATCHDOG help Reboot support for generic watchdog reset. +config SYSRESET_X86 + bool "Enable support for x86 processor reboot driver" + depends on X86 + help + Reboot support for generic x86 processor reset. + endmenu diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 0da58a1..0eb0dc7 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o +obj-$(CONFIG_SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c new file mode 100644 index 0000000..5943a63 --- /dev/null +++ b/drivers/sysreset/sysreset_x86.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * Generic reset driver for x86 processor + */ + +#include +#include +#include +#include +#include + +static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + int value; + + switch (type) { + case SYSRESET_WARM: + value = SYS_RST | RST_CPU; + break; + case SYSRESET_COLD: + value = SYS_RST | RST_CPU | FULL_RST; + break; + default: + return -ENOSYS; + } + + outb(value, IO_PORT_RESET); + + return -EINPROGRESS; +} + +static const struct udevice_id x86_sysreset_ids[] = { + { .compatible = "x86,reset" }, + { } +}; + +static struct sysreset_ops x86_sysreset_ops = { + .request = x86_sysreset_request, +}; + +U_BOOT_DRIVER(x86_sysreset) = { + .name = "x86-sysreset", + .id = UCLASS_SYSRESET, + .of_match = x86_sysreset_ids, + .ops = &x86_sysreset_ops, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Jul 3 09:48:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 938563 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Vl8UiGJq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41KfPz6bSSz9s29 for ; Tue, 3 Jul 2018 19:45:59 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8CBDAC21E8A; Tue, 3 Jul 2018 09:44:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0F10DC21F19; Tue, 3 Jul 2018 09:44:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E01C2C21F19; Tue, 3 Jul 2018 09:44:02 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 33FEEC21C93 for ; Tue, 3 Jul 2018 09:43:55 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id z1-v6so714109pgv.12 for ; Tue, 03 Jul 2018 02:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=GU2jxB8eh6v+b816luil/PhiU7l99GG688/GE6mOyH4=; b=Vl8UiGJqzbB+gRWJAKk0qKnDqibb4d+ZbGV/+AWbO/AA4EXIDUzZv4PD1cOykpQutw KgZdAAooFg1JeUwnlxDNcxoZx4TvOJOiQHpymJ1Vnm6VLMPY51fRyOAxtJHoxdW8bTa3 nKv7MNXff/OddPupHQ1NAw9MgdGZSObcOGJPP1o+2bLSphBbskFWhFMGehE9vtxpDib3 gJGNCNcuPaFrozH0GAc1pl4ibtk3cb4T8ghKv/gFvyBMTUYru9Rfihc7s0Wp+RxCdyTd XK9niY7FVlMa74ADAXC2A2sIuVaja2Z0MFqWGlP3IWPQY9sErHsTQ3oewDgMJIBlkXob QsVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=GU2jxB8eh6v+b816luil/PhiU7l99GG688/GE6mOyH4=; b=Za0gEb56Uz5FHdx2tJ2sgO3dBNXZTcah/t0C5ivNIzAx1yCvb8n31EqSVCbEQ+x3VH R4g0+8N/jujFlY5xFk9xGJlQA2Ag0Oey5CPl7F9FaavBGCdxgi2cclGRaNAq1SRXXChm mnSQabxsXF89dPSp+t5vktZqWE9QJyZK1X6Y7VgKycdLpruZxCjKRKPcXYYcBzkWK98T 7GoOPEKpUBWg0RRlmnsc45yN7T1FEyT0Z8awBivm1sTe3TM8JE2SSUOS6NLynmrONhYF FjbnSLfaBCqLvejNciuR77C8dHJmfZvbNEdv7AqVjRbS9t3KCw8tV9wdrcuC2tBPCuCl qMEw== X-Gm-Message-State: APt69E3W3g5UcRDQDse/g3KSTFVkLZopKs4an79aIh/XBJZ8J2a56IzC LlG5IEyVmb3za5xLUnTxOX8= X-Google-Smtp-Source: ADUXVKI/h8oYOFQe3ZFkwZaciiCy8W3Un5dq+sap/Ro71F9/CXncfqT7+r8O0/NO8UTnhqR4+HMtmw== X-Received: by 2002:a65:4c02:: with SMTP id u2-v6mr25417487pgq.364.1530611033802; Tue, 03 Jul 2018 02:43:53 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id d18-v6sm1721593pfn.118.2018.07.03.02.43.52 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Jul 2018 02:43:52 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , George McCollister , Andy Shevchenko , U-Boot Mailing List Date: Tue, 3 Jul 2018 02:48:41 -0700 Message-Id: <1530611322-20965-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> References: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 3/4] x86: fsp: Eliminate the reset_cpu() call X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In preparation for the reset driver conversion, eliminate the reset_cpu() call in the FSP init path as it's too early for the reset driver to work. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/lib/fsp/fsp_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index b4ba129..d5ed1d5 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -132,7 +132,7 @@ int arch_fsp_init(void) chipset_clear_sleep_state(); /* Reboot */ debug("Rebooting..\n"); - reset_cpu(0); + outb(SYS_RST | RST_CPU, IO_PORT_RESET); /* Should not reach here.. */ panic("Reboot System"); } From patchwork Tue Jul 3 09:48:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 938566 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z3KEvo8D"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41KfQ421HDz9s2g for ; Tue, 3 Jul 2018 19:46:04 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C083CC21EA7; Tue, 3 Jul 2018 09:45:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BC464C21F01; Tue, 3 Jul 2018 09:44:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E9E07C21F21; Tue, 3 Jul 2018 09:44:02 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id E0DBDC21F05 for ; Tue, 3 Jul 2018 09:43:56 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id k1-v6so773919plt.2 for ; Tue, 03 Jul 2018 02:43:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=aeX6mLKeOplXSkDaQclgDdy01Kc+08iyQGYMuJHSA8w=; b=Z3KEvo8Dp479y2GY8JQwvqDIwqfWMz9tz4TZ13aBI49mF0bIJMqknLqx3/weTg5P// UX94/1vm3omMqjAAEdTnPPbuXpGEPs+MzIzjxepf7J5Hb7TR2n3yad3xgC//XyGydpuV MHYTDk59lLl9Ce7uG3UnkjScBq/GbIXY8mZh/WEXr/AJAqvRDnLC5HK239ylEMbrr1Q9 nosLwFjzxfwWsLdqvfvkE2oWWz8DoRxwntlZIsA5/nXLFUxW+YPPEDnKEBpEAzygA+VO IaHEbZ4elSH4y2O16aGq8rPEn/pUlyqSdIIPQNQ4eGRhwXVeK6bEx6iPEKYinYBig0Tv VPuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=aeX6mLKeOplXSkDaQclgDdy01Kc+08iyQGYMuJHSA8w=; b=ImXVdHEkeJ7sDgP4YkY0R3jUJ8vME91lUQ0l0dusl9dq5yPL3+zmQFCtUwaAXiZ/5D B3mzIJe8TNG9elbnWlaP9psdwnzrspvsaWIIBHOevyPc9s1BxDnuTMkuKySSgkn7qnth mc30ICOty5K4gTtIJMc3nhIN0EeXRGHM/miFkWvAaaHECP7HILgqCOc4ylwFTlq2PnPj RjvQe8ZH/m50loDhhwTu9u73eM/B0xe8df5rjU70Mrcb7c1yYacpdCOt0omm7+p+ZoD8 +48/51fULRmG/bui9uxnCYcv8Fz1ibqM1r/dWqa4he/r77BB3YILFtrFny2nGhMrwF/U zcQA== X-Gm-Message-State: APt69E0eTu0PA1lyKKz5vLkZwLZUAz/PtfIIFU5/2r4ezlb1bKa6YEEg luQjOXj8W+mRP+E2zdcloig= X-Google-Smtp-Source: ADUXVKJJE0a2We6U1LftdLKyQw/jalslAKvISWuLRqcmmsgZWBA0HP3VMTYBZpYqRea9SxZ4C6Y7Rw== X-Received: by 2002:a17:902:123:: with SMTP id 32-v6mr28736110plb.181.1530611035362; Tue, 03 Jul 2018 02:43:55 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id d18-v6sm1721593pfn.118.2018.07.03.02.43.53 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Jul 2018 02:43:54 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , George McCollister , Andy Shevchenko , U-Boot Mailing List Date: Tue, 3 Jul 2018 02:48:42 -0700 Message-Id: <1530611322-20965-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> References: <1530611322-20965-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 4/4] x86: Switch to use DM sysreset driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This converts all x86 boards over to DM sysreset. Signed-off-by: Bin Meng --- arch/Kconfig | 2 ++ arch/x86/cpu/baytrail/valleyview.c | 6 ------ arch/x86/cpu/braswell/braswell.c | 6 ------ arch/x86/cpu/cpu.c | 26 -------------------------- arch/x86/cpu/ivybridge/early_me.c | 7 ++++--- arch/x86/cpu/ivybridge/sdram.c | 3 ++- arch/x86/cpu/qemu/qemu.c | 6 ------ arch/x86/cpu/quark/quark.c | 6 ------ arch/x86/cpu/tangier/tangier.c | 8 ++++++++ arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/baytrail_som-db5800-som-6867.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/cherryhill.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebook_samus.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/conga-qeval20-qa3-e3845.dts | 1 + arch/x86/dts/cougarcanyon2.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/dfi-bt700.dtsi | 1 + arch/x86/dts/edison.dts | 1 + arch/x86/dts/efi-x86_payload.dts | 1 + arch/x86/dts/galileo.dts | 1 + arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 1 + arch/x86/dts/qemu-x86_q35.dts | 1 + arch/x86/dts/reset.dtsi | 6 ++++++ arch/x86/include/asm/processor.h | 5 ----- arch/x86/include/asm/u-boot-x86.h | 1 - configs/chromebook_link64_defconfig | 1 + configs/edison_defconfig | 1 + configs/efi-x86_app_defconfig | 1 + 32 files changed, 42 insertions(+), 60 deletions(-) create mode 100644 arch/x86/dts/reset.dtsi diff --git a/arch/Kconfig b/arch/Kconfig index dd5a887..cbeb9f6 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -118,6 +118,8 @@ config X86 imply DM_SPI_FLASH imply DM_USB imply DM_VIDEO + imply SYSRESET + imply SYSRESET_X86 imply CMD_FPGA_LOADMK imply CMD_GETTIME imply CMD_IO diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index b7d481a..8882a76 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -55,9 +55,3 @@ int arch_misc_init(void) return 0; } - -void reset_cpu(ulong addr) -{ - /* cold reset */ - x86_full_reset(); -} diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c index 32a6a5e..7a83b06 100644 --- a/arch/x86/cpu/braswell/braswell.c +++ b/arch/x86/cpu/braswell/braswell.c @@ -27,9 +27,3 @@ int arch_misc_init(void) return 0; } - -void reset_cpu(ulong addr) -{ - /* cold reset */ - x86_full_reset(); -} diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 3a45677..395f845 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -76,37 +76,11 @@ int x86_init_cache(void) } int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("resetting ...\n"); - - /* wait 50 ms */ - udelay(50000); - disable_interrupts(); - reset_cpu(0); - - /*NOTREACHED*/ - return 0; -} - void flush_cache(unsigned long dummy1, unsigned long dummy2) { asm("wbinvd\n"); } -__weak void reset_cpu(ulong addr) -{ - /* Do a hard reset through the chipset's reset control register */ - outb(SYS_RST | RST_CPU, IO_PORT_RESET); - for (;;) - cpu_hlt(); -} - -void x86_full_reset(void) -{ - outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); -} - /* Define these functions to allow ehch-hcd to function */ void flush_dcache_range(unsigned long start, unsigned long stop) { diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index 1a15229..219d5be 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -138,17 +139,17 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, case ME_HFS_ACK_RESET: /* Non-power cycle reset */ set_global_reset(dev, 0); - reset_cpu(0); + sysreset_walk_halt(SYSRESET_COLD); break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ set_global_reset(dev, 0); - x86_full_reset(); + sysreset_walk_halt(SYSRESET_COLD); break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ set_global_reset(dev, 1); - x86_full_reset(); + sysreset_walk_halt(SYSRESET_COLD); break; case ME_HFS_ACK_S3: case ME_HFS_ACK_S4: diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 2f253e8..8a58d03 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -497,7 +498,7 @@ int dram_init(void) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { debug("Giving up in sdram_initialize: No MRC data\n"); - reset_cpu(0); + sysreset_walk_halt(SYSRESET_COLD); } /* Pass console handler in pei_data */ diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index ca4b3f0..5e8b4f0 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -156,12 +156,6 @@ int print_cpuinfo(void) } #endif -void reset_cpu(ulong addr) -{ - /* cold reset */ - x86_full_reset(); -} - int arch_early_init_r(void) { qemu_chipset_init(); diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 4fd6864..d39edb2 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -270,12 +270,6 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } -void reset_cpu(ulong addr) -{ - /* cold reset */ - x86_full_reset(); -} - static void quark_pcie_init(void) { u32 val; diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c index 0a15e64..4b623bb 100644 --- a/arch/x86/cpu/tangier/tangier.c +++ b/arch/x86/cpu/tangier/tangier.c @@ -25,7 +25,15 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } +/* TODO: convert to DM sysreset */ void reset_cpu(ulong addr) { scu_ipc_simple_command(IPCMSG_COLD_RESET, 0); } + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + reset_cpu(0); + + return 0; +} diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 74291a8..9683c52 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -12,6 +12,7 @@ /include/ "skeleton.dtsi" /include/ "keyboard.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" /include/ "coreboot_fb.dtsi" diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 36e6069..4e8a761 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -12,6 +12,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 3966199..ec691f1 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" /include/ "coreboot_fb.dtsi" diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 3e29683..39e2d2f 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 26b9f85..115a088 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -5,6 +5,7 @@ /include/ "skeleton.dtsi" /include/ "keyboard.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" /include/ "coreboot_fb.dtsi" diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 52a9ea6..9c48c9a 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -5,6 +5,7 @@ /include/ "skeleton.dtsi" /include/ "keyboard.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" /include/ "coreboot_fb.dtsi" diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index b25c919..a72a85e 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" /include/ "coreboot_fb.dtsi" diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index c3d1514..5884dbc 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -12,6 +12,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index c1cda73..9801790 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index d8faa9d..2ffcc5f 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index cb96fdf..51d33e7 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -9,6 +9,7 @@ #include #include "skeleton.dtsi" +#include "reset.dtsi" #include "rtc.dtsi" #include "tsc_timer.dtsi" diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index 9033532..a1d3c90 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -9,6 +9,7 @@ #include /include/ "skeleton.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts index 148b587..19f2530 100644 --- a/arch/x86/dts/efi-x86_payload.dts +++ b/arch/x86/dts/efi-x86_payload.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 3454abd..3a5d168 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -9,6 +9,7 @@ #include /include/ "skeleton.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 42ba0c7..02ab4c1 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" /include/ "coreboot_fb.dtsi" diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 6565429..2e5210d 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index f1c4cb9..e8f55b1 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -20,6 +20,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" diff --git a/arch/x86/dts/reset.dtsi b/arch/x86/dts/reset.dtsi new file mode 100644 index 0000000..f979d83 --- /dev/null +++ b/arch/x86/dts/reset.dtsi @@ -0,0 +1,6 @@ +/ { + reset { + compatible = "x86,reset"; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index dd957d2..f1d9977 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -43,11 +43,6 @@ enum { FULL_RST = 1 << 3, /* full power cycle */ }; -/** - * x86_full_reset() - reset everything: perform a full power cycle - */ -void x86_full_reset(void); - static inline __attribute__((always_inline)) void cpu_hlt(void) { asm("hlt"); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 2340ef8..670fcdc 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -40,7 +40,6 @@ int x86_cleanup_before_linux(void); void x86_enable_caches(void); void x86_disable_caches(void); int x86_init_cache(void); -void reset_cpu(ulong addr); ulong board_get_usable_ram_top(ulong total_size); int default_print_cpuinfo(void); diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 59b6bd0..9af2c4d 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 54305fc..d3d8816 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -32,6 +32,7 @@ CONFIG_CPU=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DM_PCI_COMPAT=y +# CONFIG_SYSRESET is not set CONFIG_USB_DWC3_GADGET=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Intel" diff --git a/configs/efi-x86_app_defconfig b/configs/efi-x86_app_defconfig index 9c1d5e7..7fba2be 100644 --- a/configs/efi-x86_app_defconfig +++ b/configs/efi-x86_app_defconfig @@ -30,6 +30,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_DM_ETH is not set CONFIG_DEBUG_EFI_CONSOLE=y +# CONFIG_SYSRESET is not set # CONFIG_REGEX is not set CONFIG_EFI=y # CONFIG_EFI_LOADER is not set