From patchwork Wed Jun 27 09:50:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 935364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-480545-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="bdDUzDQs"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41FypV4H4Hz9s0w for ; Wed, 27 Jun 2018 19:50:58 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=Dh/Oyjn/ZAWC/UoYx0iIFSGJtNboHLzQs8vAwzhXvfdSLF zd4ZzOORtBxK0C4yLAWGwEcuxzUpKXkOI83IqgkiZQrgYiFwD/kH1HoDvxFwL68d 3VLp+tcuxQyCFTCH25gd3FkLiecVqPxK75qQRhw4n1dwLeDSi1k4MZCIfd4nI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=p8yTOdkXAAwpOQr1tNOSVEMVj0I=; b=bdDUzDQsdxCNOWyt0hjW X06cXXdcMZXfpU+y9ucM83ZlwKW/Go8NGdS9BQmRndX7FkV8SlN/7knLeR6SjqQS 9lPkUeg5AjfA3ifr2VzewHIigztYv0TKlQ4+yVRciWTXSsasrwcCioXRh2EBDpaw XHFL5QLLEfhKsmC91GRAgB8= Received: (qmail 10697 invoked by alias); 27 Jun 2018 09:50:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10566 invoked by uid 89); 27 Jun 2018 09:50:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, KAM_NUMSUBJECT autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 27 Jun 2018 09:50:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 719937A9 for ; Wed, 27 Jun 2018 02:50:42 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DE743F5AD for ; Wed, 27 Jun 2018 02:50:41 -0700 (PDT) Message-ID: <5B335DF0.2010201@foss.arm.com> Date: Wed, 27 Jun 2018 10:50:40 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH][arm] Add support for Arm Cortex-A76 Hi all, The Cortex-A76 is an Armv8.2-A processor with dotproduct and FP16 support. It can be paired with the Cortex-A55 and hence the option -mcpu/-mtune=cortex-a76.cortex-a55 is also introduced. Bootstrapped and tested on arm-none-linux-gnueabihf. Committing to trunk. Thanks, Kyrill 2018-06-27 Kyrylo Tkachov * config/arm/arm-cpus.in (cortex-a76): New entry. (cortex-a76.cortex-a55): Likewise. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/driver-arm.c (arm_cpu_table): Add Cortex-A76 entry. * doc/invoke.texi (ARM Options): Document cortex-a76 and cortex-a76.cortex-a55. diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index aec73b5cae0b9d62c521c230aff510ce3d816e3b..e100610a58364f78489a72ea8bfdfedf8d3ca47b 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1339,6 +1339,15 @@ begin cpu cortex-a75 costs cortex_a73 end cpu cortex-a75 +begin cpu cortex-a76 + cname cortexa76 + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.2-a+fp16+dotprod + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 +end cpu cortex-a76 # ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations begin cpu cortex-a75.cortex-a55 @@ -1351,6 +1360,16 @@ begin cpu cortex-a75.cortex-a55 costs cortex_a73 end cpu cortex-a75.cortex-a55 +begin cpu cortex-a76.cortex-a55 + cname cortexa76cortexa55 + tune for cortex-a53 + tune flags LDSCHED + architecture armv8.2-a+fp16+dotprod + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 +end cpu cortex-a76.cortex-a55 + # V8 M-profile implementations. begin cpu cortex-m23 cname cortexm23 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 0ffb4c86ca46718bbfaf65eb41ab8e87f924e903..eacee746a39912d04aa03c636f9a95e0e72ce43b 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -280,9 +280,15 @@ EnumValue Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75) EnumValue +Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76) + +EnumValue Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55) EnumValue +Enum(processor_type) String(cortex-a76.cortex-a55) Value( TARGET_CPU_cortexa76cortexa55) + +EnumValue Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 877e3465147b8b829166b8c0f9c464ca38e0b73a..f64c1ef176de6c31659cce35326de8393e9cd886 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,6 +49,7 @@ (define_attr "tune" cortexa72,cortexa73,exynosm1, xgene1,cortexa57cortexa53,cortexa72cortexa53, cortexa73cortexa35,cortexa73cortexa53,cortexa55, - cortexa75,cortexa75cortexa55,cortexm23, - cortexm33,cortexr52" + cortexa75,cortexa76,cortexa75cortexa55, + cortexa76cortexa55,cortexm23,cortexm33, + cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index dc2f1de01a8de89adccfde3834ae7a04fa3095a6..356a5e664b6bb9489f98d3cfe54703f6aadf8ed4 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -56,6 +56,7 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xd09", "armv8-a+crc", "cortex-a73"}, {"0xd05", "armv8.2-a+fp16+dotprod", "cortex-a55"}, {"0xd0a", "armv8.2-a+fp16+dotprod", "cortex-a75"}, + {"0xd0b", "armv8.2-a+fp16+dotprod", "cortex-a76"}, {"0xc14", "armv7-r", "cortex-r4"}, {"0xc15", "armv7-r", "cortex-r5"}, {"0xc17", "armv7-r", "cortex-r7"}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a56b6afc0167e8589aa3b5372c29342e3372a833..a6f432422c96e84c161d11786f795f2c35ec7e97 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16281,8 +16281,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, -@samp{cortex-r8}, @samp{cortex-r52}, +@samp{cortex-a76}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, +@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-m33}, @samp{cortex-m23}, @samp{cortex-m7}, @@ -16306,7 +16306,7 @@ of the code for a big.LITTLE system. Permissible names are: @samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}, -@samp{cortex-a75.cortex-a55}. +@samp{cortex-a75.cortex-a55}, @samp{cortex-a76.cortex-a55}. @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}.