From patchwork Tue Jun 26 06:22:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chiang, AlanX" X-Patchwork-Id: 934686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41FGDT1Q3rz9s0W for ; Tue, 26 Jun 2018 16:22:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751937AbeFZGWb (ORCPT ); Tue, 26 Jun 2018 02:22:31 -0400 Received: from mga09.intel.com ([134.134.136.24]:51873 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935AbeFZGWb (ORCPT ); Tue, 26 Jun 2018 02:22:31 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jun 2018 23:22:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,273,1526367600"; d="scan'208";a="240651371" Received: from shawn-bm6650-bm6350.itwn.intel.com ([10.5.253.27]) by fmsmga006.fm.intel.com with ESMTP; 25 Jun 2018 23:22:27 -0700 From: alanx.chiang@intel.com To: linux-i2c@vger.kernel.org Cc: andy.yeh@intel.com, sakari.ailus@linux.intel.com, andriy.shevchenko@intel.com, rajmohan.mani@intel.com, andy.shevchenko@gmail.com, brgl@bgdev.pl, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, "alanx.chiang" Subject: [PATCH v2 1/2] dt-bindings: at24: Add address-width property Date: Tue, 26 Jun 2018 14:22:07 +0800 Message-Id: <1529994128-26770-2-git-send-email-alanx.chiang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> References: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: "alanx.chiang" The AT24 series chips use 8-bit address by default. If some chips would like to support more than 8 bits, should add the compatible field for specfic chips in the driver. Provide a flexible way to determine the addressing bits through address-width in this patch. Signed-off-by: Alan Chiang Signed-off-by: Andy Yeh --- since v1: -- Remove the address-width field in the example. --- Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index 61d833a..9467482 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -72,6 +72,8 @@ Optional properties: - wp-gpios: GPIO to which the write-protect pin of the chip is connected. + - address-width : number of address bits (one of 8, 16). + Example: eeprom@52 { From patchwork Tue Jun 26 06:22:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chiang, AlanX" X-Patchwork-Id: 934687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41FGDl4yHjz9s0W for ; Tue, 26 Jun 2018 16:22:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752081AbeFZGWh (ORCPT ); Tue, 26 Jun 2018 02:22:37 -0400 Received: from mga09.intel.com ([134.134.136.24]:51873 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935AbeFZGWf (ORCPT ); Tue, 26 Jun 2018 02:22:35 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jun 2018 23:22:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,273,1526367600"; d="scan'208";a="240651390" Received: from shawn-bm6650-bm6350.itwn.intel.com ([10.5.253.27]) by fmsmga006.fm.intel.com with ESMTP; 25 Jun 2018 23:22:32 -0700 From: alanx.chiang@intel.com To: linux-i2c@vger.kernel.org Cc: andy.yeh@intel.com, sakari.ailus@linux.intel.com, andriy.shevchenko@intel.com, rajmohan.mani@intel.com, andy.shevchenko@gmail.com, brgl@bgdev.pl, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, "alanx.chiang" Subject: [PATCH v2 2/2] eeprom: at24: Add support for address-width property Date: Tue, 26 Jun 2018 14:22:08 +0800 Message-Id: <1529994128-26770-3-git-send-email-alanx.chiang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> References: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: "alanx.chiang" Provide a flexible way to determine the addressing bits of eeprom. Pass the addressing bits to driver through address-width property. Signed-off-by: Alan Chiang Signed-off-by: Andy Yeh --- since v1 -- Add a warn message for 8-bit addressing. --- drivers/misc/eeprom/at24.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c index 0c125f2..231afcd 100644 --- a/drivers/misc/eeprom/at24.c +++ b/drivers/misc/eeprom/at24.c @@ -478,6 +478,22 @@ static void at24_properties_to_pdata(struct device *dev, if (device_property_present(dev, "no-read-rollover")) chip->flags |= AT24_FLAG_NO_RDROL; + err = device_property_read_u32(dev, "address-width", &val); + if (!err) { + switch (val) { + case 8: + chip->flags &= ~AT24_FLAG_ADDR16; + dev_warn(dev, "address-width is 8, clear the ADD16 bit\n"); + break; + case 16: + chip->flags |= AT24_FLAG_ADDR16; + break; + default: + dev_warn(dev, "Bad \"address-width\" property: %u\n", + val); + } + } + err = device_property_read_u32(dev, "size", &val); if (!err) chip->byte_len = val;