From patchwork Sat Jun 23 16:11:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 933732 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="TKdWxPGb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41CgSN73GBz9s2t for ; Sun, 24 Jun 2018 02:12:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751869AbeFWQMT (ORCPT ); Sat, 23 Jun 2018 12:12:19 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:44881 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751813AbeFWQMQ (ORCPT ); Sat, 23 Jun 2018 12:12:16 -0400 Received: by mail-pg0-f66.google.com with SMTP id b10-v6so575601pgq.11 for ; Sat, 23 Jun 2018 09:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aNqyghA/+YELYPCfAy6P30ix4otp9ywUK1kCBsmdfz8=; b=TKdWxPGbA2P8mJ8pTPUEymQDMHiAV/hb8buSDOTUxI/giKhi3IhCSLPROJQ7PEHEg4 Am/7DhH2PvxmsXhWS1dN4VQ7U6h8K1KdFdSYCfA0QynoQf47CX/ekCkXNLH0bWuHyQH8 z403H4Jfo4RU/+jKy2qKY8hs1xZHr+7anY8aU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aNqyghA/+YELYPCfAy6P30ix4otp9ywUK1kCBsmdfz8=; b=MlZIrlXoJ6u3EJ9mLMOgJ1Z/OlFIgBe2XULV4tS589UY3vzQpSKataxRrHVZrcpSQA zO1qRUlJEisHVQYl31ppzOxdDIYrhH1dddJMo4TxVVuBe2i/kf5j0zBGSHHVbcZSiHcp 9Q3kRkRfl9TNct0vh3bgJk/CieQngIwqHW3OApv1pqPSwuv839BEBM8u4qWKpN2J9tDc xEZ9sCvuZI4pzUeb1H3NUbQ8VE6olQqAJRHGSjDwcHDR1fTbBDJNY274QOHmeL2ImfNx DwcVPOPKVObbTGcpIv8RnqeziLPKgckxH7s3H5wUgEP+F5pb+EPid0QbC69A/BF0SecM i/uA== X-Gm-Message-State: APt69E0TrLJZb2KSaBVtLZMko9yqyq5b5An0AO/vwlZXkMyghFGceNl3 MrokEd4a7WWvovcc3SP7obFr X-Google-Smtp-Source: ADUXVKITb1R6Z18vRUZq7FtWFrHipA6gSepbsIOEvq36HtyslJCpBRANJCtc7K0WY4xpWuHKvZ9n3g== X-Received: by 2002:a63:bf49:: with SMTP id i9-v6mr5330556pgo.342.1529770336159; Sat, 23 Jun 2018 09:12:16 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:100:fa16:6549:5166:32c7:2dab]) by smtp.gmail.com with ESMTPSA id n26-v6sm2732745pfi.168.2018.06.23.09.12.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Jun 2018 09:12:15 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de, linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com Cc: Manivannan Sadhasivam Subject: [PATCH 1/5] dt-bindings: i2c: Add binding for Actions Semi OWL I2C controller Date: Sat, 23 Jun 2018 21:41:43 +0530 Message-Id: <20180623161147.15672-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> References: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add devicetree binding for Actions Semi OWL I2C controller Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/i2c/i2c-owl.txt | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.txt b/Documentation/devicetree/bindings/i2c/i2c-owl.txt new file mode 100644 index 000000000000..9b691968cffd --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-owl.txt @@ -0,0 +1,27 @@ +OWL I2C controller + +Required properties: + +- compatible : Should be "actions,s900-i2c". +- reg : Offset and length of the register set for the device. +- #address-cells : Should be 1. +- #size-cells : Should be 0. +- interrupts : A single interrupt specifier. +- clocks : Phandle of the clock feeding the I2C controller. + +Optional properties: + +- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and + Fast modes are supported, possible values are 100000 and + 400000. +Examples: + + i2c0: i2c@e0170000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0170000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clock CLK_I2C0>; + clock-frequency = <100000>; + }; From patchwork Sat Jun 23 16:11:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 933741 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="J3NcSQ13"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41CgTf5Hnfz9s31 for ; Sun, 24 Jun 2018 02:13:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751901AbeFWQM3 (ORCPT ); Sat, 23 Jun 2018 12:12:29 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:46527 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751889AbeFWQM0 (ORCPT ); Sat, 23 Jun 2018 12:12:26 -0400 Received: by mail-pg0-f67.google.com with SMTP id q14-v6so484098pgt.13 for ; Sat, 23 Jun 2018 09:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lyThY3JcGjNBnO+ReNP/irIxhSH65Nk/lsrkpXUda8k=; b=J3NcSQ13CsjEhPkpQtNTYTXecfElcolZMxEiZwhoaHpSK+p9tosk/VE38YhYs3bB/p JL3D1KyLAiXXjIBsu+7n1ymffiv2fQyLXvyZcIcd5CMbKEUFJrj2aSSWRqJHamrN0xDS llVx5tcpjIqNY0OC15oztBQly07Y+WfOBIwHw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lyThY3JcGjNBnO+ReNP/irIxhSH65Nk/lsrkpXUda8k=; b=flDJ6c2lNTn1NDQiy4CjCv7pY0urpJur08c9KEz66CBCP7LUPuoRgNH/Sq88TrUpLU 97iMPhYeOhfCfh3alL+K6QSJwLexqW+DGxfIoT2Cd5qNh7iiBTP0zNEb6xrmDtFw1+ik /W1+PQaLJI3ydunj/m2i7vH7de106DV3xgfAOHVAtzxZHHq2Srw6wYwJeJ92vmf170p4 r3m3KwTFDx8OAU2WwXHstOt3wR9xs6jTlbK2OCGx2n2zsC0NRWd5QT6Zn+6O3s9UcZrI HXsKIrtvyScfZJ+BomK0d4zS6+OOOZrnk8ZlxlAuuqN4Ap2HA4AhNIxnpqX7I9814BEO 0ZZw== X-Gm-Message-State: APt69E2iMomb5lSrk+lYMF3QTSCdJ9BzDr3x3N/RTBYYS+M5tmIC1Nk/ /qsmU4r7pNF2uDCpu1RJnZKd X-Google-Smtp-Source: ADUXVKIfFMuYWTIOv3872qrsjyFtDblvcaOiLC78ahFY7lzjIBqJui+z/L4hnqFzUurKwwxTQuXuhA== X-Received: by 2002:a65:6157:: with SMTP id o23-v6mr5355998pgv.310.1529770345519; Sat, 23 Jun 2018 09:12:25 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:100:fa16:6549:5166:32c7:2dab]) by smtp.gmail.com with ESMTPSA id n26-v6sm2732745pfi.168.2018.06.23.09.12.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Jun 2018 09:12:25 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de, linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com Cc: Manivannan Sadhasivam Subject: [PATCH 2/5] arm64: dts: actions: Add Actions Semi S900 I2C controller nodes Date: Sat, 23 Jun 2018 21:41:44 +0530 Message-Id: <20180623161147.15672-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> References: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add I2C controller nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 7ae8b931f000..6f7b89edbe4d 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -174,6 +174,66 @@ #clock-cells = <1>; }; + i2c0: i2c@e0170000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0170000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + }; + + i2c1: i2c@e0172000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0172000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + }; + + i2c2: i2c@e0174000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0174000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default>; + }; + + i2c3: i2c@e0176000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0176000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e0178000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0178000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e017a000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe017a000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl@e01b0000 { compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; From patchwork Sat Jun 23 16:11:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 933735 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sat, 23 Jun 2018 09:12:35 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:100:fa16:6549:5166:32c7:2dab]) by smtp.gmail.com with ESMTPSA id n26-v6sm2732745pfi.168.2018.06.23.09.12.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Jun 2018 09:12:35 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de, linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com Cc: Manivannan Sadhasivam Subject: [PATCH 3/5] arm64: dts: actions: Add pinctrl definition for S900 I2C controller Date: Sat, 23 Jun 2018 21:41:45 +0530 Message-Id: <20180623161147.15672-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> References: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinctrl definition for Actions Semi S900 I2C controller. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Signed-off-by: Manivannan Sadhasivam --- .../dts/actions/s900-bubblegum-96-pins.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi new file mode 100644 index 000000000000..e46ae187b27e --- /dev/null +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pinctrl { + + i2c0_default: i2c0_default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; +}; From patchwork Sat Jun 23 16:11:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 933736 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="js7+/iSs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41CgSx1fHzz9s2L for ; Sun, 24 Jun 2018 02:12:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751984AbeFWQMr (ORCPT ); Sat, 23 Jun 2018 12:12:47 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:46182 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751976AbeFWQMp (ORCPT ); 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Sat, 23 Jun 2018 09:12:44 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:100:fa16:6549:5166:32c7:2dab]) by smtp.gmail.com with ESMTPSA id n26-v6sm2732745pfi.168.2018.06.23.09.12.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Jun 2018 09:12:44 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de, linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com Cc: Manivannan Sadhasivam Subject: [PATCH 4/5] arm64: dts: actions: Enable I2C1 and I2C2 in Bubblegum-96 board Date: Sat, 23 Jun 2018 21:41:46 +0530 Message-Id: <20180623161147.15672-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> References: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Enable I2C1 and I2C2 exposed on the low speed expansion connector in Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index d0ba35df9015..57ae374cfb5a 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s900.dtsi" +#include "s900-bubblegum-96-pins.dtsi" / { compatible = "ucrobotics,bubblegum-96", "actions,s900"; @@ -35,6 +36,16 @@ clocks = <&cmu CLK_UART5>; }; +&i2c1 { + status = "okay"; + clocks = <&cmu CLK_I2C1>; +}; + +&i2c2 { + status = "okay"; + clocks = <&cmu CLK_I2C2>; +}; + /* * GPIO name legend: proper name = the GPIO line is used as GPIO * NC = not connected (pin out but not routed from the chip to From patchwork Sat Jun 23 16:11:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 933737 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="axDfHQnF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41CgTB02ljz9s2L for ; Sun, 24 Jun 2018 02:13:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752027AbeFWQM7 (ORCPT ); Sat, 23 Jun 2018 12:12:59 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:39002 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752025AbeFWQM5 (ORCPT ); Sat, 23 Jun 2018 12:12:57 -0400 Received: by mail-pl0-f65.google.com with SMTP id s24-v6so4855294plq.6 for ; Sat, 23 Jun 2018 09:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P/N1fV5FLgJcRyIRACOx2Le/5TZoFex1FDrd9foXQDg=; b=axDfHQnFeLOWODUBuooRlWwypzwUceLKILG4z1pVAQGibLe+GNNcyk7UYWyHzQ6gUW Z+9jwV2EnQDe0eXXxv1UcjOM2XH0C8CTYmIMCgxyCO3Bwq8UoiviMU63HJrKUWKYa3EC 8sCSvMHWRjJGKtwkULG48DMgKoNc+4k/AUdzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P/N1fV5FLgJcRyIRACOx2Le/5TZoFex1FDrd9foXQDg=; b=jmbgjMlEBIhxEsJbaEOuN2smNMHWGqrYlJa85if5Joa3frJaQkrYK0sAm5/dLLjOkE S41w+gL+AopVFhwKClWQYQfO2OTbunORiy15zeDeC6ApTNjwWm+TxyxLs9P9go+oBFbv b2vwR3C0+euKsg+CvThmeoSHNAdZZeAnCxpR7Y0CjmlSQVNaSEeRuxQnqjZhwN8p148S isx6Zz9mi9j9M+iPE9yPJWSGk2Ogk+8s6IHwQInwTNOP8qJxmxJbCk7fi1rXOE+rEUIo hgN1Oi/PiiMjnHzJ3kLlH1xZGVC1bCroWp5oUhkaXY0vZX1AYY28tYrryC6EB3/aJ+3s U0kQ== X-Gm-Message-State: APt69E3I7Pj5gACPokkj8oubhc3mgN1dDN7I4u7QkFwImYDy62AEleGh 13+lmERHmsYauPd4+gq2PQQh X-Google-Smtp-Source: ADUXVKJ5t2tSj1SUeDgkU/U8ktLbPRFMa48gFyNSFo3/NuOoQu4KFPy06Y+w8pdG1Uq3Zb4z1T5YIg== X-Received: by 2002:a17:902:b693:: with SMTP id c19-v6mr6170004pls.165.1529770376589; Sat, 23 Jun 2018 09:12:56 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:100:fa16:6549:5166:32c7:2dab]) by smtp.gmail.com with ESMTPSA id n26-v6sm2732745pfi.168.2018.06.23.09.12.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Jun 2018 09:12:56 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de, linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com Cc: Manivannan Sadhasivam Subject: [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver Date: Sat, 23 Jun 2018 21:41:47 +0530 Message-Id: <20180623161147.15672-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> References: <20180623161147.15672-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add Actions Semi OWL family S900 I2C driver. Signed-off-by: Manivannan Sadhasivam --- drivers/i2c/busses/Kconfig | 7 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++ 3 files changed, 467 insertions(+) create mode 100644 drivers/i2c/busses/i2c-owl.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 4f8df2ec87b1..2062da17e33b 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -762,6 +762,13 @@ config I2C_OMAP Like OMAP1510/1610/1710/5912 and OMAP242x. For details see http://www.ti.com/omap. +config I2C_OWL + tristate "OWL I2C Controller" + depends on ARCH_ACTIONS || COMPILE_TEST + help + Say Y here if you want to use the I2C bus controller on + the Actions Semi OWL SoCs. + config I2C_PASEMI tristate "PA Semi SMBus interface" depends on PPC_PASEMI && PCI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 5a869144a0c5..b71618f77880 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o +obj-$(CONFIG_I2C_OWL) += i2c-owl.o obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c new file mode 100644 index 000000000000..53100ddfb3cc --- /dev/null +++ b/drivers/i2c/busses/i2c-owl.c @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OWL SoC's I2C driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +/* I2C registers */ +#define OWL_I2C_REG_CTL (0x0000) +#define OWL_I2C_REG_CLKDIV (0x0004) +#define OWL_I2C_REG_STAT (0x0008) +#define OWL_I2C_REG_ADDR (0x000C) +#define OWL_I2C_REG_TXDAT (0x0010) +#define OWL_I2C_REG_RXDAT (0x0014) +#define OWL_I2C_REG_CMD (0x0018) +#define OWL_I2C_REG_FIFOCTL (0x001C) +#define OWL_I2C_REG_FIFOSTAT (0x0020) +#define OWL_I2C_REG_DATCNT (0x0024) +#define OWL_I2C_REG_RCNT (0x0028) + +/* I2Cx_CTL Bit Mask */ +#define OWL_I2C_CTL_RB BIT(1) +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) +#define OWL_I2C_CTL_IRQE BIT(5) +#define OWL_I2C_CTL_EN BIT(7) +#define OWL_I2C_CTL_AE BIT(8) +#define OWL_I2C_CTL_SHSM BIT(10) + +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) + +/* I2Cx_STAT Bit Mask */ +#define OWL_I2C_STAT_RACK BIT(0) +#define OWL_I2C_STAT_BEB BIT(1) +#define OWL_I2C_STAT_IRQP BIT(2) +#define OWL_I2C_STAT_LAB BIT(3) +#define OWL_I2C_STAT_STPD BIT(4) +#define OWL_I2C_STAT_STAD BIT(5) +#define OWL_I2C_STAT_BBB BIT(6) +#define OWL_I2C_STAT_TCB BIT(7) +#define OWL_I2C_STAT_LBST BIT(8) +#define OWL_I2C_STAT_SAMB BIT(9) +#define OWL_I2C_STAT_SRGC BIT(10) + +/* I2Cx_CMD Bit Mask */ +#define OWL_I2C_CMD_SBE BIT(0) +#define OWL_I2C_CMD_RBE BIT(4) +#define OWL_I2C_CMD_DE BIT(8) +#define OWL_I2C_CMD_NS BIT(9) +#define OWL_I2C_CMD_SE BIT(10) +#define OWL_I2C_CMD_MSS BIT(11) +#define OWL_I2C_CMD_WRS BIT(12) +#define OWL_I2C_CMD_SECL BIT(15) + +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) + +/* I2Cx_FIFOCTL Bit Mask */ +#define OWL_I2C_FIFOCTL_NIB BIT(0) +#define OWL_I2C_FIFOCTL_RFR BIT(1) +#define OWL_I2C_FIFOCTL_TFR BIT(2) + +/* I2Cc_FIFOSTAT Bit Mask */ +#define OWL_I2C_FIFOSTAT_RNB BIT(1) +#define OWL_I2C_FIFOSTAT_RFE BIT(2) +#define OWL_I2C_FIFOSTAT_TFF BIT(5) +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) + +/* I2C bus timeout */ +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000)) + +#define OWL_I2C_DEFAULT_SPEED 100000 +#define OWL_I2C_MAX_SPEED 400000 + +struct owl_i2c_dev { + struct i2c_adapter adap; + struct i2c_msg *msg; + struct completion msg_complete; + struct clk *clk; + void __iomem *base; + unsigned long clk_rate; + u32 bus_freq; + u32 msg_ptr; +}; + +static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state) +{ + unsigned int regval; + + regval = readl(base); + + if (state) + regval |= val; + else + regval &= ~val; + + writel(regval, base); +} + +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val; + + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + mdelay(1); + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, true); + + /* Reset FIFO */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, + true); + + /* Wait until FIFO reset complete */ + do { + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) + break; + } while (1); + + /* Clear status registers */ + writel(0, i2c_dev->base + OWL_I2C_REG_STAT); +} + +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val; + + val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) / + (i2c_dev->bus_freq * 16); + + /* Set clock divider factor */ + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); +} + +static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev) +{ + /* Reset I2C controller */ + owl_i2c_reset(i2c_dev); + + /* Set bus frequency */ + owl_i2c_set_freq(i2c_dev); +} + +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) +{ + struct owl_i2c_dev *i2c_dev = _dev; + struct i2c_msg *msg = i2c_dev->msg; + unsigned int stat, fifostat; + + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); + if (fifostat & OWL_I2C_FIFOSTAT_RNB) { + dev_warn(&i2c_dev->adap.dev, "received NACK from device"); + owl_i2c_reset(i2c_dev); + goto stop; + } + + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (stat & OWL_I2C_STAT_BEB) { + dev_warn(&i2c_dev->adap.dev, "bus error"); + owl_i2c_reset(i2c_dev); + goto stop; + } + + /* Handle FIFO read */ + if (msg->flags & I2C_M_RD) { + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_RFE) && + (i2c_dev->msg_ptr < msg->len)) { + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + + OWL_I2C_REG_RXDAT); + } + } else { + /* Handle the remaining bytes which were not sent */ + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_TFF) && + i2c_dev->msg_ptr < msg->len) { + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base + + OWL_I2C_REG_TXDAT); + } + } + +stop: + /* Clear pending interrupts */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, + OWL_I2C_STAT_IRQP, true); + + complete_all(&i2c_dev->msg_complete); + + return IRQ_HANDLED; +} + +static u32 owl_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + unsigned long timeout; + unsigned int val; + + timeout = jiffies + OWL_I2C_TIMEOUT; + while (1) { + val = readl(i2c_dev->base + OWL_I2C_REG_STAT); + + /* Check for Arbitration lost */ + if (val & OWL_I2C_STAT_LAB) { + val &= ~OWL_I2C_STAT_LAB; + writel(val, i2c_dev->base + OWL_I2C_REG_STAT); + return -EAGAIN; + } + + /* Check for Bus busy */ + if (!(val & OWL_I2C_STAT_BBB)) + break; + + if (time_after(jiffies, timeout)) { + dev_err(&adap->dev, "Bus busy timeout"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + struct i2c_msg *msg; + unsigned long time_left; + unsigned int i2c_cmd; + unsigned int addr; + int ret = 0, idx; + + owl_i2c_hw_init(i2c_dev); + + ret = owl_i2c_check_bus_busy(adap); + if (ret) + return ret; + + reinit_completion(&i2c_dev->msg_complete); + + /* Enable I2C controller interrupt */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_IRQE, true); + + /* + * Select: FIFO enable, Master mode, Stop enable, Data count enable, + * Send start bit + */ + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE); + + addr = (msgs[0].addr & 0x7f) << 1; + + /* Handle repeated start condition */ + if (num > 1) { + /* Set internal address length and enable repeated start */ + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1) + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE); + + /* Write slave address */ + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + /* Write internal register address */ + for (idx = 0; idx < msgs[0].len; idx++) + writel(msgs[0].buf[idx], i2c_dev->base + + OWL_I2C_REG_TXDAT); + + msg = &msgs[1]; + } else { + /* Set address length */ + i2c_cmd |= OWL_I2C_CMD_AS(1); + msg = &msgs[0]; + } + + i2c_dev->msg = msg; + i2c_dev->msg_ptr = 0; + + /* Set data count for the message */ + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); + + if (msg->flags & I2C_M_RD) { + writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT); + } else { + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + /* Write data to FIFO */ + for (idx = 0; idx < msg->len; idx++) { + /* Check for FIFO full */ + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) + & OWL_I2C_FIFOSTAT_TFF) + break; + + writel(msg->buf[idx], + i2c_dev->base + OWL_I2C_REG_TXDAT); + } + + i2c_dev->msg_ptr = idx; + } + + /* Ingore the NACK if needed */ + if (msg->flags & I2C_M_IGNORE_NAK) + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, true); + else + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, false); + + /* Start the transfer */ + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); + + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, + adap->timeout); + if (time_left == 0) { + dev_err(&adap->dev, "Transaction timed out"); + /* Send stop condition and release the bus */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true); + ret = -ETIMEDOUT; + } + + /* Disable I2C controller */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + + return i2c_dev->msg_ptr; +} + +static const struct i2c_algorithm owl_i2c_algorithm = { + .master_xfer = owl_i2c_master_xfer, + .functionality = owl_i2c_func +}; + +static const struct i2c_adapter_quirks owl_i2c_quirks = { + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, + .max_read_len = 240, + .max_write_len = 240, + .max_comb_1st_msg_len = 6, + .max_comb_2nd_msg_len = 240 +}; + +static int owl_i2c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct owl_i2c_dev *i2c_dev; + struct resource *res; + int ret, irq; + + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get IRQ number\n"); + return irq; + } + + if (of_property_read_u32(dev->of_node, "clock-frequency", + &i2c_dev->bus_freq)) + i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED; + + /* We support only frequencies of 100k and 400k for now */ + if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED && + i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) { + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); + return -EINVAL; + } + + i2c_dev->clk = devm_clk_get(dev, NULL); + if (IS_ERR(i2c_dev->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(i2c_dev->clk); + } + + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) + return ret; + + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); + if (!i2c_dev->clk_rate) { + dev_err(dev, "input clock rate should not be zero\n"); + ret = -EINVAL; + goto disable_clk; + } + + init_completion(&i2c_dev->msg_complete); + i2c_dev->adap.owner = THIS_MODULE; + i2c_dev->adap.algo = &owl_i2c_algorithm; + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; + i2c_dev->adap.quirks = &owl_i2c_quirks; + i2c_dev->adap.dev.parent = dev; + i2c_dev->adap.dev.of_node = dev->of_node; + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), + "%s", "OWL I2C adapter"); + i2c_set_adapdata(&i2c_dev->adap, i2c_dev); + + platform_set_drvdata(pdev, i2c_dev); + + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, + i2c_dev); + if (ret) { + dev_err(dev, "failed to request irq %d\n", irq); + goto disable_clk; + } + + ret = i2c_add_adapter(&i2c_dev->adap); +disable_clk: + if (ret) + clk_disable_unprepare(i2c_dev->clk); + + return ret; +} + +static const struct of_device_id owl_i2c_of_match[] = { + {.compatible = "actions,s900-i2c"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, owl_i2c_of_match); + +static struct platform_driver owl_i2c_driver = { + .probe = owl_i2c_probe, + .driver = { + .name = "owl-i2c", + .of_match_table = of_match_ptr(owl_i2c_of_match), + }, +}; +module_platform_driver(owl_i2c_driver); + +MODULE_AUTHOR("David Liu "); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver"); +MODULE_LICENSE("GPL");