From patchwork Tue Jun 12 09:13:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zihan Yang X-Patchwork-Id: 928196 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hKyleO03"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 414kjr1cVrz9s1B for ; Tue, 12 Jun 2018 19:14:56 +1000 (AEST) Received: from localhost ([::1]:53994 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSfO9-000552-Te for incoming@patchwork.ozlabs.org; Tue, 12 Jun 2018 05:14:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58920) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSfN2-0004YM-Qw for qemu-devel@nongnu.org; Tue, 12 Jun 2018 05:13:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSfMz-0006ey-IF for qemu-devel@nongnu.org; Tue, 12 Jun 2018 05:13:44 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:42186) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fSfMz-0006ee-9W for qemu-devel@nongnu.org; Tue, 12 Jun 2018 05:13:41 -0400 Received: by mail-pf0-x242.google.com with SMTP id w7-v6so11754865pfn.9 for ; Tue, 12 Jun 2018 02:13:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=usTDF2/Hfaq2noZZzk2nLWRb6W38UghISDXu3CRG5l0=; b=hKyleO03JCvEm/uxAI6fgS1blnJ2Lubw3ty19IsGIeMF9NDtvkzwvCVqp1PkGDd6GY eeMlpRFR6ahNpAKeiIhg7j8TayFXYWbA4+yOpo1dV8GGYZ3AySM59Fo0EIA+AalRDW31 hMgq73uCFHddwC73NKhADVS6vlj9NQ99FTT9gS9vcxjl0AmSpFhxyiDTKjLknoqou3qe ajtDMBB18Yk3/hO2Np3an7QT8/QClZi9VXLto9l0YW6uqw0mpNjBE5ho7H3UrhVyCxyh HKDo1IhGOIFWLldBVh/OXVkaQqx7MQbrJeYOx2b3jNsU6KEUulvDMuyopudW4KX3/DkB 7Sdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=usTDF2/Hfaq2noZZzk2nLWRb6W38UghISDXu3CRG5l0=; b=a0YoPZMQZzJKibr05d2KXZ7yyq/UFGQv6wevdb8RN5CrHHfP93JWVl+5KNi5tWXQcm +27lOxoTfl7WJc/+CagK3EfRXLxrwBJ+M+no+3L3XK/UN2sFxTysrgKeV5Pf3N9Q52PD QB+7Q1pV859vggb8Ob+QF7h67pIVNMbvxLOcErOmRj16Sv3MZ1p6S0h3DNgfOaosczi3 GX8F6mBFmBFfw7j/tDC6Jg9P42Dhjn+UtTUoQlW5NNkL2Q5Xr7mozxXa28C7MeESaMdd 9i0DoGea+OYUXfzrCMSQE9U4FzJmO/y7Ro5UI+3lrQsTuqL7G2Yt93Pe/SvfzpmrCKdo wd9w== X-Gm-Message-State: APt69E15i4GrvBlMMYMvHLiBjwhT2VNyi9wAw+4sBMKL0qqvE63b0czD Ra9Qpzjxm+RkgRIYDHFKCj0kxQ== X-Google-Smtp-Source: ADUXVKIFMkaVRUA2wQxcM2tk0CgEc8/2vy0jsUi9y4EldhLd/tBHSTY1PJwpafwyhGFWxWxOlSu7ug== X-Received: by 2002:a62:c4dd:: with SMTP id h90-v6mr3035098pfk.86.1528794820077; Tue, 12 Jun 2018 02:13:40 -0700 (PDT) Received: from localhost.localdomain ([141.101.152.11]) by smtp.gmail.com with ESMTPSA id w11-v6sm1053676pfn.71.2018.06.12.02.13.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jun 2018 02:13:38 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Tue, 12 Jun 2018 17:13:22 +0800 Message-Id: <1528794804-6289-1-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [RFC v2 1/3] pci_expander_bridge: add type TYPE_PXB_PCIE_HOST X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default, add a new type TYPE_PXB_PCIE_HOST to better utilize the ECAM of PCIe Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 118 ++++++++++++++++++++++++++++++++++-- 1 file changed, 114 insertions(+), 4 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index e62de42..448b9fb 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -15,10 +15,12 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_host.h" #include "hw/pci/pci_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "sysemu/numa.h" +#include "qapi/visitor.h" #define TYPE_PXB_BUS "pxb-bus" #define PXB_BUS(obj) OBJECT_CHECK(PXBBus, (obj), TYPE_PXB_BUS) @@ -45,7 +47,10 @@ typedef struct PXBDev { PCIDevice parent_obj; /*< public >*/ - uint8_t bus_nr; + bool sep_domain; /* whether it resides in separate PCI segment */ + uint32_t domain_nr; /* PCI domain(segment) number, should be 0 if sep_domain is false */ + uint8_t max_bus; /* max number of buses to use */ + uint8_t bus_nr; /* should be 0 when in separate domain */ uint16_t numa_node; } PXBDev; @@ -58,6 +63,18 @@ static PXBDev *convert_to_pxb(PCIDevice *dev) static GList *pxb_dev_list; #define TYPE_PXB_HOST "pxb-host" +#define TYPE_PXB_PCIE_HOST "pxb-pcie-host" +#define PXB_PCIE_HOST_DEVICE(obj) \ + OBJECT_CHECK(PXBPCIEHost, (obj), TYPE_PXB_PCIE_HOST) + +typedef struct PXBPCIEHost { + PCIExpressHost parent_obj; + + /* should only inherit from PXBDev */ + uint32_t domain_nr; + uint8_t bus_nr; + uint8_t max_bus; +} PXBPCIEHost; static int pxb_bus_num(PCIBus *bus) { @@ -111,6 +128,31 @@ static const char *pxb_host_root_bus_path(PCIHostState *host_bridge, return bus->bus_path; } +/* Use a dedicated function for PCIe since pxb-host does + * not have a domain_nr field */ +static const char *pxb_pcie_host_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + if (!pci_bus_is_express(rootbus)) { + /* pxb-pcie-host cannot reside on a PCI bus */ + return NULL; + } + PXBBus *bus = PXB_PCIE_BUS(rootbus); + + snprintf(bus->bus_path, 8, "%04lx:%02x", + object_property_get_uint((Object *)host_bridge, "domain_nr", NULL), + pxb_bus_num(rootbus)); + return bus->bus_path; +} + +static void pxb_pcie_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); + + visit_type_uint64(v, name, &e->size, errp); +} + static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) { const PCIHostState *pxb_host; @@ -142,6 +184,30 @@ static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) return NULL; } +static void pxb_pcie_host_initfn(Object *obj) +{ + PCIHostState *phb = PCI_HOST_BRIDGE(obj); + + memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, + "pci-conf-idx", 4); + memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, + "pci-conf-data", 4); + + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", + pxb_pcie_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); + +} + +static Property pxb_pcie_host_props[] = { + DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, PXBPCIEHost, parent_obj.base_addr, + PCIE_BASE_ADDR_UNMAPPED), + DEFINE_PROP_UINT32("domain_nr", PXBPCIEHost, domain_nr, 0), + DEFINE_PROP_UINT8("bus_nr", PXBPCIEHost, bus_nr, 0), + DEFINE_PROP_UINT8("max_bus", PXBPCIEHost, max_bus, 255), + DEFINE_PROP_END_OF_LIST(), +}; + static void pxb_host_class_init(ObjectClass *class, void *data) { DeviceClass *dc = DEVICE_CLASS(class); @@ -155,12 +221,34 @@ static void pxb_host_class_init(ObjectClass *class, void *data) hc->root_bus_path = pxb_host_root_bus_path; } +static void pxb_pcie_host_class_init(ObjectClass *class, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(class); + SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(class); + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class); + + dc->fw_name = "pci"; + dc->props = pxb_pcie_host_props; + /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ + dc->user_creatable = false; + sbc->explicit_ofw_unit_address = pxb_host_ofw_unit_address; + hc->root_bus_path = pxb_pcie_host_root_bus_path; +} + static const TypeInfo pxb_host_info = { .name = TYPE_PXB_HOST, .parent = TYPE_PCI_HOST_BRIDGE, .class_init = pxb_host_class_init, }; +static const TypeInfo pxb_pcie_host_info = { + .name = TYPE_PXB_PCIE_HOST, + .parent = TYPE_PCIE_HOST_BRIDGE, + .instance_size = sizeof(PXBPCIEHost), + .instance_init = pxb_pcie_host_initfn, + .class_init = pxb_pcie_host_class_init, +}; + /* * Registers the PXB bus as a child of pci host root bus. */ @@ -205,7 +293,10 @@ static gint pxb_compare(gconstpointer a, gconstpointer b) { const PXBDev *pxb_a = a, *pxb_b = b; - return pxb_a->bus_nr < pxb_b->bus_nr ? -1 : + /* check domain_nr, then bus_nr */ + return pxb_a->domain_nr < pxb_b->domain_nr ? -1 : + pxb_a->domain_nr > pxb_b->domain_nr ? 1 : + pxb_a->bus_nr < pxb_b->bus_nr ? -1 : pxb_a->bus_nr > pxb_b->bus_nr ? 1 : 0; } @@ -228,10 +319,17 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool pcie, Error **errp) dev_name = dev->qdev.id; } - ds = qdev_create(NULL, TYPE_PXB_HOST); if (pcie) { + /* either in sep_domain or stay in domain 0 */ + g_assert (pxb->sep_domain || pxb->domain_nr == 0); + g_assert (pxb->max_bus >= pxb->bus_nr); + ds = qdev_create(NULL, TYPE_PXB_PCIE_HOST); + qdev_prop_set_uint8(ds, "bus_nr", pxb->bus_nr); //TODO. + qdev_prop_set_uint8(ds, "max_bus", pxb->max_bus); + qdev_prop_set_uint8(ds, "domain_nr", pxb->domain_nr); bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); } else { + ds = qdev_create(NULL, TYPE_PXB_HOST); bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS); bds = qdev_create(BUS(bus), "pci-bridge"); bds->id = dev_name; @@ -294,6 +392,17 @@ static Property pxb_dev_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property pxb_pcie_dev_properties[] = { + /* Note: 0 is not a legal PXB bus number. */ + DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), + DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED), + DEFINE_PROP_BOOL("sep_domain", PXBDev, sep_domain, false), + DEFINE_PROP_UINT32("domain_nr", PXBDev, domain_nr, 0), + DEFINE_PROP_UINT8("max_bus", PXBDev, max_bus, 255), + + DEFINE_PROP_END_OF_LIST(), +}; + static void pxb_dev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -344,7 +453,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "PCI Express Expander Bridge"; - dc->props = pxb_dev_properties; + dc->props = pxb_pcie_dev_properties; dc->hotpluggable = false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -365,6 +474,7 @@ static void pxb_register_types(void) type_register_static(&pxb_bus_info); type_register_static(&pxb_pcie_bus_info); type_register_static(&pxb_host_info); + type_register_static(&pxb_pcie_host_info); type_register_static(&pxb_dev_info); type_register_static(&pxb_pcie_dev_info); } From patchwork Tue Jun 12 09:13:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zihan Yang X-Patchwork-Id: 928197 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WykN5qWQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 414klQ3Wdxz9s1B for ; Tue, 12 Jun 2018 19:16:18 +1000 (AEST) Received: from localhost ([::1]:54003 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSfPU-0005tT-6Y for incoming@patchwork.ozlabs.org; Tue, 12 Jun 2018 05:16:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSfND-0004gc-0h for qemu-devel@nongnu.org; Tue, 12 Jun 2018 05:13:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSfN9-0006in-OD for qemu-devel@nongnu.org; Tue, 12 Jun 2018 05:13:54 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:35243) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fSfN9-0006i7-Fc for qemu-devel@nongnu.org; Tue, 12 Jun 2018 05:13:51 -0400 Received: by mail-pl0-x241.google.com with SMTP id k1-v6so5604809plt.2 for ; Tue, 12 Jun 2018 02:13:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5ruNxPRXdcNUcw1hwtBupfkiFQfZSJiJzpIvsdyJ7dE=; b=WykN5qWQGM0Fr6rd4ReLCQdm4hbaH3+edECxNCFWcS9HILPjL7tGcy3OLeOc7UgBPx X6fLWTi2dDzDrZb512ocHP2m4/ouygVcp/HmESRiXcjXUXSlLcdZOiVBosstZO8g6tQO MRhU71fWpNnteHYPurEOEVG9p8m6SjbzrpFsL2yRMnfXdVDgj6KHdJBmP+odXi0kR7Nf H5bpeuUGsqVcoe4wySQ7xTjTpHq2fGIg+/7MIWMY0q3ujeoIW6bb3wbbAvx2P7JmjlfR 8q/3n1GqH7iolaI57049fLxMgX24CsRiQI2m0TqDrjvQ02y03/x0lL0QooK6p2qKoKh8 ljYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5ruNxPRXdcNUcw1hwtBupfkiFQfZSJiJzpIvsdyJ7dE=; b=VhiapRqRsuqMv4NqraoXcAyJtV1YWz9cZiX8U6G6KXMbjpTwYpVBPlJAOzeB+9Liyg 1Xdq4ehRONGgS0S78UgO5+84bXf4d3jdx/a81HJ2LzOwI3xuxoUGA+QeGAyC8slQp781 jX/CXvNeZti3n5h5pNmztIyYL1dfs+waaAZ4JwHEDsUWFyOz3TaFlpDwisxxdvN+RHPP iIbbS3aVNvHoMRO+YSJqfgdHCJo07+EuiXiwHIehdLRubgkrgP2O7YA8ksfwuwHNoS9S oIlznuEj0mio5TtOgDRZEskbBlqNaiDuqtoE/5fNMR9UCSkm6MG0aRd46Zm/VyyFp8E3 5XBQ== X-Gm-Message-State: APt69E2m++CMCbCqIdUrqwnEVQZaH3o7YbSFbLqhmyFauXjZknuBq5/x h4eIxahblpoR8E0jZKMBXrSwsA== X-Google-Smtp-Source: ADUXVKJsfdkgCRgnJTOVmx7xoZR2qSuF/JpIpZb9QNJKjXxi4QX1IV/VgHPVZa35hk3SU70iQOUQUw== X-Received: by 2002:a17:902:7896:: with SMTP id q22-v6mr3052805pll.243.1528794830369; Tue, 12 Jun 2018 02:13:50 -0700 (PDT) Received: from localhost.localdomain ([141.101.152.11]) by smtp.gmail.com with ESMTPSA id w11-v6sm1053676pfn.71.2018.06.12.02.13.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jun 2018 02:13:49 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Tue, 12 Jun 2018 17:13:24 +0800 Message-Id: <1528794804-6289-3-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528794804-6289-1-git-send-email-whois.zihan.yang@gmail.com> References: <1528794804-6289-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [RFC v2 3/3] acpi-build: describe new pci domain in AML X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Zihan Yang , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Describe new pci segments of host bridges in AML. The host bridge list is replaced by QTAILQ to let q35 host be processed first in every traverse Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 69 ++++++++++++++++++++++++++++++----------------- hw/pci/pci.c | 9 ++++--- include/hw/pci/pci_host.h | 2 +- 3 files changed, 50 insertions(+), 30 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 104e52d..a9f1503 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2123,36 +2123,55 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, sb_scope = aml_scope("\\_SB"); { Object *pci_host; + QObject *o; PCIBus *bus = NULL; + uint32_t domain_nr; + bool q35host = true; pci_host = acpi_get_i386_pci_host(); - if (pci_host) { + while (pci_host) { + o = object_property_get_qobject(pci_host, "domain_nr", NULL); + assert(o); + domain_nr = qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + /* skip expander bridges that still reside in domain 0 */ + if (!q35host && domain_nr == 0) { + pci_host = OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); + continue; + } bus = PCI_HOST_BRIDGE(pci_host)->bus; - } - if (bus) { - Aml *scope = aml_scope("PCI0"); - /* Scan all PCI buses. Generate tables to support hotplug. */ - build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); + if (bus) { + Aml *scope = aml_scope("PCI0"); + aml_append(scope, aml_name_decl("_SEG", aml_int(domain_nr))); + /* For simplicity, base bus number starts from 0 */ + aml_append(scope, aml_name_decl("_BBN", aml_int(0))); + /* Scan all PCI buses. Generate tables to support hotplug. */ + build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); - if (TPM_IS_TIS(tpm_find())) { - dev = aml_device("ISA.TPM"); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); - aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); - crs = aml_resource_template(); - aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, - TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); - /* - FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, - Rewrite to take IRQ from TPM device model and - fix default IRQ value there to use some unused IRQ - */ - /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); + if (TPM_IS_TIS(tpm_find())) { + dev = aml_device("ISA.TPM"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, + TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); + /* + FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, + Rewrite to take IRQ from TPM device model and + fix default IRQ value there to use some unused IRQ + */ + /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + } + + aml_append(sb_scope, scope); } - - aml_append(sb_scope, scope); + /* q35 host is the first one in the tail queue */ + q35host = false; + pci_host = OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); } } @@ -2645,7 +2664,7 @@ static AcpiMcfgInfo *acpi_get_mcfg(void) qobject_unref(o); /* skip q35 host and bridges that reside in the same domain with it */ if (domain_nr == 0) { - pci_host = OBJECT(QLIST_NEXT(PCI_HOST_BRIDGE(pci_host), next)); + pci_host = OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); continue; } @@ -2674,7 +2693,7 @@ static AcpiMcfgInfo *acpi_get_mcfg(void) assert(o); mcfg->domain_nr = qnum_get_uint(qobject_to(QNum, o)); - pci_host = OBJECT(QLIST_NEXT(PCI_HOST_BRIDGE(pci_host), next)); + pci_host = OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); } return head; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 80bc459..f63385f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -196,7 +196,8 @@ static void pci_del_option_rom(PCIDevice *pdev); static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; -static QLIST_HEAD(, PCIHostState) pci_host_bridges; +static QTAILQ_HEAD(, PCIHostState) pci_host_bridges = + QTAILQ_HEAD_INITIALIZER(pci_host_bridges); int pci_bar(PCIDevice *d, int reg) { @@ -330,7 +331,7 @@ static void pci_host_bus_register(DeviceState *host) { PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); - QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); + QTAILQ_INSERT_HEAD(&pci_host_bridges, host_bridge, next); } PCIBus *pci_device_root_bus(const PCIDevice *d) @@ -1798,7 +1799,7 @@ PciInfoList *qmp_query_pci(Error **errp) PciInfoList *info, *head = NULL, *cur_item = NULL; PCIHostState *host_bridge; - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { info = g_malloc0(sizeof(*info)); info->value = qmp_query_pci_bus(host_bridge->bus, pci_bus_num(host_bridge->bus)); @@ -2493,7 +2494,7 @@ int pci_qdev_find_device(const char *id, PCIDevice **pdev) PCIHostState *host_bridge; int rc = -ENODEV; - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); if (!tmp) { rc = 0; diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595..a5617cf 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -47,7 +47,7 @@ struct PCIHostState { uint32_t config_reg; PCIBus *bus; - QLIST_ENTRY(PCIHostState) next; + QTAILQ_ENTRY(PCIHostState) next; }; typedef struct PCIHostBridgeClass {