From patchwork Fri Jun 8 13:32:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcelo Henrique Cerri X-Patchwork-Id: 926792 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 412Ndh2jLJz9s4r; Fri, 8 Jun 2018 23:33:12 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1fRHVm-0003We-HM; Fri, 08 Jun 2018 13:33:02 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.86_2) (envelope-from ) id 1fRHVk-0003Vb-KE for kernel-team@lists.ubuntu.com; Fri, 08 Jun 2018 13:33:00 +0000 Received: from mail-qk0-f198.google.com ([209.85.220.198]) by youngberry.canonical.com with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.76) (envelope-from ) id 1fRHVk-0007Pj-9f for kernel-team@lists.ubuntu.com; Fri, 08 Jun 2018 13:33:00 +0000 Received: by mail-qk0-f198.google.com with SMTP id p85-v6so12737005qke.23 for ; Fri, 08 Jun 2018 06:33:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=gWk9FUP4iood3OUP9jFyLVZlqA73hW83I08kHqYYb7Q=; b=puSRDkdVt2xZBdOPUpd25+aj/8x6cenVlhWAM227di215947zeBDYqGIkzEAMNCr3u M+c/VfYPqQVfnxA2CxztSJlAj8I0jI8i+EABgPc9ExcxNl6zLXnQKR9FnBNYxhH11cOA H2xYS8VQ6JlBsJmIlbyPXznjVPkt+ndrhRpVxNGHXZDPWaEDdK1l6bH28JxvB65Qsrdv d7wXcxKaH0B4jxiJ1t77VrvtYAMAZN9XZpD/iH74TBIuH8AGWQpZ399N0JAN0Njl+5X6 c7fikrEB+pKWwQfIMP6veyRPfILaSaoM8r4GERiajNs5fBjdrIVWXAyCQPtEAq04bc1o H/gA== X-Gm-Message-State: APt69E33JeJd0ZJewPHNGzJmMwZ6Ieplv05+Ya5t05eZBMBVZ254o5JL sVWjyC951BwfF4rYSgg4QAGMq670yswLMva5zc+mXh7r+DBdNDC91ZtNCgYLKAgDqMH6O8ILr3i Et1JfhKu0SIujk8ucwk2TLhUGHRGykLti2jIBBedQ X-Received: by 2002:ac8:18e9:: with SMTP id o38-v6mr5789522qtk.202.1528464779002; Fri, 08 Jun 2018 06:32:59 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLZDiGzVfUSwaD8WAiqnkdFsMBat3yhJxj6Ar0+1mk/lv9Rx1ARVqO6g+WdBBdFdWbDL/nQPw== X-Received: by 2002:ac8:18e9:: with SMTP id o38-v6mr5789513qtk.202.1528464778795; Fri, 08 Jun 2018 06:32:58 -0700 (PDT) Received: from localhost.localdomain ([179.97.166.78]) by smtp.gmail.com with ESMTPSA id u25-v6sm32094207qkl.25.2018.06.08.06.32.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Jun 2018 06:32:57 -0700 (PDT) From: Marcelo Henrique Cerri To: kernel-team@lists.ubuntu.com Subject: [azure/bionic][PATCH 1/2] IB/mlx5: Enable ECN capable bits for UD RoCE v2 QPs Date: Fri, 8 Jun 2018 10:32:50 -0300 Message-Id: <20180608133251.29563-2-marcelo.cerri@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180608133251.29563-1-marcelo.cerri@canonical.com> References: <20180608133251.29563-1-marcelo.cerri@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Majd Dibbiny BugLink: http://bugs.launchpad.net/bugs/1762554 When working with RC QPs, the FW sets the ECN capable bits for all the RoCE v2 packets. On the other hand, for UD QPs, the driver needs to set the the ECN capable bits in the Address Handler since the HW generates each packet according to the Address Handler and not the QP context. If ECN is not enabled in NIC or switch, these bits are ignored. Fixes: 2811ba51b049 ("IB/mlx5: Add RoCE fields to Address Vector") Reviewed-by: Mark Bloch Signed-off-by: Majd Dibbiny Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe (cherry picked from commit ea8af0d2f2b5b16da4553205ddaf225e0a057e03) Signed-off-by: Marcelo Henrique Cerri --- drivers/infiniband/hw/mlx5/ah.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/infiniband/hw/mlx5/ah.c b/drivers/infiniband/hw/mlx5/ah.c index fe269f680103..e6bde32a83f3 100644 --- a/drivers/infiniband/hw/mlx5/ah.c +++ b/drivers/infiniband/hw/mlx5/ah.c @@ -36,6 +36,9 @@ static struct ib_ah *create_ib_ah(struct mlx5_ib_dev *dev, struct mlx5_ib_ah *ah, struct rdma_ah_attr *ah_attr) { + enum ib_gid_type gid_type; + int err; + if (rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) { const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); @@ -50,6 +53,12 @@ static struct ib_ah *create_ib_ah(struct mlx5_ib_dev *dev, ah->av.stat_rate_sl = (rdma_ah_get_static_rate(ah_attr) << 4); if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { + err = mlx5_get_roce_gid_type(dev, ah_attr->port_num, + ah_attr->grh.sgid_index, + &gid_type); + if (err) + return ERR_PTR(err); + memcpy(ah->av.rmac, ah_attr->roce.dmac, sizeof(ah_attr->roce.dmac)); ah->av.udp_sport = @@ -57,6 +66,9 @@ static struct ib_ah *create_ib_ah(struct mlx5_ib_dev *dev, rdma_ah_get_port_num(ah_attr), rdma_ah_read_grh(ah_attr)->sgid_index); ah->av.stat_rate_sl |= (rdma_ah_get_sl(ah_attr) & 0x7) << 1; + if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) +#define MLX5_ECN_ENABLED BIT(1) + ah->av.tclass |= MLX5_ECN_ENABLED; } else { ah->av.rlid = cpu_to_be16(rdma_ah_get_dlid(ah_attr)); ah->av.fl_mlid = rdma_ah_get_path_bits(ah_attr) & 0x7f;