From patchwork Wed Jun 6 09:18:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 925776 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="EilrHVYy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41135V6f06z9rxs for ; Wed, 6 Jun 2018 19:19:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932369AbeFFJTJ (ORCPT ); Wed, 6 Jun 2018 05:19:09 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:21719 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932352AbeFFJTI (ORCPT ); Wed, 6 Jun 2018 05:19:08 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w569J7PJ022824; Wed, 6 Jun 2018 04:19:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528276748; bh=mrypBNxAN3aWxT8DiNWzHnweLtZUgvaMtYrpEkzZii4=; h=From:To:CC:Subject:Date; b=EilrHVYyd65mvN6OH6fn4i/AAiuU1xLqw3o5+4v1Wp3qaFjxDDNxwrgleCfY0esSJ uA/wlBZfe0KUlvdLDxyy1cdev69Yrup9PGVOcKJ2dFoqJKhD9blTv8b++SRzKnvQ4I G52+CEQw5S/Cu6BCXAP0U+GH4I21SQ6BL7DtUm1M= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w569J7Xo027998; Wed, 6 Jun 2018 04:19:07 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 6 Jun 2018 04:19:07 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 6 Jun 2018 04:19:07 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w569J5c7017036; Wed, 6 Jun 2018 04:19:06 -0500 From: Keerthy To: CC: , , , Subject: [PATCH 1/2] gpio: davinci: Move fetching IRQ to beginning of probe Date: Wed, 6 Jun 2018 14:48:53 +0530 Message-ID: <1528276734-1483-1-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Currently IRQ resource fetching is done at the very end of probe. In case the of IRQ resource not being ready, we defer probe and need to revert prior changes. Hence move it to the beginning of the probe so as to avoid reverting. Signed-off-by: Keerthy --- Tested for GPIO Interrupts on da850-lcdk and keystone-k2g-evm boards. drivers/gpio/gpio-davinci.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 987126c..861f35b 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -55,7 +55,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) return g; } -static int davinci_gpio_irq_setup(struct platform_device *pdev); +static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq); /*--------------------------------------------------------------------------*/ @@ -168,7 +168,7 @@ static int davinci_gpio_probe(struct platform_device *pdev) { static int ctrl_num, bank_base; int gpio, bank, ret = 0; - unsigned ngpio, nbank; + unsigned int ngpio, nbank, bank_irq; struct davinci_gpio_controller *chips; struct davinci_gpio_platform_data *pdata; struct device *dev = &pdev->dev; @@ -209,6 +209,12 @@ static int davinci_gpio_probe(struct platform_device *pdev) if (IS_ERR(gpio_base)) return PTR_ERR(gpio_base); + bank_irq = platform_get_irq(pdev, 0); + if (bank_irq < 0) { + dev_dbg(dev, "IRQ not populated\n"); + return bank_irq; + } + snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++); chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL); if (!chips->chip.label) @@ -243,7 +249,7 @@ static int davinci_gpio_probe(struct platform_device *pdev) goto err; platform_set_drvdata(pdev, chips); - ret = davinci_gpio_irq_setup(pdev); + ret = davinci_gpio_irq_setup(pdev, bank_irq); if (ret) goto err; @@ -452,16 +458,15 @@ static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) * (dm6446) can be set appropriately for GPIOV33 pins. */ -static int davinci_gpio_irq_setup(struct platform_device *pdev) +static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) { unsigned gpio, bank; int irq; int ret; struct clk *clk; u32 binten = 0; - unsigned ngpio, bank_irq; + unsigned int ngpio; struct device *dev = &pdev->dev; - struct resource *res; struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); struct davinci_gpio_platform_data *pdata = dev->platform_data; struct davinci_gpio_regs __iomem *g; @@ -481,18 +486,6 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; ngpio = pdata->ngpio; - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_err(dev, "Invalid IRQ resource\n"); - return -EBUSY; - } - - bank_irq = res->start; - - if (!bank_irq) { - dev_err(dev, "Invalid IRQ resource\n"); - return -ENODEV; - } clk = devm_clk_get(dev, "gpio"); if (IS_ERR(clk)) { From patchwork Wed Jun 6 09:18:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 925777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="eHtKqsce"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41135n1R4Xz9rxs for ; Wed, 6 Jun 2018 19:19:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932529AbeFFJTN (ORCPT ); Wed, 6 Jun 2018 05:19:13 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:43185 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932499AbeFFJTK (ORCPT ); Wed, 6 Jun 2018 05:19:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w569J9C3013394; Wed, 6 Jun 2018 04:19:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528276749; bh=iU5WT95ItF9gJlr42kx5siZc95pOn28/RqT8Cora6M0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eHtKqscebWIb62sQmJa3v/E11W4igh4GMghwp/orQrItTWPRtrran1wsoJKN/qlAU 79J+hz4VR4sxGnY013CMXIiv6Mab2fAfwBsHJ3EG4dEfAXSsruPzQgENqReKsLc1TQ JzgJvfROj9VqisHIaFnyH6i+65sxD7q9s4ETLrcY= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w569J941023092; Wed, 6 Jun 2018 04:19:09 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 6 Jun 2018 04:19:09 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 6 Jun 2018 04:19:09 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w569J5c8017036; Wed, 6 Jun 2018 04:19:08 -0500 From: Keerthy To: CC: , , , Subject: [PATCH 2/2] gpio: davinci: Do not assume continuous IRQ numbering Date: Wed, 6 Jun 2018 14:48:54 +0530 Message-ID: <1528276734-1483-2-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1528276734-1483-1-git-send-email-j-keerthy@ti.com> References: <1528276734-1483-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Currently the driver assumes that the interrupts are continuous and does platform_get_irq only once and assumes the rest are continuous, instead call platform_get_irq for all the interrupts and store them in an array for later use. Signed-off-by: Keerthy --- Tested for GPIO Interrupts on da850-lcdk and keystone-k2g-evm boards. drivers/gpio/gpio-davinci.c | 49 ++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 861f35b..375578c 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -42,6 +42,7 @@ struct davinci_gpio_regs { #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ #define MAX_LABEL_SIZE 20 +#define MAX_INT_PER_BANK 32 static void __iomem *gpio_base; static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; @@ -55,7 +56,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) return g; } -static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq); +static int davinci_gpio_irq_setup(struct platform_device *pdev, int *bank_irq); /*--------------------------------------------------------------------------*/ @@ -168,7 +169,8 @@ static int davinci_gpio_probe(struct platform_device *pdev) { static int ctrl_num, bank_base; int gpio, bank, ret = 0; - unsigned ngpio, nbank, bank_irq; + unsigned int ngpio, nbank, nirq; + int bank_irq[MAX_INT_PER_BANK], i; struct davinci_gpio_controller *chips; struct davinci_gpio_platform_data *pdata; struct device *dev = &pdev->dev; @@ -197,6 +199,16 @@ static int davinci_gpio_probe(struct platform_device *pdev) if (WARN_ON(ARCH_NR_GPIOS < ngpio)) ngpio = ARCH_NR_GPIOS; + /* + * If there are unbanked interrupts then the number of + * interrupts is equal to number of gpios else all are banked so + * number of interrupts is equal to number of banks(each with 16 gpios) + */ + if (pdata->gpio_unbanked) + nirq = pdata->gpio_unbanked; + else + nirq = DIV_ROUND_UP(ngpio, 16); + nbank = DIV_ROUND_UP(ngpio, 32); chips = devm_kzalloc(dev, nbank * sizeof(struct davinci_gpio_controller), @@ -209,10 +221,13 @@ static int davinci_gpio_probe(struct platform_device *pdev) if (IS_ERR(gpio_base)) return PTR_ERR(gpio_base); - bank_irq = platform_get_irq(pdev, 0); - if (bank_irq < 0) { - dev_dbg(dev, "IRQ not populated\n"); - return bank_irq; + for (i = 0; i < nirq; i++) { + bank_irq[i] = platform_get_irq(pdev, i); + if (bank_irq[i] < 0) { + dev_info(dev, "IRQ not populated, err = %d\n", + bank_irq[i]); + return bank_irq[i]; + } } snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++); @@ -458,7 +473,7 @@ static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) * (dm6446) can be set appropriately for GPIOV33 pins. */ -static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) +static int davinci_gpio_irq_setup(struct platform_device *pdev, int *bank_irq) { unsigned gpio, bank; int irq; @@ -492,6 +507,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); return PTR_ERR(clk); } + ret = clk_prepare_enable(clk); if (ret) return ret; @@ -531,12 +547,12 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) if (pdata->gpio_unbanked) { /* pass "bank 0" GPIO IRQs to AINTC */ chips->chip.to_irq = gpio_to_irq_unbanked; - chips->base_irq = bank_irq; + chips->base_irq = bank_irq[0]; chips->gpio_unbanked = pdata->gpio_unbanked; binten = GENMASK(pdata->gpio_unbanked / 16, 0); /* AINTC handles mask/unmask; GPIO handles triggering */ - irq = bank_irq; + irq = bank_irq[0]; irq_chip = gpio_get_irq_chip(irq); irq_chip->name = "GPIO-AINTC"; irq_chip->irq_set_type = gpio_irq_type_unbanked; @@ -547,10 +563,11 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) writel_relaxed(~0, &g->set_rising); /* set the direct IRQs up to use that irqchip */ - for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { - irq_set_chip(irq, irq_chip); - irq_set_handler_data(irq, chips); - irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); + for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { + irq_set_chip(bank_irq[gpio], irq_chip); + irq_set_handler_data(bank_irq[gpio], chips); + irq_set_status_flags(bank_irq[gpio], + IRQ_TYPE_EDGE_BOTH); } goto done; @@ -560,7 +577,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we * then chain through our own handler. */ - for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { + for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { /* disabled by default, enabled only as needed * There are register sets for 32 GPIOs. 2 banks of 16 * GPIOs are covered by each set of registers hence divide by 2 @@ -587,8 +604,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev, int bank_irq) irqdata->bank_num = bank; irqdata->chip = chips; - irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler, - irqdata); + irq_set_chained_handler_and_data(bank_irq[bank], + gpio_irq_handler, irqdata); binten |= BIT(bank); }