From patchwork Wed Jun 6 07:38:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haren Myneni X-Patchwork-Id: 925760 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4110sZ6N1JzB3sh for ; Wed, 6 Jun 2018 17:38:42 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4110sZ573GzF2ZW for ; Wed, 6 Jun 2018 17:38:42 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=haren@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4110sV1cF4zF1yM for ; Wed, 6 Jun 2018 17:38:37 +1000 (AEST) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w567Y8UU094215 for ; Wed, 6 Jun 2018 03:38:35 -0400 Received: from e13.ny.us.ibm.com (e13.ny.us.ibm.com [129.33.205.203]) by mx0a-001b2d01.pphosted.com with ESMTP id 2jeb74ggt8-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 06 Jun 2018 03:38:35 -0400 Received: from localhost by e13.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 6 Jun 2018 03:38:34 -0400 Received: from b01cxnp22034.gho.pok.ibm.com (9.57.198.24) by e13.ny.us.ibm.com (146.89.104.200) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 6 Jun 2018 03:38:31 -0400 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w567cV6x8454648 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 6 Jun 2018 07:38:31 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F10DF28064; Wed, 6 Jun 2018 03:38:19 -0400 (EDT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C3F728058; Wed, 6 Jun 2018 03:38:19 -0400 (EDT) Received: from [9.70.82.143] (unknown [9.70.82.143]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 6 Jun 2018 03:38:19 -0400 (EDT) From: Haren Myneni To: stewart@linux.vnet.ibm.com Date: Wed, 06 Jun 2018 00:38:20 -0700 Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 X-TM-AS-GCONF: 00 x-cbid: 18060607-0064-0000-0000-0000031610E2 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009139; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000265; SDB=6.01043027; UDB=6.00534142; IPR=6.00822157; MB=3.00021491; MTD=3.00000008; XFM=3.00000015; UTC=2018-06-06 07:38:33 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18060607-0065-0000-0000-0000397F16F5 Message-Id: <1528270700.5945.33.camel@hbabu-laptop> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-06_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1805220000 definitions=main-1806060088 Subject: [Skiboot] [PATCH V3] NX: Add NX coprocessor init opal call X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The read offset (4:11) in Receive FIFO control register is incremented by FIFO size whenever CRB read by NX. But the index in RxFIFO has to match with the corresponding entry in FIFO maintained by VAS in kernel. VAS entry is reset to 0 when opening the receive window during driver initialization. So when NX842 is reloaded or in kexec boot, possibility of mismatch between RxFIFO control register and VAS entries in kernel. It could cause CRB failure / timeout from NX. This patch adds nx_coproc_init opal call for kernel to initialize readOffset (4:11) and Queued (15:23) in RxFIFO control register. Fixes: 3b3c5962f432 ("NX: Add P9 NX support for 842 compression engine") CC: stable # v5.8+ Signed-off-by: Haren Myneni --- Changelog: v2: Added doc/opal-api/opal_nx_coproc_init-167.rst v3: Format changes and corrections in opal_nx_coproc_init-167.rst Return unsupported on P7 and P8 diff --git a/doc/opal-api/opal_nx_coproc_init-167.rst b/doc/opal-api/opal_nx_coproc_init-167.rst new file mode 100644 index 0000000..b22c5a0 --- /dev/null +++ b/doc/opal-api/opal_nx_coproc_init-167.rst @@ -0,0 +1,36 @@ +.. _opal_nx_coproc_init: + +OPAL_NX_COPROC_INIT +=================== + +This OPAL call resets read offset and queued entries in high and normal +priority receive FIFO control registers. The kernel initializes read +offset entry in RXFIFO that it maintains during initialization. So this +register reset is needed for NX module reload or in kexec boot to make sure +read offset value matches with kernel entries. Otherwise NX reads requests +with wrong offset in RxFIFO which could cause NX request failures. + +The kernel initiates this call for each coprocessor type such as 842 and +GZIP per NX instance. + +Arguments +--------- +:: + + ``uint32_t chip_id`` + Contains value of the chip number identified at boot time. + + ``uint32_t pid`` + Contains NX coprocessor type (pid from the device tree). + +Returns +------- +OPAL_SUCCESS + The call to reset readOffset and queued entries for high and normal + FIFOs was successful. + +OPAL_PARAMETER + Indicates invalid chip ID or NX coprocessor type. + +OPAL_UNSUPPORTED + Not supported on P7 and P8. diff --git a/hw/nx-compress.c b/hw/nx-compress.c index 9b89664..ccd4799 100644 --- a/hw/nx-compress.c +++ b/hw/nx-compress.c @@ -21,6 +21,7 @@ #include #include #include +#include static int nx_cfg_umac_tx_wc(u32 gcid, u64 xcfg) { @@ -206,14 +207,78 @@ int nx_cfg_rx_fifo(struct dt_node *node, const char *compat, return 0; } +static int nx_init_fifo_ctrl(u32 gcid, u64 fifo_ctrl) +{ + u64 cfg; + int rc = 0; + + rc = xscom_read(gcid, fifo_ctrl, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P9_RX_FIFO_CTRL_READ_OFFSET, cfg, 0); + cfg = SETFIELD(NX_P9_RX_FIFO_CTRL_QUEUED, cfg, 0); + + rc = xscom_write(gcid, fifo_ctrl, cfg); + + return rc; +} + + +static int opal_nx_coproc_init(u32 gcid, u32 ct) +{ + struct proc_chip *chip; + u64 fifo, fifo_hi; + u32 nx_base; + int rc; + + if (proc_gen < proc_gen_p9) + return OPAL_UNSUPPORTED; + + chip = get_chip(gcid); + if (!chip) + return OPAL_PARAMETER; + + nx_base = chip->nx_base; + if (!nx_base) + return OPAL_PARAMETER; + + switch (ct) { + case NX_CT_842: + fifo_hi = nx_base + NX_P9_842_HIGH_PRI_RX_FIFO_CTRL; + fifo = nx_base + NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL; + break; + case NX_CT_GZIP: + fifo_hi = nx_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL; + fifo = nx_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL; + break; + default: + prlog(PR_EMERG, "OPAL: Unknown NX coprocessor type\n"); + return OPAL_PARAMETER; + } + + rc = nx_init_fifo_ctrl(gcid, fifo_hi); + + if (!rc) + rc = nx_init_fifo_ctrl(gcid, fifo); + + return rc; +} + +opal_call(OPAL_NX_COPROC_INIT, opal_nx_coproc_init, 2); + void nx_create_compress_node(struct dt_node *node) { u32 gcid, pb_base; + struct proc_chip *chip; int rc; gcid = dt_get_chip_id(node); pb_base = dt_get_address(node, 0, NULL); + chip = get_chip(gcid); + chip->nx_base = pb_base; + prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base); if (dt_node_is_compatible(node, "ibm,power9-nx")) { diff --git a/include/chip.h b/include/chip.h index 43b5ea5..81e435c 100644 --- a/include/chip.h +++ b/include/chip.h @@ -216,6 +216,8 @@ struct proc_chip { struct vas *vas; + /* Used by hw/nx-compress.c */ + uint64_t nx_base; /* location code of this chip */ const uint8_t *loc_code; }; diff --git a/include/nx.h b/include/nx.h index c2f7dfc..0322349 100644 --- a/include/nx.h +++ b/include/nx.h @@ -149,6 +149,7 @@ #define NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x05) #define NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0c) #define NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0e) +#define NX_P9_RX_FIFO_CTRL_READ_OFFSET PPC_BITMASK(4, 11) #define NX_P9_RX_FIFO_CTRL_QUEUED PPC_BITMASK(15, 23) #define NX_P9_RX_FIFO_CTRL_HPRI_MAX_READ PPC_BITMASK(27, 35) diff --git a/include/opal-api.h b/include/opal-api.h index df71cf2..deb2b49 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -223,7 +223,8 @@ #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165 #define OPAL_HANDLE_HMI2 166 -#define OPAL_LAST 166 +#define OPAL_NX_COPROC_INIT 167 +#define OPAL_LAST 167 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */